Download - ECE 554 Miniproject
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ECE 554 MiniprojectECE 554 Miniproject
Spring 2002www.engr.wisc.edu/ece/courses/ece554.html
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OBJECTIVESOBJECTIVES
To get familiar with the lab environment prior to the class project
To provide the basic I/O interface to the class project
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Configuration DownloadConfiguration Download
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XSV BoardXSV Board
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XSV Block DiagramXSV Block Diagram
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XSV Board: FeaturesXSV Board: Features
Xilinx Virtex FPGA (Compute)2 MB Memory (Store for Read/Write)Parallel & Serial Ports to PC
(I/O from/to Outside World)Keyboard (PS/2) PortVGA Output to VGA MonitorAudio/Video Converter
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Current SetupCurrent SetupParallel Cable
Serial Cable
NT machine running
HyperTerminal
Parallel port: Configuration downloadSerial port: Miniproject
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Asynch Serial CommunicationAsynch Serial Communication
Start bit (1 bit wide)Data bits (8 bits)Parity(None, Even, Odd)Stop bit (1 bit wide)
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Baudrate and SamplingBaudrate and Sampling
4800 and 9600 bit per secondSampling rate = x16 of the baud rate
(bit rate)Divide the clock (5 and 20 MHz) to
get the “Enable” signal (sampling rate)
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TransmittingTransmitting
Tx must be tested first.Tx shifts the “LSB” out from Tx
buffer first.Tx sends “stop bit” when there is
nothing to send.
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ReceivingReceiving
Receiver samples the RxD to get the beginning of the “start bit”
Use “resynchronization” to avoid “metastability” of any flip-flop
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Processor InterfaceProcessor Interface
Data is sent/received across the “bidirectional” data bus
Handshaking (status) signalsTBR: Transmit Buffer Ready (Empty)RDA: Receive Data AvailableCS: Chip SelectR/W_: Read or Write Bar signal
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Testbench (mock Processor)Testbench (mock Processor)
A finite state machineReceives data on the RxD and
transmits back on the TxD (echos) back to the HyperTerminal
Note that it is not provided.
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DemonstrationDemonstration
baud rate CLK4800 5 MHz4800 20 MHz9600 5 MHz9600 20 MHz