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ECE 301 – Digital Electronics
Constraints in Logic Circuit Design
(Lecture #14)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
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Spring 2011 ECE 301 - Digital Electronics 2
Logic Circuits
● Thus far, we have focused on the design of logic circuits in terms of their logical behavior only.
● When designing a logic circuit, we must also consider several real-world constraints, including:
– Noise
– Fan-out
– Fan-in
– Power consumption
– Time delay
– Transient behavior
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Spring 2011 ECE 301 - Digital Electronics 3
Representing Logic Levels
● A voltage range is specified for each logic level.
GND
VDD
V1,MIN
V0,MAX
Logic 1
Logic 0
UndefinedThreshold voltages
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Spring 2011 ECE 301 - Digital Electronics 4
Noise and Noise Margin
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Spring 2011 ECE 301 - Digital Electronics 5
Noise
● External noise sources can cause the logic gate output voltages to deviate from their expected values.
VOH
VOL
VIH
VIL
noise
● As a result, the voltages may be misinterpretted.
– An output low voltage not interpreted as a logic 0
– An output high voltage not interpreted as a logic 1
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Spring 2011 ECE 301 - Digital Electronics 6
Noise Margin
● Must select logic gates to allow the logic circuit to function properly even in the presence of noise.
● The noise margin is the amount of noise that the logic circuit can withstand while still functioning properly.
● It is a measure of the noise immunity provided by the logic circuit.
● The noise margin is defined for both logic 1 and logic 0
– NMH = VOH – VIH High noise margin
– NML = VIL – VOL
Low noise margin
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Spring 2011 ECE 301 - Digital Electronics 7
Noise Margin
GND
VDD
VIH
VIL
Logic 1
Logic 0
Undef
GND
VDD
VOH
VOL
Logic 1
Logic 0
Undef
GND
VDD
VOH
VOL
VIH
VIL
NMH
NML
Noise MarginInput Output
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Spring 2011 ECE 301 - Digital Electronics 8
Noise Margin
● The noise margin must be positive, for both logic 1 and logic 0, for the circuit to function properly.
– VOH (driver) > VIH (load)
– VOL (driver) < VIL (load)
● A negative noise margin implies that the voltage output by the driving gate will not be interpreted properly by the load gate(s).
Driver Load
VOH
VOL
VOH + noise
VOL + noise
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Spring 2011 ECE 301 - Digital Electronics 9
Example: Noise Margin
Calculate NMH and NML
when a 74LS08 drives a 74LS32.
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Spring 2011 ECE 301 - Digital Electronics 10
Example: Noise Margin
VOH, VOL
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Spring 2011 ECE 301 - Digital Electronics 11
Example: Noise Margin
VIH, VIL
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Spring 2011 ECE 301 - Digital Electronics 12
Example: Noise Margin
Gate VOH VOL VIH VIL NMH NML
LS08 2.7V 0.4V 0.7V 0.4V
LS32 2.0V 0.8V
LS08
HC32
HC32
LS08
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Spring 2011 ECE 301 - Digital Electronics 13
Example: Noise Margin
Calculate NMH and NML
when a 74HC32 drives a 74LS08.
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Spring 2011 ECE 301 - Digital Electronics 14
Example: Noise Margin
VOH, VOL
74HC32
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Spring 2011 ECE 301 - Digital Electronics 15
Example: Noise Margin
VIH, VIL
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Spring 2011 ECE 301 - Digital Electronics 16
Example: Noise Margin
Gate VOH VOL VIH VIL NMH NML
LS08
LS32
LS08
HC32
HC32 4.18V 0.26V 2.18V 0.54V
LS08 2.0V 0.8V
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Spring 2011 ECE 301 - Digital Electronics 17
Example: Noise Margin
Calculate NMH and NML
when a 74LS08 drives a 74HC32.
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Spring 2011 ECE 301 - Digital Electronics 18
Example: Noise Margin
VOH, VOL
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Spring 2011 ECE 301 - Digital Electronics 19
Example: Noise Margin
VIH, VIL
74HC32
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Spring 2011 ECE 301 - Digital Electronics 20
Example: Noise Margin
Gate VOH VOL VIH VIL NMH NML
LS08
LS32
LS08 2.7V 0.4V - 0.45V 0.95
HC32 3.15V 1.35V
HC32
LS08
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Spring 2011 ECE 301 - Digital Electronics 21
Example: Noise Margin
Gate VOH VOL VIH VIL NMH NML
LS08 2.7V 0.4V 0.7V 0.4V
LS32 2.0V 0.8V
LS08 2.7V 0.4V - 0.45V 0.95
HC32 3.15V 1.35V
HC32 4.18V 0.26V 2.18V 0.54V
LS08 2.0V 0.8V
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Spring 2011 ECE 301 - Digital Electronics 22
Fan-out
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Spring 2011 ECE 301 - Digital Electronics 23
Fan-out
To the input of n logic gates
● Fan-out is the number of logic gate inputs that can be properly driven by a single logic gate output.
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Spring 2011 ECE 301 - Digital Electronics 24
Fan-out
● Logic gates can sink and source a limited amount of current, both at the input and the output.
● These currents are defined in terms of four parameters
– IOH = output high current IIH = input high current
– IOL = output low current IIL = input low current
● These are specified in the data sheet for the corresponding logic gate.
● They differ from one logic family to another.
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Spring 2011 ECE 301 - Digital Electronics 25
Fan-out
● Fan-out is limited by the output current of the driving gate and the input current of the load gates.
● Fan-out is calculated, simply, as the ratio of the output current (of the driving gate) to the total input current (of the load gates).
● It must be calculated for both the logic 1 output (high-state) and the logic 0 output (low-state).
● Both must be considered when designing a logic circuit.
– Select the worst-case as the limit.
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Spring 2011 ECE 301 - Digital Electronics 26
Fan-out
● Low-state Fan-out =
Floor[ IOL_max
(driver) / IIL_max
(load) ]
● High-state Fan-out =
Floor[ IOH_max
(driver) / IIH_max
(load) ]
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Spring 2011 ECE 301 - Digital Electronics 27
Example: Fan-out
Calculate the fan-outwhen a 74LS08 drives one or more 74LS32.
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Spring 2011 ECE 301 - Digital Electronics 28
Example: Fan-out
IOH, IOL
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Spring 2011 ECE 301 - Digital Electronics 29
Example: Fan-out
IIH, IIL
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Spring 2011 ECE 301 - Digital Electronics 30
Example: Noise Margin
Gate IOH IOL IIH IIL FOH FOL
LS08 0.4 mA 8 mA 20 22.2
LS32 20 µA 0.36 mA
LS08
HC32
HC32
LS08
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Spring 2011 ECE 301 - Digital Electronics 31
Example: Fan-out
Calculate the fan-outwhen a 74HC32 drives one or more 74LS08.
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Spring 2011 ECE 301 - Digital Electronics 32
Example: Fan-out
IOH, IOL
74HC32
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Spring 2011 ECE 301 - Digital Electronics 33
Example: Fan-out
IIH, IIL
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Spring 2011 ECE 301 - Digital Electronics 34
Example: Noise Margin
Gate IOH IOL IIH IIL FOH FOL
LS08
LS32
LS08
HC32
HC32 4.0 mA 4.0 mA 200 11.1
LS08 20 µA 0.36 mA
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Spring 2011 ECE 301 - Digital Electronics 35
Example: Fan-out
Calculate the fan-outwhen a 74LS08 drives one or more 74HC32.
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Spring 2011 ECE 301 - Digital Electronics 36
Example: Fan-out
IOH, IOL
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Spring 2011 ECE 301 - Digital Electronics 37
Example: Fan-out
IIH, IIL
74HC32
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Spring 2011 ECE 301 - Digital Electronics 38
Example: Noise Margin
Gate IOH IOL IIH IIL FOH FOL
LS08
LS32
LS08 0.4 mA 8 mA 400 8000
HC32 1 µA 1 µA
HC32
LS08
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Spring 2011 ECE 301 - Digital Electronics 39
Example: Noise Margin
Gate IOH IOL IIH IIL FOH FOL
LS08 0.4 mA 8 mA 20 22.2
LS32 20 µA 0.36 mA
LS08 0.4 mA 8 mA 400 8000
HC32 1 µA 1 µA
HC32 4.0 mA 4.0 mA 200 11.1
LS08 20 µA 0.36 mA
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Spring 2011 ECE 301 - Digital Electronics 40
Fan-out
● Exceeding fan-out limit leads to
– Increase in output-low voltage (VOL)
● And possibly the wrong logic state
– Decrease in output-high voltage (VOH)
● And possibly the wrong logic state
– Increase in temperature
● And possible destruction of the circuit / device
– Increase in propagation delay
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Spring 2011 ECE 301 - Digital Electronics 41
for n = 1 V f
for n = 4 V f
V DD
Gnd
Time0
(c) Propagation times for different values of n
Effect of Fan-out on Gate Delay
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Spring 2011 ECE 301 - Digital Electronics 42
Electrical Constraints
● Devices in the same logic family have the same electrical characteristics.
● Devices in different logic families often have different electrical characteristics.
● In order to interconnect devices of different logic families:
– Must consider the noise margin
● voltage constraint
– Must consider the fan-out
● current constraint
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Spring 2011 ECE 301 - Digital Electronics 43
Fan-in
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Spring 2011 ECE 301 - Digital Electronics 44
Fan-in
● Fan-in is the number of inputs to a logic gate.
● It is limited by
– Silicon area
– Input capacitance
● Thus, when designing a logic circuit, we must consider the practical limit on the fan-in of the logic gates.
– Cannot assume that an n-input logic gate is available
● where n is large.
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Spring 2011 ECE 301 - Digital Electronics 45
Fan-in● As we have already seen,
– A SOP expression is most easily realized using a two-level AND-OR circuit
– A POS expression is most easily realized using a two-level OR-AND circuit
● However, if the logic circuit requires logic gates that exceed the fan-in limit, an alternate design will be necessary.
– Manipulate the Boolean expression
– Realize using a multiple-level circuit
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Spring 2011 ECE 301 - Digital Electronics 46
Example: Fan-in
Design a combinational logic circuit using 3-input NOR gates only, for the following logic function:
F(A,B,C,D) = Π M(1, 2, 6, 7, 11, 12, 13)
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Spring 2011 ECE 301 - Digital Electronics 47
Example: Fan-in
F = [b + d′ + (a + c)(a′ + c′)][a + c′ + b′d][a′ + b′ + c]
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Questions?