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Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email [email protected] and I will address this as soon as possible.
Digital Integrated Circuits(83-313)
Lecture 12:
The NanoScaled MOSFETSemester B, 2016-17
Lecturer: Dr. Adam Teman
TAs: Itamar Levi, Robert Giterman
19 June 2017
mailto:[email protected]
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Lecture Content
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Leakage in NanoScaled Transistors
3
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Leakage in Nanoscaled Transistors
• Transistors that are supposed to be off actually leak!
4
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Main Types of Leakage
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P-substrate
n+n+
Source Drain
Polysilicon Gate
Oxide
subthreshold
Ga
te
Punchthrough
GS TV V
subI e
1,gate GC
ox
I Vt
GIDL DGI V
DSVDIBL e
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Subthreshold Leakage
• When VGS
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Subthreshold Leakage
• Let’s make things easier:
• Remember that:
• And we now defined the threshold voltage according to current:
• So the edge condition requires:
• And we can now calculate subthreshold current as:
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subGS T
T
V Vn
DS
WI Const e
L
100GS T
T
V Vn
sub
WI nA e
L
100nADS GS TW
I V VL
0
sub 100nATGS T
n
DS V V
W W WI Const e Const
L L L
Subthreshold Leakage
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• An even easier way is to define the subthreshold slope:
• And Ioff, which is defined as the current when VGS=0 is:
Subthreshold Leakage
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100
100 10
GS T
T
GS T
V Vn
sub
V VS
WI nA e
L
W
L
100 10TV
Soff
WI nA
L
ln 10 1 2.3dep Tox
CkTS n
q C
Subthreshold Leakage
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Subthreshold Leakage
• So subthreshold leakage is:
• Exponentially dependent on VGS.
• Exponentially dependent on VT.
• S is the subthreshold swing coefficient.
• Optimally, (Sopt)-1=60 mV/dec
• Realistically (S)-1≈100 mV/dec
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ln10 0.06TS n
1dep
oxe
Cn
C
Subthreshold Leakage
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Subthreshold Leakage
Example:
• We want to design a transistor with:
• What is the minimum VT?
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410on
off
I
I
mV60
decS
Subthreshold Leakage
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Impact of DIBL
• DIBL causes an additional exponential increase
in subthreshold leakage with VDS.
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90nm technology.
Gate length: 45nm
Intel, T. Ghani et al., IEDM 2003
0 (1 )
GS T DS DS
t t t
V V V V
n n
subI I e e e
Subthreshold Leakage
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Subthreshold Dependence on Temperature
• This is rather complex, as mobility degrades with temperature and
other device values such as flatband voltage are temperature
dependent.
• Altogether, subthreshold leakage rises
exponentially with temperature.
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GS T
T
V V
subI e
TkT
q
Subthreshold Leakage
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Temperature Inversion
• Standard approach to temperature effect on delay:
• BUT!
• VT decreases by as much as -3mV/°C
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1
I
T
1pdt T
1T
pd T
V T
t V
pdt T
Subthreshold Leakage
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Gate Leakage
• Two mechanisms:• Direct tunneling (dominant)
• Fowler Nordheim tunneling
• Exponentially Dependent on:• Gate Voltage (VG)
• Oxide Thickness (tox).
• Non-dependent on temperature.
• Much stronger in nMOS than pMOS (higher barrier for holes)
• Minimum tox=1.2nm!!!
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Subthreshold Leakage
Gate Leakage
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Gate Induced Drain Leakage
• GIDL current flows from the drain to the substrate.
• Caused by high electric field under the gate/drain
overlap, causing e-h pair creation.
• Main phenomena is Band-to-Band Tunneling
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Subthreshold Leakage
Gate Leakage
GIDL
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Diode Leakage
• JS=10-100pA/μm2 @25°C for 0.25μm CMOS.
• JS doubles for every 9°C
• Much smaller than other leakages in deep sub-micron.
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DL SI J A
Subthreshold Leakage
Gate Leakage
GIDL
Diode Leakage
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Punchthrough
• As VDS grows, so does the drain depletion region,
and the channel length decreases.
• In severe cases, the source and drain are connected
causing non-controllable leakage current.
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rjWs
xorjWD
L +VD
rjWs
xorjWD
L++VD
e-
Subthreshold Leakage
Gate Leakage
GIDL
Diode Leakage
Punchthrough
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Leakage Summary• Subthreshold Leakage:
• IDS>0 when VGS0 due to direct tunneling through the oxide.
• Grows with VGB
• Gate Induced Drain Lowering (GIDL):• IDB>0 due to high electric field in the GD overlap region.
• Band to Band tunneling.
• Reverse Biased Diode Leakage• ISB, IDB Due to diffusion and thermal generation.
• Punchthrough:• IDS due to drain and source depletion layers touching.
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Subthreshold Leakage
Gate Leakage
GIDL
Diode Leakage
Punchthrough
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Latchup
• Latchup is more of a design problem than a leakage current.
• “Thyristors” created by parasitic BJT transistors
can turn on and short VDD and GND.
• This requires power down at the least, and
sometimes causes chip destruction.
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Subthreshold Leakage
Gate Leakage
GIDL
Diode Leakage
Punchthrough
Latchup
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Secondary Effects and Solutions
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Problem: Mobility Degradation
• Reminder: we have degraded mobility due to:
• Velocity Saturation
• Surface Scattering
• …and in general, we want more speed!
• There are a number of solutions that are currently
used or are being developed:
• Strained Silicon
• Miller Index
• Different Materials
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Mobility Degradation
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Problem: Surface Scattering
• The mobility at the surface is vertical field (VG) dependent.
• The stronger the field, the more carriers
“hit” the interface and scatter. 0
1 GS TV V
Mobility Degradation
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Solution: Strained Silicon
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Chang, IEDM 2005
Enhanced Channel Mobility
Mobility Degradation
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Solution: Improved Channel Materials
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Mobility Degradation
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Solution: Silicon Orientation
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Mobility Degradation
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Problem: Serial Resistance
• The resistance of the Source and Drain areas, especially
with Lightly Doped Drain (LDD),
can have a large impact (>15%)
on transistor conductance
)(1 0
0
tgs
sdsat
dsatdsat
VV
RI
II
0 0dsat dsat dsat s dV V I R R
K. Kuhn, IEDM 2008
Serial Resistance
Mobility Degradation
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Solution: Salicides
• Salicide = Self Aligned Silicide
• A low resistance contact is formed
on the diffusion and polysilicon
surface through annealing.
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Serial Resistance
Mobility Degradation
Source: Wikipedia
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Problem: Hot Carrier Effects
• Reminder:• Carriers in strong electric fields jump over the gate energy barrier
and get stuck in the oxide.
• This causes VT to change over time.
• Happens mainly close to the drain
where strong fields exist.
• Solution:• To solve this, Lightly Doped Drains (LDD) are used.
• The N- area reduces the field
gradient near the drain.
• N+ is needed for ohmic contacts.
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N gradient
n-n+
Serial Resistance
Mobility Degradation
Hot Carriers
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Problem: Subthreshold Leakage
• Reminder:• There is a finite number of free carriers in the channel when VGS
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Solution: MTCMOS
• A very common solution, already available in most PDKs for
many generations is multi-threshold voltage devices.• High-VT (HVT) devices are slow but have lower leakage
• Low-VT (LVT) devices are fast but very leaky
• Nominal/Standard/Regular-VT (NVT/SVT/RVT) transistors
are best for most operations.
• This approach provides an easy way to trade off
high-performance and low leakage.
• Standard cells are often designed with identical footprints in
order to exchange various VT options seamlessly.
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Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Solution: Body Biasing
• As we have previously seen, the body voltage of the transistor
affects the threshold voltage of the transistor.
• The body voltage of PMOS devices, residing in a shared NWELL
can be set without the need for special process steps.
• Changing the body voltage of NMOS devices requires the use of an
isolated PWELL (IPW) inside a Deep NWELL (DNW) area.
• The effectiveness of body biasing has thoroughly degraded with process
scaling.
• New technologies, such as Fully-depleted Ultra-thin body and buried oxide
Silicon-on-Insulator (FD-SOI or UTBB-SOI) have given this technique “new life”.
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Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Solution: Vertical Dimensions
• A better model of VT, taking into account both DIBL and Roll-Off shows a strong dependence on the transistor’s vertical dimensions:
• tox – gate thickness• Wdep – depletion width• Xj – S/D junction depth
• Reduction of each of these provides a smaller Lmin and other advantages.
• smaller tox means better transconductance.
• smaller Xj means lower S/D capacitance
• smaller Wdep means better drain-channel isolation32
0.4 dL
l
t t long dsV V V e
3d ox dep jl t W X
Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Solution: Vertical Dimensions
• Thinner oxide is the most important
aspect of scaling, as it allows better
gate control.
• Shallow junctions are achieved by:• High Substrate Doping (not wanted)
• Lightly Doped Drains (LDD)
• Metal S/D
• What about Wdep?33
3d ox dep jl t W X
Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Solution: Vertical Dimensions
• Wdep can be reduced by
“Retrograde Doping”• Reduces impurity scattering
(improves mobility).
• Wdep does not vary with VSB.• Causes a linear body effect.
• Reduces punchthrough
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data model
-2 -1 0 1 2 Vsb (V)
NFET
PFET
Vt 0
Vt0
0.6
-0.2
-0.6
0.4
-0.4
Vt (V)
0.2
Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
3d ox dep jl t W X
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Solution: Multi-gate Transistors
• To gain better control of the channel
(better subthreshold slope) use multiple gates:
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Double-gate MOSFETFinFET
Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Solution: Multi-gate Transistors
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Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot CarriersA. Planar bulk MOSFET
B. SOI MOSFET
C.Tri-gate SOI nanowire
MOSFET
D.Tri-gate Bulk FinFET
E. Tri-gate SOI FinFET
F. Pi-gate SOI nanowire MOSFET
G.Omega-gate SOI nanowire
MOSFET
H.Horizontal Gate-all-around (GAA)
nanowire MOSFET
I. Vertical GAA nanowire MOSFET
Ferain, Nature 2011
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Solution: Silicon-On-Insulator
• Silicon on Insulator (SOI) is a better
(though more expensive) way to make transistors:• Fixed depletion widths (Wdep, Xj) – lower Roll-Off/DIBL
• No body effect.
• No Punchthrough.
• Junction to substrate parasitic capacitance small.
• No latch-up between NMOS and PMOS (no substrate)
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Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Solution: Silicon-On-Insulator
• Lower diffusion capacitance:
• Raised Source/Drain for reduced resistivity.
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Serial Resistance
Subthreshold Leakage
Mobility Degradation
Hot Carriers
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Problem: Gate Leakage
• Reminder:
• Gate leakage is exponentially dependent on tox.
• A thin oxide reduces Roll-Off.
• A thin oxide provides higher transconductance (Cox)
• A thin oxide reduces the subthreshold swing:
• Major Problem:
• Oxide thickness reached 1.2nm (5 atomic layers) in 65nm.
• Gate leakage is intolerable under tox=1.5nm
• The end of scaling???
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1
ln10TS
n1
dep
oxe
Cn
C
Serial Resistance
Subthreshold Leakage
Gate Leakage
Mobility Degradation
Hot Carriers
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Solution: High-K Dielectrics
• Higher K (ε) means Cox is increased, therefore:• Transconductance is higher.
• n=1+CD/Cox is lower Better gate control.
• So we can use thicker gates to eliminate tunneling
without losing control or drive strength.
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Serial Resistance
Subthreshold Leakage
Gate Leakage
Mobility Degradation
Hot Carriers
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Solution: High-K Dielectrics
• HfO2 has a relative dielectric constant (k) of ~24, six times large than that of SiO2. • For the same EOT, the HfO2 film presents a much thicker
(albeit a lower) tunneling barrier to the electrons and holes.
• Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.
• The difficulties of high-k dielectrics:• Chemical reactions between them and the silicon
substrate and gate
• Lower surface mobility than the Si/SiO2 system
• Too low a VT for pMOS(as if there is positive charge in the high-k dielectric).
• Long-term reliability41
Serial Resistance
Subthreshold Leakage
Gate Leakage
Mobility Degradation
Hot Carriers
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Problem: Punchthrough Currents
• Reminder:
• Drain and Source depletion regions “connect”
to each other deep underneath the channel.
• Solutions:
• Halo Implants
• LDD
• Retrograde Doping
• SOI
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Serial Resistance
Subthreshold Leakage
Gate Leakage
Punchthrough
Mobility Degradation
Hot Carriers
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Solution: Halo Implants
• p+ implants suppress the
source/drain depletion regions.
• However, the also cause the
Reverse Short Channel Effect.
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Serial Resistance
Subthreshold Leakage
Gate Leakage
Punchthrough
Mobility Degradation
Hot Carriers
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Problem: Latch Up
• Reminder:
• A Thyristor is created because of voltage drop
over the substrate (or well).
• In general, cases of forward biased diodes
are often called latchup.
• Solutions:
• Body Taps.
• SOI.
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Serial Resistance
Subthreshold Leakage
Gate Leakage
Punchthrough
Latchup
Mobility Degradation
Hot Carriers
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Further Reading• J. Rabaey, “Digital Integrated Circuits” 2003, Chapters 2.5, 3.3-3.5
• Weste, Harris “CMOS VLSI Design”, Chapter 7
• C. Hu, “Modern Semiconductor Devices for Integrated Circuits”, 2010, Chapters 4-7 http://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.html
• Tzividis, et al. “Operation and Modeling of MOS Transistor” New York Press 2011. Chapters 1-5
• E. Alon, Berkeley EE-141, Lecture 9 (Fall 2009) http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/
• M. Alam, Purdue ECE-606 – lectures 32-38 (2009) http://nanohub.org/resources/5749
• A. B. Bhattacharyya “Compact MOSFET models for VLSI design”, 2009,
• T. Sakurai, “Alpha Power-Law MOS Model” – JSSC Newsletter Oct 2004
• Managing Process Variation in Intel’s 45nm CMOS Technology, Intel Technology Journal, Volume 12, Issue 2, 2008
• Berkeley “BSIM 4.6.4 User’s Manual” http://www-device.eecs.berkeley.edu/~bsim/BSIM4/BSIM464/BSIM464_Manual.pdf
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