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Flip Flops
prepared by : Eng. Rania Elsadig
Sudan University of science and Technology
College of Engineering Biomedical Engineering
DepartmentDigital Design II
Third year
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Clock Signal
Sequential logic circuits have memory Output is a function of input and present stateSequential circuits are synchronized by a periodic “clock” signal
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SR Flip Flop
SR (set-reset) flip-flop based on two nor gates
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SR Flip Flop
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Edge triggered flip-flop changes only when the clock C changes
Edge Triggered Flip Flop
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ExerciseFor a given S and R inputs to SR flip-flop, sketch the output signal Q
Q
t
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Exercise
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Positive Edge Triggered D Flip Flop
Positive-edge triggered flip-flop changes only on the rising edge of the clock C
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Positive Edge Triggered D Flip Flop Cont.
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ExerciseThe input D to a positive-edge triggered flip-flop is shownFind the output signal Q
Q
t
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Exercise
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Positive Edge Triggered JK Flip Flop
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D = J Q' + K' Q
Positive Edge Triggered JK Flip Flop Cont.
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T ( Toggle) Flip Flop
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D = T Q = T Q' + T' Q+
T ( Toggle) Flip Flop Cont.
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D flip-flop with asynchronous reset
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17
Master-slave D-type flip-flop
D Q
CLK
Input
Master D latch
D Q Output
Slave D latchX
• How to make into negative edge-triggered D-type flip-flop?
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Analysis of Clocked Sequential Circuits
State diagrams:• How do we characterize logic circuits?– Combinational circuits: Truth tables – Sequential circuits: State diagrams
• First draw the states– States Unique circuit configurations
• Second draw the transitions between states– Transitions Changes in state caused by inputs
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Example1: A Sequential Circuit with D Flip Flops
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State Table for the Circuit (ex1)
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State Diagram for the Circuit (ex1)
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Example2: A Sequential Circuit with D Flip Flops
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example3: A Sequential Circuit with JK Flip Flops
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State Table & Diagram for the Circuit (ex3)
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example4: A Sequential Circuit with T Flip Flops
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State Table for the Circuit (ex4)