Designing CMOS Wireless System-on-a-chip
– analog/RF perspective
David Su, [email protected]
Qualcomm Atheros, San Jose, California
Japan, Nov 2011
(c) D. Su, 2011 Japan
Outline
• System-on-a-Chip Overview– Transceiver Building Blocks
– Integration issues
• System-on-a-Chip Example:– A 1x1 802.11n WLAN SoC
– Terrovitis et al, 2009 ESSCirC
• Conclusion
p.2
(c) D. Su, 2011 Japan
SoC Trends: WLAN (1996)
Prism WLAN chipset (Harris Semi) AMD App Note (www.amd.com)
Multi-Chip 802.11b Transceiver
p.3
SwitchDigitalSignal
Processor
Synthesizer
LOI
LOQ
LOI
LOQ
LO
LNA
RFVGAPA
ADC
ADC
DAC
DAC
Su et al ISSCC 2002 (Atheros)Mehta et al ISSCC 2005 (Atheros)Chang et al ISSCC 2007 (Atheros)
WLAN Integration Story
(c) D. Su, 2011 Japan p.4
Soc Trends: WLAN (2011)
(c) D. Su, 2011 Japan
Abdollahi-Alibeik et al, ISSCC 2011 (Atheros)
3x3 802.11n MIMO Solution(1 of 3 chains shown)
p.5
Advantages of SoC Integration
• Increased functionality
• Smaller Size / Form Factor
• Lower Power – On-chip interface
• Lower Cost– Single package
– Ease of manufacture• Minimum RF board tuning
• Reduced component count ���� Improved reliability
(c) D. Su, 2011 Japan p.6
Cost of WLAN Throughput
Zargari, 2007 VLSI Symposium Short Course
(c) D. Su, 2011 Japan p.7
(c) D. Su, 2011 Japan
1
10
100
1000
1996 1998 2000 2002 2004 2006 2008
Ma
x P
HY
Da
ta R
ate
(M
b/s
)
Year of Product Introduction
802.11 (2.4GHz)
802.11b (2.4GHz)
802.11a (5GHz)
802.11g (2.4GHz)
802.11n (2.4 and 5GHz)
Evolution of 802.11 WLAN PHY Rates
p.8
Wireless SoC Block Diagram
SwitchDigitalSignal
Processor
Synthesizer
Receiver LOI
LOQ
LOI
LOQ
LO
LNA
RFVGAPA
Transmitter
ADC
ADC
DAC
DAC
(c) D. Su, 2011 Japan p.9
Low Noise Amplifier
• Low Noise Figure– Sufficient gain
• Able to accommodate large blockers– Large Dynamic Range– Large Common-mode Rejection– High Linearity
(c) D. Su, 2011 Japan p.10
LNA with Cascoded Diff Pair
• Input match• Noise Figure
BIAS
IN IN
(c) D. Su, 2011 Japan p.11
Zargari et al, JSSC Dec 2004 (Atheros)
LNA with Switchable Gain
• CMRR at RF• Switchable gain for high DR
BIAS
IN IN
gain
M1 M4
gain
gain
M2 M3
(c) D. Su, 2011 Japan p.12
Power Amplifier
General Specifications
� Output power: Saturated power, P1dB
� Efficiency
� Linearity: OIP3/IM3, Harmonics
� Stability/Robustness: VSWR
Digital Communications
� Large Peak to Average Ratio ���� linearity
� Transmit Spectral Mask – modest linearity
� Error Vector Magnitude (EVM) – high linearity
(c) D. Su, 2011 Japan p.13
� Information encoded in both amplitude and phase
(c) D. Su, 2011 Japan p.14
Cascoded Power Amplifier
� Cascoding advantages
�3.3V supply voltage
�Stability
� Capacitive Level-shift
� Differential
�Off-chip balun
RFIN
RFOUT
Bias
M2
Single-ended equivalent
M1
L1 L2
VDD
Su et al, ISSCC 2002 (Atheros)
(c) D. Su, 2011 Japan p.15
Cascoded Power Amplifiers
Zargari et al, JSSC Dec 2002 (Atheros)
RFINRFIN
Bias1Bias1
RFOUT
Bias2
RFOUT
Bias2
PMAX = 22 dBm POFDM = 17.8 dBm (BPSK)
(c) D. Su, 2011 Japan p.16
Measured Power vs Data Rate
6 9 12 18 24 36 48 54
12
14
16
18O
FD
M O
utp
ut
Po
we
r (d
Bm
)
Data Rate (Mbps)
10
Spectral mask limited EVM limited
IEEE 802.11aOFDM Data
4-6dB Power Backoff
10-12 dB Power Backoff
(c) D. Su, 2011 Japan p.17
System-on-a-Chip Integration
� Digital Assistance: Calibration Techniques
• Digital Interference: Noise Coupling
Analog/RF
DIGITAL
(c) D. Su, 2011 Japan p.18
Digital Assisted Analog/RF Design
Digital Designer
(c) D. Su, 2011 Japan p.19
Digital Assisted Analog/RF Design
• Using digital logic to compensate/correct for imperfections of analog and RF circuits to enable:– Lower power,– smaller area, – improved reliability of analog/RF
���� resulting in lower cost and improved performance
(c) D. Su, 2011 Japan p.20
Digital Assistance: Calibration Issues
• Desired properties of calibration: – Independent of temperature, aging, frequency– Inexpensive (in time, area and power) to implement– Do not interfere with system performance
• Wireless System-on-a-Chip advantage:– Calibration building blocks already exist on-chip:
transmitter and receiver, data converters, and CPU– No package pin limitation
(c) D. Su, 2011 Japan p.21
Calibration Techniques
� Test Signal
– Dedicated test signals from DAC: Tx carrier leak
– RF loop back: Receive filter bandwidth
– Thermal noise: Rx Gain
– Live Rx (signal) traffic: Rx I/Q mismatch
� Observation Signal
– Dedicated ADC
– Implicit ADC: Comparator
� Tuning Mechanism
– Dedicated DAC
– Implicit DAC: Selectable capacitors, resistors, transistors
– Digital tuning (if signal is already digital)
(c) D. Su, 2011 Japan p.22
RF loop back: Tx Carrier Leak
• Test signal: Tx DAC
• Observation signal: RF loop back to Rx ADC
• Tuning: Carrier Leak Correction at Tx DAC input
LO
PA
DAC
DigitalBaseband
TX
LNA
ADC
LO
RX+
+
Carrier LeakCorrection
(c) D. Su, 2011 Japan p.23
Calibrating Low-pass gm-C Filter
Zargari et al, JSSC Dec 2004
Low-QBiquad
High-QBiquad
TransresistanceAmplifier
Capacitor setting
IN OUT
Iin
gm1
-gm2
gm3gm4
Iout
ReplicaBiquad
PhaseDetector
StateMachine
Ref Clock
(c) D. Su, 2011 Japan p.24
System-on-a-Chip Integration
• Digital Assistance: Calibration Techniques
� Digital Interference: Noise Coupling
Analog/RF
DIGITAL
(c) D. Su, 2011 Japan p.25
Digital Interference
Analog
Digital
(c) D. Su, 2011 Japan p.26
Digital Interference: Noise Coupling
Aggressor
Victim
Accomplice
(c) D. Su, 2011 Japan p.27
Noise Source
Pacify the aggressor
• Reduce noise by turning off unused digital– Clock gating
– Avoid oversized digital buffers
• Stagger digital switching– Avoid large number of digital pads switching
simultaneously
– Avoid switching digital logic at the same sampling instance of sensitive analog
(c) D. Su, 2011 Japan p.28
Noise Destination
Strengthen the victim
• Increase immunity of sensitive analog and RF circuits– Common-mode noise rejection���� Fully differential topology
– Power Supply noise rejection���� Good PSRR���� Dedicated on-chip voltage regulators
• Avoid package coupling by keeping sensitive nodes on chip (Example: VCO control voltage)
(c) D. Su, 2011 Japan p.29
Coupling Mechanism
Deter the accomplice
• Power Supply noise coupling– Separate or star-connected power supplies
• Capacitive or inductive coupling to sensitive signals and bias voltages– Careful routing of signal traces to reduce parasitic
capacitive/inductive coupling
– Use ground return-path shields
• Substrate coupling induced VTH modulation– Low-impedance substrate connection
– Guard rings
– Physical separation
– Deep Nwell(c) D. Su, 2011 Japan p.30
Frequency Synthesizer
Terrovitis et al, ISSCC 2004 (Atheros)
DFFRefDiv
P & S Counter
DFF8/8.5Div
16/17 Divider
PFD CP
On-chip Loop Filter
fvco/4I Q
LO Buffers
Xtal Osc
40MHz
/ 2
Reg1 Reg2
Retiming FFs
VCO
(c) D. Su, 2011 Japan p.31
A 1x1 802.11n WLAN SoC with fully integrated RF Front-end Utilizing PA
Linearization
Manolis Terrovitis, Michael Mack, Justin Hwang, Brian Kaczynski, Gabriel Tseng*, Bor-Chin Wang*, Srenik Mehta, David Su
Atheros Communications, Santa Clara, California
*Atheros Communications, Hsinchu, Taiwan
From presentation by Dr. Manolis Terrovitis at the 35th European Solid-State Circuits Conference in Athens on September 16, 2009
(c) D. Su, 2011 Japan
SoC Design Goals
• Design a low cost, small form factor, and high performance 802.11 system
• Eliminate external components (Power Amplifier, Low-Noise Amplifier, Transmit/Receive switch)
• Power Amp Linearization for maximum transmit linear output power and efficiency
Terrovitis et al, ESSCIRC 2009 (Atheros) p.33
(c) D. Su, 2011 Japan
SoC Block Diagram
PA
PA
Linearization
VGA2 VGA1
LNA2ADC & DAC
MA
C
PC
Ie
Antenna2
SYNTH
Antenna1
LNA1
VGA
BB I
LOQLOI
BB Q
BA
SE
BA
ND
Ref: Zargari et al, Dec. 2008, JSSC.
Terrovitis et al, ESSCIRC 2009 (Atheros)
PA
PA
Linearization
VGA2 VGA1
p.34
(c) D. Su, 2011 Japan
Combined RF Frontend
Terrovitis et al, ESSCIRC 2009 (Atheros)
•PA, LNA, T/R Switch•Large swing•Low impedance
p.35
M5
LNAOUT
bias2
L1
L1
PAINM1
M3 bias1
RFIO
(c) D. Su, 2011 Japan
Combined RF Frontend
RFIO
X
L1
RFIO
X
L2
PAIN
M1
M3
PAIN
M2
M4 b1b1
TX
M5
LNAOUT
M6
LNAOUT
b2b2
RX
RX
Terrovitis et al, ESSCIRC 2009 (Atheros) p.36
Linearized RF Power Amp
Transistors are cheap on an System-on-a-Chip
• Use linearization technique to improve linearity and efficiency of the Power Amplifier
(c) D. Su, 2011 Japan p.37
Envelope Feedback
RFOUT
PARFIN
Envelope detector
Error Amp
• Linearizes Gain
• Fixes Gain over process and temperature
Vc
(c) D. Su, 2011 Japan p.38
(c) D. Su, 2011 Japan
Envelope FB Linearization Issues
• Phase distortion is not corrected
• Envelope detectors do not respond for low signal
– Loop opens at low amplitude
– Offset Correction
|RFIN|
Gain
ClosedLoop
OpenLoop
Terrovitis et al, ESSCIRC 2009 (Atheros) p.39
(c) D. Su, 2011 Japan
PA driver PARF Gain
Offset DAC
Vc Monitor &Gain Control State Machine
Error Amp
Mixer
Vc
Envelope detector
Implemented Feedback Loop
Terrovitis et al, ESSCIRC 2009 (Atheros) p.40
RFOUT
RFIN
(c) D. Su, 2011 Japan
RFINM1
ENVOUT
RFIN M2
S
M3
M4CLOAD
bias
Fast Envelope Detector
Terrovitis et al, ESSCIRC 2009 (Atheros) p.41
(c) D. Su, 2011 Japan
PA Driver with Variable Load
bias
Vcas
RFINRFIN
RFOUT RFOUT
Vc
Terrovitis et al, ESSCIRC 2009 (Atheros) p.42
(c) D. Su, 2011 Japan
Sensitivity Measurements
System NF (LNA1/LNA2) = 5.5dB / 3.5dB
Legacy 54Mbps Sensitivity
-79
-78
-77
-76
-75
-74
0 5 10 15
Channel
Se
ns
itiv
ity (
dB
m)
LNA2 LNA1
Data Rate Sensitivity
LNA1/LNA2
(dBm)
CCK 1Mbps -97/-99
11g 54Mbps -76/-78
HT20 65Mbps -73/-75
HT40 135Mbps -69/-71.5
Terrovitis et al, ESSCIRC 2009 (Atheros) p.43
(c) D. Su, 2011 Japan
Output Power Measurements
PSAT = 26.5 dBm at the antenna
20
22
24
26
28
30
32
34
36
2 4 6 8 10 12 14 16 18 20
HT20 TX Power (dBm)
EVM
(-
dB
) .
Linearization ON Linearization OFF
65 Mbps spec 5.5 dB
6 dB
Terrovitis et al, ESSCIRC 2009 (Atheros) p.44
(c) D. Su, 2011 Japan
Maximum EVM and Mask Compliant Power vs Data Rate
12
14
16
18
20
22
6 9 12
18
24
36
48
54
58.5 65
81
108
121.5
135
Data Rate (Mbps)
Outp
ut Pow
er (d
Bm
) _
Linearization OFF Linearization ON
HT20 HT40
11g
Max EVM and Mask Compliant Power vs Data Rate
Terrovitis et al, ESSCIRC 2009 (Atheros) p.45
(c) D. Su, 2011 Japan
Chip Micrograph
• 0.13µµµµm CMOS
• 68 pin QFN package
• 19mm2 Silicon Area
• Current Consumption from 3.3V
– RX: 210mA
– TX: 455mA @ Pout=18.4dBm, HT20, EVM=-28dB
Terrovitis et al, ESSCIRC 2009 (Atheros) p.46
Conclusions
• CMOS has become the technology of choice for integrated radio systems
• Integrating a radio in mixed-Signal System-on-a-Chip is no longer a dream but a reality
• Wireless SoC can provide significant advantages in size, power, and cost
(c) D. Su, 2011 Japan p.47
Continuing Challenges
• Multi-mode radios to support several wireless standards
• RF design in scaled CMOS– Reduced supply voltage: voltage, current, time…– nanometer transistors: leaky, low gm.ro– How to reduce area and power– More “digital assistance”
• Challenges of radio designers have been, are, and will continue to be:– Power consumption / Battery life– Range – Data rate– Cost
(c) D. Su, 2011 Japan p.48
Acknowledgments
• Many of the slides are based on previous presentations from Qualcomm Atheros and Stanford University, especially those by:
Masoud Zargari,Manolis Terrovitis, Srenik Mehta, William Si, William McFarland, Lalitkumar Nathawad Richard ChangAmirpouya Kavousian
(c) D. Su, 2011 Japan p.49