-
Design considerations Design considerations for LPDDR4/3 PHY and controller for LPDDR4/3 PHY and controller for LPDDR4/3 PHY and controller for LPDDR4/3 PHY and controller sub systemsub system
Kishore Kasamsetty, Jeffrey Chung
Cadence Design Systems
Mobile Forum 2014Copyright © 2014 Cadence Design Systems
-
Considerations for dual mode Considerations for dual mode LPDDR3/4 designsLPDDR3/4 designs
Items LPDDR4 LPDDR3 Comments
Channels per die 2 1
Data bus width/channel 16b 32b
Min BL per RD 16 8
Min data block size 32B 32BMin data block size 32B 32B
CA bus width/channel 6b 10b 2-tick CMD for LPDDR4
Max DQ data rate 4266 Mbps 2133 Mbps DDR for both
Max CA data rate 2133 Mbps 2133 Mbps SDR vs. DDR
PoP PKG One channel in same corner of PKG
CA & DQ for one channel in opposite side of PKG
Signaling GND-terminated UnterminatedCenter-terminated
-
Considerations for dual mode Considerations for dual mode LPDDR3/4 designsLPDDR3/4 designs
Items LPDDR4 LPDDR3 Comments
Channels per die 2 1
Data bus width/channel 16b 32b
Min BL per RD 16 8
Min data block size 32B 32B Command channelMin data block size 32B 32B
CA bus width/channel 6b 10b 2-tick CMD for LPDDR4
Max DQ data rate 4266 Mbps 2133 Mbps DDR for both
Max CA data rate 2133 Mbps 2133 Mbps SDR vs. DDR
PoP PKG One channel in same corner of PKG
CA & DQ for one channel in opposite side of PKG
Signaling GND-terminated UnterminatedCenter-terminated
Command channel
Physical design
-
LPDDR4/3 command channel LPDDR4/3 command channel differencesdifferences
How do controller and PHY switch from using two independent x16 command channels to a single x32 channel ?
-
PoP PKG Ballout ComparisonPoP PKG Ballout Comparison
DQ_0
DQ
_0
DQ
_0D
Q_1
CA
_1
DQ
_1
CA_3DQ_3
DQ
_3
CA_2 DQ_2
DQ
_2
CA_0
LPDDR3
CA & DQ on opposite side
CA_0DQ_0
DQ
_
LPDDR4
CA & DQ on same side
DQ_1C
A_1
CA_1 DQ_1
DQ
_
What are the tradeoffs in PHY placement when a single SOC die needs to work for both ballouts?
-
LPDDR4/3 dual mode conceptLPDDR4/3 dual mode concept
MC
CMDqueue,
x16/x32
Bu
s F
ab
ric LPDDR4/
LPDDR3 x32 DRAM
16 DQ
12/10 CA
32/10 16/10
Lo
ad
Ba
lan
ce
r
CMD
PHY
IO
.
X16 PHYLPDDR4/3
X16 PHY
16/6
• LPDDR4 (two channels, 32 byte access)– Can fully exploit parallelism in LPDDR4 device
• LPDDR3 (single channel, 32 byte access)
Bu
s F
ab
ric
16 DQDFI
MUX
16/6 16/6
Lo
ad
Ba
lan
ce
r
CMD queue
x16
X16 PHYLPDDR4/3 16/6
-
LPDDR4/3 dual mode conceptLPDDR4/3 dual mode conceptLPDDR4 mode (two channels, 32 byte access)LPDDR4 mode (two channels, 32 byte access)
MC
CMDqueue,
x16/x32
Bu
s F
ab
ric LPDDR4
x32 DRAM
16 DQ
12/10CA
32/10 16/10
Lo
ad
Ba
lan
ce
r
CMD
PHY
IO
.
X16 PHYLPDDR4/3
X16 PHY
16/6
• Both controller queues in operation in x16 mode
• DFI mux disabled
• Inter PHY communication disabled
Bu
s F
ab
ric
16 DQDFI
MUX
16/6 16/6
Lo
ad
Ba
lan
ce
r
CMD queue
x16
X16 PHYLPDDR4/3 16/6
-
LPDDR4/3 dual mode conceptLPDDR4/3 dual mode conceptLPDDR3 mode (single channel, 32 byte access)LPDDR3 mode (single channel, 32 byte access)
MC
CMD
queue,
x16/x32
Bu
s F
ab
ric LPDDR3
x32 DRAM
16 DQ
16 DQ
12/10
CA
DFI 16/6
32/10
16/6
16/10
Lo
ad
Ba
lan
ce
r
CMD queue
x16
PHY
IO
.
X16 PHYLPDDR4/3
X16 PHYLPDDR4/3
16/6
16/6
• Master CMD queue in 32 bit mode
• Other command queue disabled
• DFI mux active
• X16 bit PHY need inter communication (training)
DFI MUX
16/6 16/6x16
-
Simpler LPDDR4/3 system Simpler LPDDR4/3 system 64 byte access size64 byte access size
• Systems with 64B minimum access size can implement a much simpler dual mode system
• LPDDR4 mode : Operate both channels in lock • LPDDR4 mode : Operate both channels in lock step, same command on both 64 byte access size
• LPDDR3 mode : Single channel, 64 or 32 byte access size
-
Simpler LPDDR4/3 system Simpler LPDDR4/3 system 64 byte access size64 byte access size
PHY
IO
.
MC
CMDqueue
X32
Bu
s F
ab
ric
X32 PHYLPDDR4/3
LPDDR4/ LPDDR3
x32 DRAM32/12
32/10
16 DQ
16 DQ
12/10 CA
• MC always operates as single channel x32
• Command replication in LPDDR4 mode (Glue logic or phy_top)
• Passes thru in LPDDR3 mode
16 DQ
-
Simpler LPDDR4/3 system Simpler LPDDR4/3 system 64 byte access size64 byte access size
PHY
IO
.
MC
CMDqueue
X32
Bu
s F
ab
ric
X32 PHYLPDDR4/3
LPDDR4/ LPDDR3
x32 DRAM32/12
32/10
16 DQ
16 DQ
12/10 CA
• Benefits– Single command queue – smaller MC
– Simpler MC-PHY communication
– Simple PHY with IO replication in LPDDR4 mode
– Suited for legacy systems moving to LPDDR4
16 DQ
-
Physical design implications Physical design implications with PoP and Discrete PKGwith PoP and Discrete PKG
• PoP and discrete package ballout for LPDDR4 is quite different than that of LPDDR3
– To allow single SoC design to support both – To allow single SoC design to support both LPDDR4 and LPDDR3, one must accept PKG routing complexity
– Same SoC die with different package design is practical
– Similar issues exist for supporting PoP and Discrete PKG from the same SoC design
-
LPDDR3 focused SoC PKG LPDDR3 focused SoC PKG designdesign
DQ_0
DQ
_0
DQ
_P
HY
_C
DQ_PHY_A DQ_PHY_B
CA
_P
HY
_D
DQ
_P
HY
_C
DQ_PHY_A DQ_PHY_B
CA
_P
HY
_D
CA_0 CA_0DQ_0
DQ
_0
LPDDR3 focused physical design does not work for LPDDR4 POP !!
DQ
_P
HY
_C
DQ_PHY_DCA_PHY
_ACA_PHY
_B CA
_P
HY
_C
CA
_P
HY
_D
DQ_PHY_DCA_PHY
_ACA_PHY
_B CA
_P
HY
_C
CA
_P
HY
_D
-
LPDDR4 focused SoC PKG LPDDR4 focused SoC PKG designdesign
DQ_0
DQ
_0
DQ
_0
PHY_A PHY_BPHY_A PHY_B
• LPDDR4 optimized placement can work for LPDDR3• Still need long routes in package and Soc for LPDDR3• Per bit deskew capabilities in CA and DQ can be handy
CA_0 CA_0DQ_0
DQ
_0
PHY_C PHY_DPHY_C PHY_D
-
Controller and PHY IP Controller and PHY IP TechniquesTechniques
• DRAM Controller and PHY IP may employ techniques to ease the burden and provide package/PCB routing flexibility for multi-modefor multi-mode
– Per bit deskew on CA bus
– CA bit swapping
– Dual-mode (SDR and DDR) support for CA
-
SummarySummary
• Command bus differences and POP/discrete package ballout differences make multi mode LPDDR3/4 challenging
• Optimization to system intent and capabilities can lead to practical implementations
• Cadence offers integrated LPDDR4 controller + PHY + memory models IP that address these issues