Download - Delta Tester 9424 Training Module
July 2008 1
www.fairchildsemi.com
July 2008 1
THERMAL RESISTANCE ΔVBE / ΔVDS TESTER
MODEL 9424-KTB/L 9425-PUB
James A. Ochea
TF2 Equipment Technician I
2
VBE1 VBE2
POWER TIME
VBE
+
-
D
S
-5V
IDS
IM
300Ω
PRESENTATION OUTLINE
INTRODUCTION
OPERATION PANEL
DV240-PU FRONT & REAT PANEL
FUNDAMENTAL MEASUREMENT CIRCUIT
∆VBE / ∆VDS TIMING DIAGRAM
FLOW CHART
RESOURCE BOARDS ASSIGNMENT
CONTACT CHECK DETECTION
3
Overview
DV240 is an automatic test system designed to evaluate a full range of discrete
devices from small signal to high power transistors (NPN/PNP), Darlingtons, and MOSFETs
(N-channel/P-channel). The system operates by forcing a power pulse to the
device and then displays a digital readout of the variation of base to emitter voltage ΔVBE or
ΔVDS in the case of FET before and after the pulse was applied.
DV240 can be used for both manual testing and automatic testing using handlers.
A real time parallel testing of both DC parameters and thermal impedance can achieved by
coupling with TESEC DC testers, where high level programming of limits and binning
information can be accomplished through the larger system’s computer.
Besides thermal resistance applications, such as evaluating die attachment, the
tester can be used to obtain data for determining safe operating area. A device protection
circuit is built-in to cut-off power when avalanche occurs.
INTRODUCTION
4
Features
- Fast and accurate ΔVBE / ΔVDS measurement.
- Display of both ΔVBE1 / ΔVDS1 and ΔVBE or ΔVDS is achieved.
- A special contact check function prevents the wrong measurement
and mis-binning due to contact failure.
- Oscillation detection function prevents the wrong measurement and
mis-binning due to oscillations
- Digitalized operation & high speed data logging.
- Tester can be controlled externally through IEEE-488 I/F
- Interfaces with the DC testers and handlers.
- Standardized to 19 inch cabinet rack.
INTRODUCTION
5
SpecificationsMeasurement range
Polarity : PNP/NPN, P-MOSFET/N-MOSFET
Pretest : Contact check, B-E open and short tests
Measurement range : ΔVBE1 or ΔVDS1 0000~4095 mV
ΔVBE or ΔVDS 0000~1999 mV
(measurement accurate to ±2% or ±3 mV
– whichever is greater)
INTRODUCTION
Item Range Step Accuracy Digit
Forcing Current IE / IDS 00.01~39.99A 10mA ± (1 + 2mA) 4
Sensing Current IM 01~99 mA 1mA 01~39mA (± 1.5 %)
40~99mA(± 3 %)
2
Gate Limit Voltage
Gate-L
01.0~19.9V
(Fix value of ± 12V is also possible)
0.1V ± 5V 2 ½
Power Dissipation Time PT 100 µs~9.99 s 1µs (Crystal) 3
Delay Time DT 010~999 µs 1µs ± 3µs ( Crystal) 3
Upper Limit / Lower Limit 0000~1999 mV 1mV Digital Comparison 3 ½
VCB / VDS 001~199 V 1V ± (0.02 % + 0.1V) 3
Range of Settings
6
Forcing Power Range Diagram
800W (100ms)
600W (9.99s)
39.99
30
8
6
4
3
20 100 199
IE / IDS
(A)
VCB / VDS (V)
7
Fundamental Measurement Circuit
ΔVBE Test Circuit (NPN TR)
-64V
IM
-64V
IE
-64V
IM
∆VBE=VBE1-VBE2
VBE1 POWER VBE2
VBE1 VBE2
NOTE:
Device is turn ON before Power Time since IM is already present during 1st sampling (VBE1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.
VCB VCB VCB
8
Fundamental Measurement Circuit
ΔVDS Test Circuit (N-MOS FET)
∆VDS=VDS1-VDS2
VDS1 POWER VDS2
+64V
-5V
ONVDS1
IM
+64V
-5V
ONVDS2
IM
+64V
+
-
-5V
IDS
IM
250Ω
NOTE:
Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.
VDS
250Ω250Ω
9
Fundamental Measurement Circuit
ΔVGS Test Circuit (N-IGBT)
∆VGS=VGS1-VGS2
VGS1 POWER VGS2
- 64V
+
-
-5V
IM
250Ω
NOTE:
Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.
VDS
- 64V
+
-
-5V
IM
250Ω
VDS
ID
- 64V
+
-
-5V
IM
250Ω
VDS
VGS1 VGS1
10
Fundamental Measurement Circuit
ΔVCE Test Circuit (N-IGBT)
∆VCE=VCE1-VCE2
VCE1 POWER VCE2
NOTE:
Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.
- 64V
+
-
+15V
IM
250Ω
VCE
ID
-64V
IM
VCE1
+15V
250Ω
-64V
IM
VCE2
+15V
250Ω
11
Fundamental Measurement Circuit
ΔVF Test Circuit (N-DIODE)
∆VF=VF1-VF2
VF1 POWER
NOTE:
Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.
+64V
IM
VF1
+64V
IMID
+64V
IM
VF2
C
E
C
E E
C
VF2
12
ΔVBE Test Timing (NPN TR/PNP TR)
VCB
IM ON
VCB ON
IE ON
S/π
VBE1 VBE2
POWER TIME
VBE
10us (fix)
16ms
DELAY TIME
POWER TIME
13
ΔVDS Test Timing
VDS1 VDS2
POWER TIME
DRAIN
VDS ON
IDS ON VGATE ON
S/π
0V
-5V
SOURCE
GATE
POWER TIME
DELAY TIME
10us (fix)
14
ΔVGS Test Timing (N-IGBT/P-IGBT)
VGS1 VGS2
POWER TIME
VCB
S/π
SOURCE
sample (10us fix)
POWER TIME
DELAY TIME
IM ON
VCB ON
IE ON
(SAMPLE HOLD)
15
ΔVCE Test Timing (N-IGBT)
VCE1 POWER TIME
COLLECTOR
S/π
POWER TIME
DELAY TIME
10us (fix)
-15V
EMITTER
GATE
DT
VCE ON
IC ON
VG ON
(SAMPLE HOLD)
VCE2
16
ΔVF Test Timing (N-DIODE)
VF1
POWER TIME
EMITTER
S/π
POWER TIME
DELAY TIME
10us (fix)
VF2
DT
IM ON
IE ON
(SAMPLE HOLD)
17
RESOURCE BOARDS ASSIGNMENT
PT9131 – VCB control board
PT9404 – IM board
PT9406 – IC limit
PT9117 – IE GEN
PT9403 – Resistor Board
CP8751B – Controller Board
CP8744 – Resistor Board
CP8742 – VG Gen
CP8745 – IS Generator
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Flow Chart
Test Start
Test Condition Load
Contact Check
VBE1 Read
VBE1 < 0.2V
VBE1 > 3V
Power Forcing
VBE Read
A
CONTF
OPEN
SHORT
B
Yes
Yes
No
No
Reject Indicator
Result Indicator
LEGEND:
H-Up CheckYes
No
Yes
AVAL
No
1
3
4
1
When an avalanche is detected, power forcing is cut-off at high speed
and “AVAL” is displayed
When VBE1 < VBE2, “ERROR” is displayed
2
3 & 4 The following sheet is default value when it is initially shipped from the
vendor.
19
Flow Chart Continuation
Oscillation
Error
Upper Limit < ΔVBE
A
Yes
Yes
Yes
OSCILLATION
ERROR
HIGH
No
No
No
ΔVBE < Lower Limit
LOW
PASS
END
B
Yes
No
2
20
HANDLER Connectors (pin arrangement)
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 -
2 LOW-L 9 GND
3 HIGH-L 10 SHIELD
4 REJECT-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 1
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 -
2 - 9 GND
3 FAIL-L 10 SHIELD
4 - 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 2
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
21
HANDLER Connectors (pin arrangement)
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 -
2 OPEN-L 9 GND
3 REJECT-L 10 SHIELD
4 HIGH-L or LOW-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 3
(For the tester of P-ROM version “-02.C” or later)
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 CONTF-L
2 LOW-L 9 GND
3 HIGH-L 10 SHIELD
4 REJECT-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 4
(For the tester of P-ROM version “-01.J” or later)
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
22
HANDLER Connectors (pin arrangement)
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 -
2 OPEN-L/SHORT-L 9 GND
3 REJECT-L 10 SHIELD
4 HIGH-L or LOW-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 5
(For the tester of P-ROM version “-02.D” or later)
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 CONTF-L
2 OPEN-L 9 GND
3 SHORT-L 10 SHIELD
4 REJECT-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 6
(For the tester of P-ROM version “-02.E” or later)
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
23
HANDLER Connectors (pin arrangement)
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 -
2 CONTF-L/OSC-L 9 GND
3 OPEN-L/SHORT-L 10 SHIELD
4 REJECT-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 7
(For the tester of P-ROM version “-02.F” or later)
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 -
2 OPEN-L/SHORT-L 9 GND
3 REJECT-L 10 SHIELD
4 HIGH/LOW-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
HANDLER 8
(For the tester of P-ROM version “-02.U” or later)
“-L” indicates a low true.
Nos. 13 & 14 are not provided for SD-1612A
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HANDLER Connectors (pin arrangement)
HANDLER 9
(For the tester of P-ROM version “-03.O” or later)
“-L” indicates a low true.
“AVAL1” indicates AVAL (GATE LIMIT)
Nos. 13 & 14 are not provided for SD-1612A
“AVAL2” indicates AVAL (0.2V detect, IC Limit)
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 PASS-L 8 CONTF-L
2 OPEN-L/AVAL1-L 9 GND
3SHORT-L/AVAL2-
L 10 SHIELD
4 REJECT-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
25
USER (for the 9424-KT/L tester)
“-L” indicates a low true.
HANDLER57GE- 40140-751 (DDK)
Pin No. Signal Pin No. Signal
1 BIN1-L 8 BIN5-L
2 BIN2-L 9 GND
3 BIN3-L 10 SHIELD
4 BIN4-L 11 -
5 RETURN (+12V) 12 +12V -KT
6 START-L 13
7 END-L 14
26
• Test Start Signal• Low true is set at time of shipment• Switching to high true can be made by the DIP switch SW-4 to SW-6• Required signal pulse is 1ms
• Test End Signal• Low true is set at time of shipment• Switching to high true can be made by the DIP switch SW-2• Required signal pulse is 3ms
• Bin Signals• Low true is set at time of shipment• Switching to high true can be made by the DIP switch SW-1• Output signal is HOLD
27
• 2-bin mode (HAND1)• PASS, FAIL (LOW, HIGH, REJECT)
• 4-bin mode (HAND2)• PASS, LOW, HIGH, REJECT (AVAL, ERROR, OSC, OPEN, SHORT, CONTF)
• 5-bin mode (HAND3)• PASS, LOW, HIGH, CONTF, REJECT (AVAL, ERROR, OSC, OPEN, SHORT)
• 4-bin mode (HAND4)• PASS, OPEN, HIGH/LOW, REJECT (AVAL, ERROR, OSC, SHORT, CONTF)
• 5-bin mode (HAND5)• PASS, OPEN, SHORT, CONTF, REJECT (HIGH, LOW, AVAL, ERROR, OSC)
• 4-bin mode (HAND6)• PASS, OPEN/SHORT, HIGH/LOW, REJECT (AVAL, ERROR, OSC, CONTF)
• 4-bin mode (HAND7)• PASS, OPEN/SHORT, REJECT, HIGH/LOW (AVAL, ERROR, OSC, CONTF)
• 4-bin mode (HAND8)• PASS, CONTF/OSC, OPEN/SHORT, REJECT (AVAL, ERROR, HIGH, LOW)
• 5-bin mode (HAND9)• PASS, OPEN/AVAL1(GATE LIMIT), SHORT/AVAL2 (0.2V detect, IC limit), REJECT
(LOW, HIGH, OSC, ERROR, VCB ALARM, CONTF)
28
SIGNAL CIRCUITS
5
6
SW4-3
SW4-5
SW4-4
SW4-6
360Ω
PC817RETURN
START
OUTPUT
2K
12V
LS06INTPUT CIRCUIT
(START SIGNAL)
OUTPUT CIRCUIT
(END, BIN SIGNALS)
29
DIP SWITCH SETTING
Logic setting (high true & low true) is made by the DIP switch SW4 on the rear panel of the main unit (KT).
NOTICE:
(a.) SORT=PASS, HIGH/FAIL, LOW, REJECT
(b.) When the switches, No.3 and No.4 are turned ON, the switches No.5 and No.6 must be turned OFF.
(c.) When the switches, No.5 and No.6 are turned ON, the switches No.3 and No.4 must be turned OFF.
(d.) The SW4 switch is set to conform to the interface specifications at the time of shipment.
(e.) “-H” indicates high true and “-L” indicates low true.
30
EXT Connector (Pin Arrangement)
NOTICE:
(a.) The *1 mark indicates that the pin is not in use.
(b.) “-H” indicates high true and “-L” indicates low true.
TEST start Signal (AUXX,AUXY, or AUXZ) Always low true Required signal pulse is 1ms Select 1 signal among AUXX,AUXY and AUXZ with DIP switch SW3. One desired switch only must be turned ON and 2 other switches must be turned OFF
31
CHECK TERMINAL Site
CHECK TERMINAL
CYCLE S/H1 DELAY S/H2
VCB ON VG ON IE ON GND
1 5 6 7
2 3 4 8
(1.) CYCLE
(2.) VCB ON
(3.) VG ON
(4.) IE ON
(5.) S/H1
(6.) DELAY
(7.) S/H2
(8.) GND
Low level from the start to the end of a test
Low level while the VCB power is ON.
Low level while the gate power is ON in FET measurement
Low level while the IE power is ON
Low level during the 1st sampling
Low level during the delay time
Low level during the 2nd sampling
The ground terminal for an oscilloscope
The following check terminals are provided, which are to be checked by an oscilloscope (0 to +3.4V, low true
32
OPERATION PREREQUISITES
1 6
OFF
1 5
OFF
1 3
OFF
1 7
OFF
SW1 SW2 SW3 SW4
SW1 >> sets the baud rates of the SERIAL connector
SW2 >> sets the address of the GPIIB connector
SW3 >> sets the start signal type of the EXT connector
SW4 >> sets the logic (high true and low true) for signal of the HANDLER connector
33
Contact Check Detection
Contact Check of Transistors
(a) Connect the force (F) and sense (S) terminals for each of B, C and E.
(b) Set the POLARITY Switch to NPN.
Turn ON the Contact Check Switch.
(c) Push the START Switches. If there is no CONTACT FAIL, it is OK
(d) Remove the shorting wire connected to BASE and push the START Switches.
If there is CONTACT FAIL, it is OK.
(e) Return to (a) condition.
Remove the shorting wire connected to COLLECTOR and push the START Switches.
If there is CONTACT FAIL, it is OK.
(f) Return to (a) condition.
Remove the shorting wire connected to EMITTER and push the START Switches.
If there is CONTACT FAIL, it is OK.
(g) Return to (a) condition, set the POLARITY switch to PNP.
Conduct steps (c) to (f) to confirm that PNP is OK.
(h) If under any condition, there is no CONTACT FAIL, the system is OK.
34
Contact Check Detection
Contact Check of FET
(a) Connect the force (F) and sense (S) terminals for Drain and Source.
(b) Set the POLARITY Switch to N-MOS FET.
Turn ON the Contact Check Switch.
(c) Push the START Switches. If there is no CONTACT FAIL, it is OK
(d) Remove the shorting wire connected to DRAIN and push the START Switches.
If there is CONTACT FAIL, it is OK.
(e) Return to (a) condition.
Remove the shorting wire connected to SOURCE and push the START Switches.
If there is CONTACT FAIL, it is OK.
(g) Return to (a) condition, set the POLARITY switch to P-MOS FET.
Conduct steps (c) to (e) to confirm that P-MOS FET is OK.
(h) If under any condition, there is no CONTACT FAIL, the system is OK.
NOTE:
Contact resistance limit is adjustable from 50Ω, 100Ω, 150Ω, 200Ω located at CP8741. It can be set for total contact resistance at G, D & S.
35