Download - Ddr3 Controller Design
DDR3 CONTROLLER DESIGN
Pavan Kumar Reddy (621638)Brindha AG (621685)Vaishnavi S (621703)Lekshmi Vishwanath (621653)Amritha Krishna R S (621663)Anju C (621661)Arun Rajan (621844)
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OVERVIEW
• INTRODUCTION• OBJECTIVE• MOTIVATION• ARCHITECTURE OF DDR3 CONTROLLER• MICRO ARCHITECTURE OF DDR3 CONTROLLER• TASKS COMPLETED
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INTRODUCTION• DRAM (Dynamic random access memory)
– Random access : indicates that any position in the memory can be accessed by providing the row and column address
– Dynamic : The memory is designed using transistor and capacitor. This involves periodic charging of the capacitors
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INTRODUCTION CONT…
• Specific features of DDR3
1) Faster than earlier generations as it provides data in both edges of the clock cycle
2) Better performance than previous generation DDR2 by writing /reading 8 consecutive locations. DDR2 can read/write 4 consecutive locations
3) Lower power due to smaller die-size and lower supply voltage
4) Larger densities. Reduces the number of pins by using row and column multiplexing
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OBJECTIVE
To design a DDR3 memory controller for interfacing AXI and DDR3 DRAM memory
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MOTIVATION• DDR3 memory controller acts as an interface between AXI and DDR3
DRAM memory
• Row, column and bank address decoding is done by this module
• Takes care of write and read latencies
• Interprets the commands issued by the AXI and translates it to DDR3 memory
• Takes care of periodic refresh of memory
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INITIALISATION(VENDOR SPECIFIC)
DEVICE READY LOGIC
REFRESH TIMER
ADDRESS DECODER
ROW STATUS LOGIC
PREV ROW ADDR STATUS
PREV ROW ADDR STATUS
PREV ROW ADDR STATUS
PREV ROW ADDR STATUS
COMMAND CONTROLLER COMMAND
PATH
WRITE PATH
READ PATH
CLK
RESET_N
ADDR
RD
WR
WDATA
CMD_ACK
DEV_RDY
DDR3_CKE
DDR3_CS
DDR3_CK_N
DDR3_CK
DDR3_CAS_N
DDR3_RAS_N
DDR3_ADDR
DDR3_BA
DDR3_ODT
DDR3_DM
DDR3_WE_N
DDR3_DQ
DDR3_DQS
ARCHITECTURE OF DDR3 CONTROLLER
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MICRO ARCHITECTURE OF DDR3 CONTROLLER
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INITIALISATIONMODULE
CLK
RST_NMRS
MODULE COMMAND PATH
MODULE
FSMMODULE
ADDRESS DECODERMODULE
WRITE PATH MODULE
READ PATHMODULE
DLL_RESET
DEV
_REA
DY
BA_A
DD
R[2:
0]
CA[
{11,
9:0}
]
RA[1
5:0]
OPENED_ROW
MATCH
mrs[18:16]
DLL_ENABLE
DQS
DQ[7:0]
DQS
DQ[7:0]
mrs[15:0]
DATA_VALID
READ_DATA[31:0]AXI SLAVE CONTROLLER
AXI SLAVE CONTROLLER
DATA[31:0]
DEV_READY
WRITE
READ
READ
WRITEAXI
REFR
ESH
ACTI
VE
PREC
HAR
GE
ODTCKE
ZQCL
MRS
BA[2:0]
MRS
ADDR_OUT[15:0]
BA_ADDR[2:0]
CSRAS_N
CAS_N
WE_N
COMMAND_ACK
CLK
RST_
N
CLK
CLK
CLK
CLK
RST_
NRS
T_N
RST_
NRS
T_N
WRITE(AXI)
REFR
ESH
ACTI
VE
PREC
HAR
GE
W
RITE
REA
D
ADDR[31:0]AXI SLAVE CONTROLLER
NOP
CSRAS_
N
CAS_
NW
E_N
DQS_N
CKCK_N
DQS_N
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INITIALIZATION• Purpose
– For creating source synchronization (ie for creating the clock for memory)
– To inform the timing setup (in terms of latencies) to the memory
– Provides On Die Termination(ODT) information for fabrication
– Provides the calibration precision required for DDR-PHY
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INITILIZATION CONT…
WAIT TXPR
IDLE
WAIT 500µs
LOAD MODE COMMAND TO MR2
LOAD MODE COMMAND TO MR3
LOAD MODE COMMAND TO MR1
LOAD MODE COMMAND TO MR0
WAIT TMRD
WAIT TMOD
ZQCL CALIBRATION
WAIT ZQCL
INITIALIZATION DONE
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INITILIZATION CONT…
Mode register select
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INITILIZATION CONT…
Device ready
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INITILIZATION CONT…
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INITILIZATION CONT…
CHALLENGES SOLUTIONS
Specification mismatch Changed the clock-period and parameters accordingly
ZQCL mismatch Added ZQCL command to command path
Timing violations The code was debugged and added timing delays
tCK(avg ) parameter violation The column latency and additive latency were changed accordingly
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ADDRESS DECODER• Purpose
– Addressing of 8GB memory• Column address• Row address• Bank Address
– Maintains row status logic• Organization
– 8 banks with 1GB each– This addressed as 4GB address at a time– A11 bit of column address is used to select top 4GB or bottom 4GB– 16 bit row address– 10 bit column address
512
512
A11
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ADDRESS DECODER CONT …CHALLENGES SOLUTIONS
Row open status OPEN signal was generated along with MATCH signal
Auto - precharge and burst chop Auto-precharge : ignoredBurst chop : 0Burst size : 4Burst type : sequential
Address - one clock cycle Temporary register was used to capture the address
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COMMAND PATH• Purpose
– Helps in decoding the command issued by the AXI and indicates it to the memory by the ras_n, cas_n, we_n and cs_n signals
– Based on the command, command path either passes MRS contents or the row /column address to the addr_out
– Achieves address multiplexing by passing row address during activate/precharge commands
– The column address is passed during read and write commands– Based on the command, command path either passes register
address or bank address through the ba_out
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COMMAND PATH CONT…
MRS
MRS
ADDRESS DECODER
ADDRESS DECODER
COMMAND DECODING LOGIC
0
1
0
1
!MRS/OC
!MRS/OC
addr out
ba
cas_nras_ncs_nwe_n
active precharge
read write
refresh
nop
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COMMAND PATH CONT…
MODE REGISTER SET• Purpose
– Used to provide the setup information to memory in terms of four registers.
– Provides the following information to the memory• Column write latency• Additive latency• Burst size and type• ODT resistance values• Refresh timings (Auto refresh)
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COMMAND PATH CONT…
CHALLENGES SOLUTIONS
Fixed length burst write/readOn-The-Fly burst write/read
Implemented Fixed length burst write/read
Multiplexing of row and column address Achieved using ACTIVE and READ/WRITE command
Activate logic Redesigned ZQCL counter
Parameter in the MRS register set Identified and hardcoded
Write leveling logic Disabled
Fixed burst size Respective bits of MRS were changed
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COMMAND CONTROLLER
• Purpose– Acts as the heart of the module– Responsible for taking care of all the latencies of the memory– Issues refresh, activate, precharge, read and write commands to
the command path after the wait latencies– Takes care of issuing device ready signal and command
acknowledgement signal to the AXI– Acts as the major coordinator with AXI– Communicates with the row-status logic to issue precharge and
activate commands accordingly– Manages read and write data path by issuing appropriate read
and write commands
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COMMAND CONTROLLER FSM
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VENDOR SPECIFIC INITIALISATION
SEQUENCE
REFRESH
WAIT_tRC
IDLEREFRESH TIMER
PRECHARGE
WAIT_tRP
ACTIVATE
WAIT_tRCDWRITE
WAIT_tWR
READ
WAIT_tCCD
INIT DONE
(WRITE | READ)&(OPENED_ROW)& !MATCH
READ&(OPENED_ROW)& MATCH
BURST DONE
BURST DONE
READ & MATCH &!OPENED_ROW
REFRESH DONE
PRECHARGE DONE
ACTIVATE DONE
WRITE &(OPENED_ROW)& MATCH
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COMMAND CONTROLLER CONT…
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COMMAND CONTROLLER CONT…
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COMMAND CONTROLLER CONT…
CHALLENGES SOLUTIONS
To interface with the AXI, device ready and command acknowledgement signals were required
Required signals were added to FSM at the required time
NOP was not issued earlier during the wait period
Later it was issued to the command path
Refresh timer value Calculated the exact value based on specification
Sensing the read/write command coming from the AXI
The signal was sensed in the first clock cycle
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WRITE PATH• Purpose
– The write path should facilitate the writing of data in both posedge and negedge of the clock
– Should take care of burst length – Receives the 32-bit input from the AXI and then divides it according
to the burst length and writes into the memory – Should provide data strobe signal which indicates to the memory
that the data is being written into the memory– The strobe should be active for period before and after the
transaction of the data transfer
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Temp Reg for DATA Capture
Count > tWPR& count < tWPST
0
10
1
0
1
0
1clk
WRITEDQ
DQS
z
8
8
8
8
8
8
8
select
8 FF
8 FF
WRITE PATH CONT…
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WRITE PATH CONT…
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WRITE PATH CONT…
CHALLENGES SOLUTIONS
Not working as per the specification Introduced NOP during the wait period
Should accept the data only for one clock cycle
Used temporary register
Integrating with top module Data mask output = 0
Testing of write data path with the AXI driver
Delay was modeled accordingly to get the expected output
Set-up and hold time violations The data was sent with a delay (Behavioral coding)
Write leveling error Corrected by mode register setting
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READ PATH
• Purpose– Used to read the data from the memory and provide it to the
AXI– Reads the data from the memory on receiving the strobe signal
(DQS)– Similar to the write operation, the read operations reads data in
both posedge and negedge of the clock– Receives the data from the memory according to the burst length– Concatenates the data into a 32-bit output and provides to the
AXI– Provides a valid signal to the AXI which indicates that the valid
data is being transferred
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Data Processing Unit
Control Logic
8-bit 8-bit 8-bit 8-bit
32-bit Data8-bit DQ
AXI
DDR3 Memo
ry Data Valid
DQS
RST_NCLKRead(from FSM)
Control Signals
READ PATH CONT…
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READ PATH CONT…
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READ PATH CONT…
CHALLENGES SOLUTIONS
Valid signal to AXI model Incorporated additional signal
Following the data strobe signal Studied the DQS pattern as per the specification
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DDR3 CONTROLLER - TOP
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TASKS COMPLETED• RTL coding of the blocks as per the micro-architecture
• All the blocks were integrated and testing was done by forcing the values
• Timing verification of the initialization sequence as per the reference model
• Testing of write operation using AXI driver is in progress
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THANK YOU