Download - DDES Combinational Lec 0
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 1
Digital Design and Embedded Systems (GP)
Combinational Logic
Binary numbers revision
Gate and Flip-flop revision
Boolean Algebra
Combinational LogicBoolean function realisation, and
cost optimised reduction
Karnaugh maps minimisation
The Essence of Digital Design, Barry Wilkinson, 1998, ISBN 0-13-570110-4
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 2
Digital Logic Design
Logic DesignSchematic, VHDL & FSM
Logic simulation
Principles of logic simulation, multi-valued logic simulation and
indeterminacy.
Logic ImplementationFPGA development tools.
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 3
Revision binary numbers
Convert the following decimal numbers into binary:
(a) 16 = 10000
(b) 77= 1001101
(c) 0.5= 0.1
(d) 99.75=1100011._________
(e) 77.3=_________. 0100110011001100
77.3*______ -> (hex)=_______->(bin)=___________________
(f) -45=1010011
(g) -2.5
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 4
Revision binary numbers
Write the 1s and 2s complement representation for-5
Perform the following mathematical operations by using addition:
-34+44
-24-31
45-44
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 5
Logic level representation
+5V
+0V
+0.4V
+2.4V+2.0V
+0.8V
Output voltage Input voltage
Noise margins
Logic
1
Logic
0
TTL voltages
Input voltageOutput voltage
CMOS voltages
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 6
Revision Gates and Flip-flops
A
BY
A
BY
A
BY
A Y
A B Y
0 0 00 1 0
1 0 0
1 1 1
A B Y
0 0
0 1
1 0
1 1
A B Y
0 0
0 1
1 0
1 1
A Y
0
1
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Revision Gates and Flip-flops
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A B Y
0 00 1
1 0
1 1
A B Y
0 0
0 1
1 0
1 1
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 8
Revision Gates and Flip-flops
A
B
YY
B
A
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
0 1 1 0
T1
T1
T2 T2
CMOS OR Gate
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 9
Revision Gates and Flip-flops
A B
Y
Y
B
A
A B Y
0 0
0 1
1 0
1 1
0 1 1 0
T2
T2
T1 T1
CMOS ____ Gate
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 10
Revision Gates and Flip-flops
T2
T1A Y
A Y
0 1
1 0
CMOS NOT Gate
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 11
Revision Gates and Flip-flops
T1
T1
T2 T2
T2
T1A
B
Y
CMOS ____ Gate
A B Y
0 00 1
1 0
1 1
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 12
Revision Gates and Flip-flops
Fan-in:
Fan-out:
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 13
Revision Gates and Flip-flops
S R Q+
0 0
0 1
1 0
1 1
Q
Q
R
S
Q
Q
D
CLK
Q
Q
R
S
CLK
Q
Q
J
KCLK
D Q+
0
1
S RCLK
Q+
0 0
0 1
1 0
1 1
J KCLK
Q+
0 0
0 1
1 0
1 1
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 14
Revision Gates and Flip-flops
Q
Q
D
CLK
Q
Q
R
S
CLK
R
Q
Q
Q
Q
S
D
CLK
CLK
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 15
Revision Boolean algebra
A0=
A1=
AA=
AA=
A+0=A+1=
A+A=
A+A=
A=
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 16
Revision Boolean algebra
AB=BA
A+B=B+A
Associative law:
ABC=(AB) C=A(BC)
A+B+C=(A+B)+C=A+(B+C)
Distribution law:
A(B+C)=AB+AC
A+(BC)=(A+B) (A+C)
Duality:
A+AB = A (A+B)
DeMorgans theorem
A+B=(AB)
AB=(A+B)
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 17
A logic system with output values that depend
only on the logic structure and the current value of
the system inputs.
Combinational LogicDefinition
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 18
Operational representation of a combinational logic system
The operation of any combinational circuit can be represented in two ways:
Truth table
Boolean function
What defines the size of the truth tables?
Why do we need to represent the operation of any combinational logic
circuit by Boolean functions?
Truth tables and Boolean function expressions are interchangeable.
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 19
Boolean function
Sums of Products (SOP or minterms)
The logic function is implemented with an AND/OR hierarchy
ie.
Products of Sums (POS or Maxterms)
The logic function is implemented with an OR/AND hierarchy
ie.
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 20
Boolean function SOP mintermsThe usual way of deriving Boolean functions is by converting a
truth table. Can you write the minterm Boolean function for the
truth table presented below?
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 11 1 0 1
1 1 1 0
minterms are terms in the truth table
that evaluate to truth as output
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 21
Boolean function SOP (minterms)The usual way of deriving Boolean functions is by converting a
truth table. Can you write the minterm Boolean function for the
truth table presented below?
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 11 1 0 1
1 1 1 0
f(A,B,C)=m(2,3,5,6)=m2+m3+m5+m6
CBACBACBACBACBAf ),,(
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 22
Truth tables
The following Truth table describes the logic for digital system shown on the
right hand side
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 23
Based on the truth table shown below can you design its corresponding logic
on the space given on the right?
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Truth tables
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 24
Minimisation
What is it?
Why do we need it?
Cost
Systems reliability, propagation delay
How can we perform it?
Boolean algebra
Karnaugh maps
Quine-McCluskey
CAD tools
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 25
Karnaugh maps minimisation
Karnaugh maps consists of a two dimensional array of squares.
Each square corresponds to one minterm.
The addressing of each square is based on the particular combination of
the input operands.
The value of each square represents the output of the system.
Allocation of addresses for each square is based on the rule that only
one input operand may be different (complemented) for horizontally orvertically neighbouring squares.
Karnaugh maps have the advantage of offering a visual way of
minimization.
Their size is limited by their increasing complexity when the input
operands increase.
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 26
Minimisation with Karnaugh maps
Three Variables
Four Variables
Two Variables
Five Variables
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 27
Karnaugh maps addressing (three input operands)
Three Variables
A
A
CB CB BC CB
000
100
001 011 010
101 111 110
0
4
1 3 2
5 7 6
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 28
Karnaugh maps addressing (four input operands)
Four Variables
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 29
Karnaugh maps minterm grouping rules
DC
BA
DC CD DC
BA
AB
BA
DC
BA
DC CD DC
BA
AB
BA
DC
BA
DC CD DC
BA
AB
BA
1 1
1
1
11
1
1 1
1 1
1
1
DC
BA
DC CD DC
BA
AB
BA
1 1 1 1
1
1
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 30
Karnaugh maps minimisation procedure
DC
BA
DC CD DC
BA
AB
BA
1 1 1
1 1
1 1
DB
BDA
BCA
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Digital Design and Embedded Systems (5ELE0060) Lecture 0 31
Karnaugh maps (minimisation example)
DC
BA
DC CD DC
BA
AB
BA
0 1 1 1
0 1 1 1
0 0 0 0
0 0 0 0
DCBADCBADCBADCBADCBADCBAfDCBADCBADCBADCBADCBADCBADCBADCBAf
DCBADCBADCBADCBADCBADCBAf
3
2
1
DC
BA
DC CD DC
BA
AB
BA
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
DC
BA
DC CD DC
BA
AB
BA
3
2
1 )(
f
f
CDACADAf