Download - Datesheet PIC24FJ32GA
© 2008 Microchip Technology Inc. Preliminary DS39881C
PIC24FJ64GA004 FamilyData Sheet
28/44-Pin General Purpose,16-Bit Flash Microcontrollers
Note the following details of the code protection feature on Microchip devices:� Microchip products meet the specification contained in their particular Microchip Data Sheet.
� Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
� There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip�s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
� Microchip is willing to work with the customer who is concerned about the integrity of their code.
� Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as �unbreakable.�
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip�s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer�s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.
DS39881C-page ii Prelimin
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
ary © 2008 Microchip Technology Inc.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company�s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip�s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
PIC24FJ64GA004 FAMILY28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:� Modified Harvard Architecture� Up to 16 MIPS Operation @ 32 MHz � 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options� 17-Bit by 17-Bit Single-Cycle Hardware Multiplier� 32-Bit by 16-Bit Hardware Divider� 16-Bit x 16-Bit Working Register Array� C Compiler Optimized Instruction Set Architecture:
- 76 base instructions- Flexible addressing modes
� Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Special Microcontroller Features:� Operating Voltage Range of 2.0V to 3.6V� 5.5V Tolerant Input (digital pins only)� High-Current Sink/Source (18 mA/18 mA) on All I/O Pins� Flash Program Memory:
- 10,000 erase/write- 20-year data retention minimum
� Power Management modes: - Sleep, Idle, Doze and Alternate Clock modes- Operating current 650 μA/MIPS typical at 2.0V- Sleep current 150 nA typical at 2.0V
� Fail-Safe Clock Monitor Operation:- Detects clock failure and switches to on-chip,
low-power RC oscillator � On-Chip, 2.5V Regulator with Tracking mode� Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)� Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation� In-Circuit Serial Programming� (ICSP�) and
In-Circuit Debug (ICD) via 2 Pins� JTAG Boundary Scan and Programming Support
Analog Features:� 10-Bit, up to 13-Channel Analog-to-Digital Converter:
- 500 ksps conversion rate- Conversion available during Sleep and Idle
� Dual Analog Comparators with Programmable Input/Output Configuration
Peripheral Features:� Peripheral Pin Select:
- Allows independent I/O mapping of many peripherals- Up to 26 available pins (44-pin devices)- Continuous hardware integrity checking and safety
interlocks prevent unintentional configuration changes� 8-Bit Parallel Master/Slave Port (PMP/PSP):
- Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices
- Programmable polarity on control lines� Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions� Programmable Cyclic Redundancy Check (CRC)� Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer� Two I2C� modules support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing� Two UART modules:
- Supports RS-485, RS-232, and LIN 1.2- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Start bit- Auto-Baud Detect- 4-level deep FIFO buffer
� Five 16-Bit Timers/Counters with Programmable Prescaler� Five 16-Bit Capture Inputs� Five 16-Bit Compare/PWM Outputs� Configurable Open-Drain Outputs on Digital I/O Pins� Up to 4 External Interrupt Sources
PIC24FJDevice Pi
ns
Prog
ram
Mem
ory
(byt
es)
SRA
M(b
ytes
)
Remappable Peripherals
I2 C�
10-B
it A
/D(c
h)
Com
para
tors
PMP/
PSP
JTA
G
Rem
appa
ble
Pin
s
Tim
ers
16-
Bit
Cap
ture
Inpu
t
Com
pare
/PW
MO
utpu
t
UA
RT
w/
IrDA
®
SPI
16GA002 28 16K 4K 16 5 5 5 2 2 2 10 2 Y Y32GA002 28 32K 8K 16 5 5 5 2 2 2 10 2 Y Y48GA002 28 48K 8K 16 5 5 5 2 2 2 10 2 Y Y64GA002 28 64K 8K 16 5 5 5 2 2 2 10 2 Y Y16GA004 44 16K 4K 26 5 5 5 2 2 2 13 2 Y Y32GA004 44 32K 8K 26 5 5 5 2 2 2 13 2 Y Y48GA004 44 48K 8K 26 5 5 5 2 2 2 13 2 Y Y64GA004 44 64K 8K 26 5 5 5 2 2 2 13 2 Y Y
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 1
PIC24FJ64GA004 FAMILY
Pin DiagramsPIC
24FJ
XXG
A00
2
1234567891011121314
2827262524232221201918171615
28-Pin SPDIP, SSOP, SOIC
28-Pin QFN(1)
10 11
23
6
1
18192021
22
1213 1415
87
1617
232425262728
9
PIC24FJXXGA00254
MCLR
VSS
VDD
AN0/VREF+/CN2/RA0AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
SOSCO/T1CK/CN0/PMA1/RA4SOSCI/RP4/PMBE/CN1/RB4
OSCO/CLKO/CN29/PMA0/RA3OSCI/CLKI/CN30/RA2
AN5/C1IN+/RP3/SCL2/CN7/RB3AN4/C1IN-/RP2/SDA2/CN6/RB2
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5
VDDVSS
PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6
DISVREGVCAP/VDDCORE
RP7/INT0/CN23/PMD5/RB7
TDO/RP9/SDA1/CN21/PMD3/RB9TCK/RP8/SCL1/CN22/PMD4/RB8
AN9/RP15/CN11/PMCS1/RB15AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14AN11/RP13/CN13/PMRD/RB13AN12/RP12/CN14/PMD0/RB12
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
VSS
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
OSCO/CLKO/CN29/PMA0/RA3OSCI/CLKI/CN30/RA2
AN5/C1IN+/RP3/SCL2/CN7/RB3AN4/C1IN-/RP2/SDA2/CN6/RB2
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
DISVREGVCAP/VDDCORE
TDO/RP9/SDA1/CN21/PMD3/RB9
AN11/RP13/CN13/PMRD/RB13AN12/RP12/CN14/PMD0/RB12
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
VD
D
PGC
3/E
MU
C3/
RP6
/ASC
L1/C
N24
/PM
D6/
RB6
SO
SC
O/T
1CK/
CN
0/P
MA
1/R
A4
SO
SC
I/RP4
/PM
BE/C
N1/
RB
4
RP7
/INT0
/CN
23/P
MD
5/R
B7
TCK
/RP8
/SC
L1/C
N22
/PM
D4/
RB
8
PGD
3/E
MU
D3/
RP5
/AS
DA1
/CN
27/P
MD
7/R
B5
MC
LRA
N0/
VRE
F+/C
N2/
RA
0A
N1/
VRE
F-/C
N3/
RA
1
VD
DV
SS
AN
9/R
P15/
CN
11/P
MC
S1/
RB
15AN
10/C
V REF
/RTC
C/R
P14/
CN
12/P
MW
R/R
B14
Legend: RPn represents remappable peripheral pins.Note 1: Back pad on QFN devices should be connected to Vss.
DS39881C-page 2 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)1011
23456
1
18 19 20 21 2212 13 14 15
3887
44 43 42 41 40 3916 17
2930313233
232425262728
36 3435
9
PIC24FJXXGA004
37
44-Pin QFN(1)
RP8
/SC
L1/C
N22
/PM
D4/
RB8
RP7
/INT0
/CN
23/P
MD
5/R
B7
PG
C3/
EM
UC
3/R
P6/A
SC
L1/C
N24
/PM
D6/
RB
6P
GD
3/E
MU
D3/
RP5
/AS
DA
1/C
N27
/PM
D7/
RB
5V
DD
TDI/P
MA9
/RA
9S
OS
CO
/T1C
K/C
N0/
RA4
VS
SR
P21/
CN
26/P
MA
3/R
C5
RP2
0/C
N25
/PM
A4/
RC
4R
P19/
CN
28/P
MB
E/R
C3
AN12/RP12/CN14/PMD0/RB12PGC2/EMUC2/RP11/CN15/PMD1/RB11PGD2/EMUD2/RP10/CN16/PMD2/RB10
VCAP/VDDCOREDISVREG
RP25/CN19/PMA6/RC9RP24/CN20/PMA5/RC8RP23/CN17/PMA0/RC7RP22/CN18/PMA1/RC6
RP9/SDA1/CN21/PMD3/RB9
AN11/RP13/CN13/PMRD/RB13 AN4/C1IN-/RP2/SDA2/CN6/RB2AN5/C1IN+/RP3/SCL2/CN7/RB3AN6/RP16/CN8/RC0AN7/RP17/CN9/RC1AN8/RP18/CN10/PMA2/RC2
SOSCI/RP4/CN1/RB4
VDDVSSOSCI/CLKI/CN30/RA2OSCO/CLKO/CN29/RA3TDO/PMA8/RA8
PG
C1/
EMU
C1/
AN3/
C2I
N+/
RP1
/CN
5/R
B1
PG
D1/
EM
UD
1/A
N2/
C2I
N-/R
P0/C
N4/
RB
0 A
N1/
VRE
F-/C
N3/
RA
1A
N0/
VRE
F+/C
N2/
RA
0M
CLR
TMS/
PMA
10/R
A10
AVD
DAV
SS
AN
9/R
P15/
CN
11/P
MC
S1/
RB
15A
N10
/CVR
EF/
RTC
C/R
P14/
CN
12/P
MW
R/R
B14
TCK
/PM
A7/
RA
7
Legend: RPn represents remappable peripheral pins.Note 1: Back pad on QFN devices should be connected to Vss.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 3
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)1011
23456
1
18 19 20 21 2212 13 14 15
38
87
44 43 42 41 40 3916 17
2930313233
232425262728
36 34359
37
44-Pin TQFP
PIC24FJXXGA004
AN12/RP12/CN14/PMD0/RB12PGC2/EMUC2/RP11/CN15/PMD1/RB11PGD2/EMUD2/RP10/CN16/PMD2/RB10
VCAP/VDDCOREDISVREG
RP25/CN19/PMA6/RC9RP24/CN20/PMA5/RC8RP23/CN17/PMA0/RC7RP22/CN18/PMA1/RC6
RP9/SDA1/CN21/PMD3/RB9
AN11/RP13/CN13/PMRD/RB13 AN4/C1IN-/RP2/SDA2/CN6/RB2AN5/C1IN+/RP3/SCL2/CN7/RB3AN6/RP16/CN8/RC0AN7/RP17/CN9/RC1AN8/RP18/CN10/PMA2/RC2
SOSCI/RP4/CN1/RB4
VDDVSSOSCI/CLKI/CN30/RA2OSCO/CLKO/CN29/RA3TDO/PMA8/RA8
RP8
/SC
L1/C
N22
/PM
D4/
RB
8R
P7/IN
T0/C
N23
/PM
D5/
RB
7P
GC
3/E
MU
C3/
RP6
/AS
CL1
/CN
24/P
MD
6/R
B6
PG
D3/
EM
UD
3/R
P5/A
SD
A1/
CN
27/P
MD
7/R
B5
VD
D
TDI/P
MA
9/R
A9
SO
SCO
/T1C
K/C
N0/
RA
4
VS
SR
P21/
CN
26/P
MA3
/RC
5R
P20/
CN
25/P
MA4
/RC
4R
P19/
CN
28/P
MBE
/RC
3
PG
C1/
EM
UC
1/A
N3/
C2I
N+/
RP1
/CN
5/R
B1
PG
D1/
EMU
D1/
AN2/
C2I
N-/R
P0/C
N4/
RB
0 A
N1/
VRE
F-/C
N3/
RA
1A
N0/
V RE
F+/C
N2/
RA
0M
CLR
TMS
/PM
A10
/RA
10
AVD
DAV
SS
AN
9/R
P15/
CN
11/P
MC
S1/R
B15
AN
10/C
V RE
F/R
TCC
/RP1
4/C
N12
/PM
WR
/RB
14TC
K/PM
A7/
RA
7
Legend: RPn represents remappable peripheral pins.
DS39881C-page 4 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 CPU ........................................................................................................................................................................................... 173.0 Memory Organization ................................................................................................................................................................. 234.0 Flash Program Memory.............................................................................................................................................................. 415.0 Resets ........................................................................................................................................................................................ 476.0 Interrupt Controller ..................................................................................................................................................................... 537.0 Oscillator Configuration .............................................................................................................................................................. 878.0 Power-Saving Features.............................................................................................................................................................. 959.0 I/O Ports ..................................................................................................................................................................................... 9710.0 Timer1 ..................................................................................................................................................................................... 11711.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 11912.0 Input Capture............................................................................................................................................................................ 12513.0 Output Compare....................................................................................................................................................................... 12714.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 13315.0 Inter-Integrated Circuit (I2C�) ................................................................................................................................................. 14316.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 15117.0 Parallel Master Port (PMP)....................................................................................................................................................... 15918.0 Real-Time Clock And Calendar (RTCC) ................................................................................................................................. 16919.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 17920.0 10-Bit High-speed A/D Converter............................................................................................................................................. 18321.0 Comparator Module.................................................................................................................................................................. 19322.0 Comparator Voltage Reference................................................................................................................................................ 19723.0 Special Features ...................................................................................................................................................................... 19924.0 Development Support............................................................................................................................................................... 20925.0 Instruction Set Summary .......................................................................................................................................................... 21326.0 Electrical Characteristics .......................................................................................................................................................... 22127.0 Packaging Information.............................................................................................................................................................. 239Appendix A: Revision History............................................................................................................................................................. 251Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 252Index ................................................................................................................................................................................................. 253The Microchip Web Site ..................................................................................................................................................................... 257Customer Change Notification Service .............................................................................................................................................. 257Customer Support .............................................................................................................................................................................. 257Reader Response .............................................................................................................................................................................. 258Product Identification System ............................................................................................................................................................ 259© 2008 Microchip Technology Inc. Preliminary DS39881C-page 5
PIC24FJ64GA004 FAMILY
TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.
Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:� Microchip�s Worldwide Web site; http://www.microchip.com� Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.
Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.
DS39881C-page 6 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
1.0 DEVICE OVERVIEWThis document contains device-specific information forthe following devices:
� PIC24FJ16GA002� PIC24FJ32GA002� PIC24FJ48GA002� PIC24FJ64GA002� PIC24FJ16GA004� PIC24FJ32GA004� PIC24FJ48GA004� PIC24FJ64GA004
This family introduces a new line of Microchip devices:a 16-bit microcontroller family with a broad peripheralfeature set and enhanced computational performance.The PIC24FJ64GA004 family offers a new migrationoption for those high-performance applications whichmay be outgrowing their 8-bit platforms, but don�trequire the numerical processing power of a digitalsignal processor.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURECentral to all PIC24F devices is the 16-bit modifiedHarvard architecture, first introduced with Microchip�sdsPIC® digital signal controllers. The PIC24F CPU coreoffers a wide range of enhancements, such as:
� 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces
� Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data)
� A 16-element working register array with built-in software stack support
� A 17 x 17 hardware multiplier with support for integer math
� Hardware support for 32 by 16-bit division� An instruction set that supports multiple
addressing modes and is optimized for high-level languages such as �C�
� Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGYAll of the devices in the PIC24FJ64GA004 familyincorporate a range of features that can significantlyreduce power consumption during operation. Keyitems include:
� On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs.
� Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat.
� Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.
1.1.3 OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC24FJ64GA004 family offerfive different oscillator options, allowing users a rangeof choices in developing application hardware. Theseinclude:
� Two Crystal modes using crystals or ceramic resonators.
� Two External Clock modes offering the option of a divide-by-2 clock output.
� A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz.
� A Phase Lock Loop (PLL) frequency multiplier, available to the External Oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz.
� A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications.
The internal oscillator block also provides a stablereference source for the Fail-Safe Clock Monitor. Thisoption constantly monitors the main clock sourceagainst a reference signal provided by the internaloscillator and enables the controller to switch to theinternal oscillator, allowing for continued low-speedoperation or a safe application shutdown.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 7
PIC24FJ64GA004 FAMILY
1.1.4 EASY MIGRATIONRegardless of the memory size, all devices share thesame rich set of peripherals, allowing for a smoothmigration path as applications grow and evolve.The consistent pinout scheme used throughout theentire family also aids in migrating to the next largerdevice. This is true when moving between devices withthe same pin count, or even jumping from 28-pin to44-pin devices.
The PIC24F family is pin-compatible with devices in thedsPIC33 family, and shares some compatibility with thepinout schema for PIC18 and dsPIC30. This extendsthe ability of applications to grow from the relativelysimple, to the powerful and complex, yet still selectinga Microchip device.
1.2 Other Special Features� Communications: The PIC24FJ64GA004 family
incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the peripheral pin select feature, two independent UARTs with built-in IrDA encoder/decoders and two SPI modules.
� Peripheral Pin Select: The peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins.
� Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communi-cations. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes.
� Real-Time Clock/Calendar: This moduleimplements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.
� 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.
1.3 Details on Individual Family Members
Devices in the PIC24FJ64GA004 family are availablein 28-pin and 44-pin packages. The general blockdiagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in twoways:
1. Flash program memory (64 Kbytes forPIC24FJ64GA devices, 48 Kbytes forPIC24FJ48GA devices, 32 Kbytes forPIC24FJ32GA devices and 16 Kbytes forPIC24FJ16GA devices).
2. Internal SRAM memory (4k for PIC24FJ16GAdevices, 8k for all other devices in the family).
3. Available I/O pins and ports (21 pins on 2 portsfor 28-pin devices and 35 pins on 3 ports for44-pin devices).
All other features for devices in this family are identical.These are summarized in Table 1-1.
A list of the pin features available on thePIC24FJ64GA004 family devices, sorted by function, isshown in Table 1-2. Note that this table shows the pinlocation of individual peripheral features and not howthey are multiplexed on the same pin. This informationis provided in the pinout diagrams in the beginning ofthe data sheet. Multiplexed features are sorted by thepriority given to a feature, with the highest priorityperipheral being listed first.
DS39881C-page 8 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILYFeatures
16G
A00
2
32G
A00
2
48G
A00
2
64G
A00
2
16G
A00
4
32G
A00
4
48G
A00
4
64G
A00
4
Operating Frequency DC � 32 MHz Program Memory (bytes) 16K 32K 48K 64K 16K 32K 48K 64KProgram Memory (instructions) 5,504 11,008 16,512 22,016 5,504 11,008 16,512 22,016Data Memory (bytes) 4096 8192 4096 8192Interrupt Sources(soft vectors/NMI traps)
43(39/4)
I/O Ports Ports A, B Ports A, B, CTotal I/O Pins 21 35Timers: Total Number (16-bit) 5(1)
32-Bit (from paired 16-bit timers) 2Input Capture Channels 5(1)
Output Compare/PWM Channels 5(1)
Input Change Notification Interrupt 21 30Serial Communications: UART 2(1)
SPI (3-wire/4-wire) 2(1)
I2C� 2Parallel Communications (PMP/PSP) YesJTAG Boundary Scan Yes10-Bit Analog-to-Digital Module (input channels)
10 13
Analog Comparators 2Remappable Pins 16 26
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP Note 1: Peripherals are accessible through remappable pins.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 9
PIC24FJ64GA004 FAMILY
FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAMInstructionDecode &Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
DivideSupport
Inst Latch
16
EA MUX
Read AGUWrite AGU
16
16
8
InterruptController
PSV & TableData AccessControl Block
StackControl
Logic
RepeatControlLogic
Data Latch
Data RAM
AddressLatch
Address Latch
Program Memory
Data Latch
16
Address Bus
Lite
ral D
ata
23
Control Signals
16
16
16 x 16W Reg Array
Multiplier17x17
OSCI/CLKIOSCO/CLKO
VDD,
TimingGeneration
VSS MCLR
Power-upTimer
OscillatorStart-up Timer
Power-onReset
WatchdogTimer
BOR and
Precision
ReferenceBand Gap
FRC/LPRCOscillators
RegulatorVoltage
VDDCORE/VCAP
DISVREG
PORTA(1)
PORTC(1)
RA0:RA9
RC0:RC9
PORTB
RB0:RB15
Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled.3: Peripheral I/Os are accessible through remappable pins.
RP(1)
RP0:RP25
Comparators(3)Timer2/3(3)Timer1 RTCC
IC1-5(3)
ADC10-Bit
PWM/SPI1/2(3) I2C1/2
Timer4/5(3)
PMP/PSP
OC1-5(3) CN1-22(1) UART1/2(3)
LVD(2)
DS39881C-page 10 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS
Function
Pin Number
I/O Input Buffer Description28-Pin
SPDIP/SSOP/SOIC
28-PinQFN
44-PinQFN/TQFP
AN0 2 27 19 I ANA A/D Analog Inputs.AN1 3 28 20 I ANAAN2 4 1 21 I ANAAN3 5 2 22 I ANAAN4 6 3 23 I ANAAN5 7 4 24 I ANAAN6 � � 25 I ANAAN7 � � 26 I ANAAN8 � � 27 I ANAAN9 26 23 15 I ANAAN10 25 22 14 I ANAAN11 24 21 11 I ANAAN12 23 20 10 I ANAASCL1 15 12 42 I/O I2C Alternate I2C1 Synchronous Serial Clock Input/Output.(1)
ASDA1 14 11 41 I/O I2C Alternate I2C2 Synchronous Serial Clock Input/Output. (1)
AVDD � � 17 P � Positive Supply for Analog Modules.AVSS � � 16 P � Ground Reference for Analog Modules.C1IN- 6 3 23 I ANA Comparator 1 Negative Input.C1IN+ 7 4 24 I ANA Comparator 1 Positive Input.C2IN- 4 1 21 I ANA Comparator 2 Negative Input.C2IN+ 5 2 22 I ANA Comparator 2 Positive Input.CLKI 9 6 30 I ANA Main Clock Input Connection.CLKO 10 7 31 O � System Clock Output.Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C� = I2C/SMBus input bufferNote 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 11
PIC24FJ64GA004 FAMILY
CN0 12 9 34 I ST Interrupt-on-Change Inputs.CN1 11 8 33 I STCN2 2 27 19 I STCN3 3 28 20 I STCN4 4 1 21 I STCN5 5 2 22 I STCN6 6 3 23 I STCN7 7 4 24 I STCN8 � � 25 I STCN9 � � 26 I STCN10 � � 27 I STCN11 26 23 15 I STCN12 25 22 14 I STCN13 24 21 11 I STCN14 23 20 10 I STCN15 22 19 9 I STCN16 21 18 8 I STCN17 � � 3 I STCN18 � � 2 I STCN19 � � 5 I STCN20 � � 4 I STCN21 18 15 1 I STCN22 17 14 44 I STCN23 16 13 43 I STCN24 15 12 42 I STCN25 � � 37 I STCN26 � � 38 I STCN27 14 11 41 I STCN28 � � 36 I STCN29 10 7 31 I STCN30 9 6 30 I STCVREF 25 22 14 O ANA Comparator Voltage Reference Output.DISVREG 19 16 6 I ST Voltage Regulator Disable.EMUC1 5 2 21 I/O ST In-Circuit Emulator Clock Input/Output.EMUD1 4 1 22 I/O ST In-Circuit Emulator Data Input/Output.EMUC2 22 19 9 I/O ST In-Circuit Emulator Clock Input/Output.EMUD2 21 18 8 I/O ST In-Circuit Emulator Data Input/Output.EMUC3 15 12 42 I/O ST In-Circuit Emulator Clock Input/Output.EMUD3 14 11 41 I/O ST In-Circuit Emulator Data Input/Output.INT0 16 13 43 I ST External Interrupt Input.
MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset.
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input Buffer Description28-Pin
SPDIP/SSOP/SOIC
28-PinQFN
44-PinQFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/output I2C� = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
DS39881C-page 12 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
OSCI 9 6 30 I ANA Main Oscillator Input Connection.OSCO 10 7 31 O ANA Main Oscillator Output Connection.PGC1 5 2 22 I/O ST In-Circuit Debugger and ICSP� Programming ClockPGD1 4 1 21 I/O ST In-Circuit Debugger and ICSP Programming Data.PGC2 22 19 9 I/O ST In-Circuit Debugger and ICSP Programming Clock.PGD2 21 18 8 I/O ST In-Circuit Debugger and ICSP Programming Data.PGC3 14 12 42 I/O ST In-Circuit Debugger and ICSP Programming Clock.PGD3 15 11 41 I/O ST In-Circuit Debugger and ICSP Programming Data.PMA0 10 7 3 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).PMA1 12 9 2 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).PMA2 � � 27 O � Parallel Master Port Address (Demultiplexed Master
modes).PMA3 � � 38 O �PMA4 � � 37 O �PMA5 � � 4 O �PMA6 � � 5 O �PMA7 � � 13 O �PMA8 � � 32 O �PMA9 � � 35 O �PMA10 � � 12 O �PMA11 � � � O �PMA12 � � � O �PMA13 � � � O �PMBE 11 8 36 O � Parallel Master Port Byte Enable Strobe.PMCS1 26 23 15 O � Parallel Master Port Chip Select 1 Strobe/Address Bit 14.PMD0 23 20 10 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).PMD1 22 19 9 I/O ST/TTLPMD2 21 18 8 I/O ST/TTLPMD3 18 15 1 I/O ST/TTLPMD4 17 14 44 I/O ST/TTLPMD5 16 13 43 I/O ST/TTLPMD6 15 12 42 I/O ST/TTLPMD7 14 11 41 I/O ST/TTLPMRD 24 21 11 O � Parallel Master Port Read Strobe.PMWR 25 22 14 O � Parallel Master Port Write Strobe.
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input Buffer Description28-Pin
SPDIP/SSOP/SOIC
28-PinQFN
44-PinQFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/output I2C� = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 13
PIC24FJ64GA004 FAMILY
RA0 2 27 19 I/O ST PORTA Digital I/O.RA1 3 28 20 I/O STRA2 9 6 30 I/O STRA3 10 7 31 I/O STRA4 12 9 34 I/O STRA7 � � 13 I/O STRA8 � � 32 I/O STRA9 � � 35 I/O STRA10 � � 12 I/O STRB0 4 1 21 I/O ST PORTB Digital I/O.RB1 5 2 22 I/O STRB2 6 3 23 I/O STRB3 7 4 24 I/O STRB4 11 8 33 I/O STRB5 14 11 41 I/O STRB6 15 12 42 I/O STRB7 16 13 43 I/O STRB8 17 14 44 I/O STRB9 18 15 1 I/O STRB10 21 18 8 I/O STRB11 22 19 9 I/O STRB12 23 20 10 I/O STRB13 24 21 11 I/O STRB14 25 22 14 I/O STRB15 26 23 15 I/O STRC0 � � 25 I/O ST PORTC Digital I/O.RC1 � � 26 I/O STRC2 � � 27 I/O STRC3 � � 36 I/O STRC4 � � 37 I/O STRC5 � � 38 I/O STRC6 � � 2 I/O STRC7 � � 3 I/O STRC8 � � 4 I/O STRC9 � � 5 I/O ST
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input Buffer Description28-Pin
SPDIP/SSOP/SOIC
28-PinQFN
44-PinQFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/output I2C� = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
DS39881C-page 14 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
RP0 4 1 21 I/O ST Remappable Peripheral.
RP1 5 2 22 I/O STRP2 6 3 23 I/O STRP3 7 4 24 I/O STRP4 11 8 33 I/O STRP5 14 11 41 I/O STRP6 15 12 42 I/O STRP7 16 13 43 I/O STRP8 17 14 44 I/O STRP9 18 15 1 I/O STRP10 21 18 8 I/O STRP11 22 19 9 I/O STRP12 23 20 10 I/O STRP13 24 21 11 I/O STRP14 25 22 14 I/O STRP15 26 23 15 I/O STRP16 � � 25 I/O STRP17 � � 26 I/O STRP18 � � 27 I/O STRP19 � � 36 I/O STRP20 � � 37 I/O STRP21 � � 38 I/O STRP22 � � 2 I/O STRP23 � � 3 I/O STRP24 � � 4 I/O STRP25 � � 5 I/O STRTCC 25 22 14 O � Real-Time Clock Alarm Output.SCL1 17 14 44 I/O I2C I2C1 Synchronous Serial Clock Input/Output.SCL2 7 4 24 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SDA1 18 15 1 I/O I2C I2C1 Data Input/Output.SDA2 6 3 23 I/O I2C I2C2 Data Input/Output.SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input.SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output.
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input Buffer Description28-Pin
SPDIP/SSOP/SOIC
28-PinQFN
44-PinQFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/output I2C� = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 15
PIC24FJ64GA004 FAMILY
T1CK 12 9 34 I ST Timer1 Clock.TCK 17 14 13 I ST JTAG Test Clock/Programming Clock Input.TDI 21 18 35 I ST JTAG Test Data/Programming Data Input.TDO 18 15 32 O � JTAG Test Data Output.TMS 22 19 12 I ST JTAG Test Mode Select Input.VDD 13, 28 10, 25 28, 40 P � Positive Supply for Peripheral Digital Logic and I/O Pins.VDDCAP 20 17 7 P � External Filter Capacitor Connection (regulator enabled).VDDCORE 20 17 7 P � Positive Supply for Microcontroller Core Logic (regulator
disabled).VREF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input.VREF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input.VSS 8, 27 5, 24 29, 39 P � Ground Reference for Logic and I/O Pins.
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input Buffer Description28-Pin
SPDIP/SSOP/SOIC
28-PinQFN
44-PinQFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/output I2C� = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
DS39881C-page 16 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.0 CPU
The PIC24F CPU has a 16-bit (data) modified Harvardarchitecture with an enhanced instruction set and a24-bit instruction word with a variable length opcodefield. The Program Counter (PC) is 23 bits wide andaddresses up to 4M instructions of user programmemory space. A single-cycle instruction prefetchmechanism is used to help maintain throughput and pro-vides predictable execution. All instructions execute in asingle cycle, with the exception of instructions thatchange the program flow, the double-word move(MOV.D) instruction and the table instructions. Over-head-free program loop constructs are supported usingthe REPEAT instructions, which are interruptible at anypoint.
PIC24F devices have sixteen, 16-bit working registersin the programmer�s model. Each of the workingregisters can act as a data, address or address offsetregister. The 16th working register (W15) operates asa Software Stack Pointer for interrupts and calls.
The upper 32 Kbytes of the data space memory mapcan optionally be mapped into program space at any16K word boundary defined by the 8-bit Program SpaceVisibility Page Address (PSVPAG) register. The programto data space mapping feature lets any instructionaccess program space as if it were data space.
The Instruction Set Architecture (ISA) has beensignificantly enhanced beyond that of the PIC18, butmaintains an acceptable level of backward compatibil-ity. All PIC18 instructions and addressing modes aresupported, either directly, or through simple macros.Many of the ISA enhancements have been driven bycompiler efficiency needs.
The core supports Inherent (no operand), Relative,Literal, Memory Direct and three groups of addressingmodes. All modes support Register Direct and variousRegister Indirect modes. Each group offers up to sevenaddressing modes. Instructions are associated withpredefined addressing modes depending upon theirfunctional requirements.
For most instructions, the core is capable of executinga data (or program data) memory read, a working reg-ister (data) read, a data memory write and a program(instruction) memory read per instruction cycle. As aresult, three parameter instructions can be supported,allowing trinary operations (that is, A + B = C) to beexecuted in a single cycle.
A high-speed, 17-bit by 17-bit multiplier has beenincluded to significantly enhance the core arithmeticcapability and throughput. The multiplier supportsSigned, Unsigned and Mixed mode, 16-bit by 16-bit or8-bit by 8-bit, integer multiplication. All multiplyinstructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divideassist hardware that supports an iterative non-restoringdivide algorithm. It operates in conjunction with theREPEAT instruction looping mechanism and a selectionof iterative divide instructions to support 32-bit (or16-bit), divided by 16-bit, integer signed and unsigneddivision. All divide operations require 19 cycles tocomplete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with upto 8 sources of non-maskable traps and up to 118 inter-rupt sources. Each interrupt source can be assigned toone of seven priority levels.
A block diagram of the CPU is shown in Figure 2-1.
2.1 Programmer�s ModelThe programmer�s model for the PIC24F is shown inFigure 2-2. All registers in the programmer�s model arememory mapped and can be manipulated directly byinstructions. A description of each register is providedin Table 2-1. All registers associated with theprogrammer�s model are memory mapped.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 2. CPU� (DS39703).
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 17
PIC24FJ64GA004 FAMILY
FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAMInstructionDecode &Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
Instruction Reg
16
16 x 16W Register ArrayDivide
Support
ROM Latch
16
EA MUX
RAGUWAGU
16
16
8
InterruptController
PSV & TableData AccessControl Block
StackControlLogic
LoopControlLogic
Data Latch
Data RAM
AddressLatch
Control Signalsto Various Blocks
Program Memory
Data Latch
Address Bus
16
Lite
ral D
ata
16 16
HardwareMultiplier
16
To Peripheral Modules
Address Latch
DS39881C-page 18 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 2-1: CPU CORE REGISTERSFIGURE 2-2: PROGRAMMER�S MODEL
Register(s) Name Description
W0 through W15 Working Register ArrayPC 23-Bit Program CounterSR ALU STATUS RegisterSPLIM Stack Pointer Limit Value RegisterTBLPAG Table Memory Page Address RegisterPSVPAG Program Space Visibility Page Address RegisterRCOUNT Repeat Loop Counter RegisterCORCON CPU Control Register
N OV Z C
TBLPAG
22 0
7 0
015
Program Counter
Table Memory Page
ALU STATUS Register (SR)
Working/AddressRegisters
W0 (WREG)
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Frame Pointer
Stack Pointer
PSVPAG7 0
Program Space Visibility
RA
0
RCOUNT15 0
Repeat Loop Counter
SPLIM Stack Pointer Limit
SRL
Registers or bits shadowed for PUSH.S and POP.S instructions.
0
0
Page Address Register
15 0CPU Control Register (CORCON)
SRH
W14
W15
DC IPL2 1 0
� ������
IPL3 PSV� � � � � � � � � � � � � �
PC
Divider Working Registers
Multiplier Registers
15 0
Value Register
Address Register
Register
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 19
PIC24FJ64GA004 FAMILY
2.2 CPU Control RegistersREGISTER 2-1: SR: ALU STATUS REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0� � � � � � � DC
bit 15 bit 8
R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2(2) IPL1(2) IPL0(2) RA N OV Z C
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as �0�bit 8 DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)of the result occurred
0 = No carry-out from the 4th or 8th low-order bit of the result has occurredbit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU interrupt priority level is 7 (15); user interrupts disabled.110 = CPU interrupt priority level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU interrupt priority level is 4 (12)011 = CPU interrupt priority level is 3 (11)010 = CPU interrupt priority level is 2 (10)001 = CPU interrupt priority level is 1 (9)000 = CPU interrupt priority level is 0 (8)
bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress
bit 3 N: ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)
bit 2 OV: ALU Overflow bit1 = Overflow occurred for signed (2�s complement) arithmetic in this arithmetic operation0 = No overflow has occurred
bit 1 Z: ALU Zero bit1 = An operation which effects the Z bit has set it at some time in the past0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
DS39881C-page 20 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.3 Arithmetic Logic Unit (ALU)The PIC24F ALU is 16 bits wide and is capable of addi-tion, subtraction, bit shifts and logic operations. Unlessotherwise mentioned, arithmetic operations are 2�scomplement in nature. Depending on the operation, theALU may affect the values of the Carry (C), Zero (Z),Negative (N), Overflow (OV) and Digit Carry (DC)Status bits in the SR register. The C and DC Status bitsoperate as Borrow and Digit Borrow bits, respectively,for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,depending on the mode of the instruction that is used.Data for the ALU operation can come from the Wregister array, or data memory, depending on theaddressing mode of the instruction. Likewise, outputdata from the ALU can be written to the W register arrayor a data memory location.
The PIC24F CPU incorporates hardware support forboth multiplication and division. This includes adedicated hardware multiplier and support hardwarefor 16-bit divisor division.
2.3.1 MULTIPLIERThe ALU contains a high-speed, 17-bit x 17-bitmultiplier. It supports unsigned, signed or mixed signoperation in several multiplication modes:
1. 16-bit x 16-bit signed2. 16-bit x 16-bit unsigned3. 16-bit signed x 5-bit (literal) unsigned4. 16-bit unsigned x 16-bit unsigned5. 16-bit unsigned x 5-bit (literal) unsigned6. 16-bit unsigned x 16-bit signed7. 8-bit unsigned x 8-bit unsigned
REGISTER 2-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0� � � � IPL3(1) PSV � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as �0�bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data space
bit 1-0 Unimplemented: Read as �0�
Note 1: User interrupts are disabled when IPL3 = 1.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 21
PIC24FJ64GA004 FAMILY
2.3.2 DIVIDERThe divide block supports 32-bit/16-bit and 16-bit/16-bitsigned and unsigned integer divide operations with thefollowing data sizes:1. 32-bit signed/16-bit signed divide2. 32-bit unsigned/16-bit unsigned divide3. 16-bit signed/16-bit signed divide4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0and the remainder in W1. Sixteen-bit signed andunsigned DIV instructions can specify any W registerfor both the 16-bit divisor (Wn), and any W register(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.The divide algorithm takes one cycle per bit of divisor,so both 32-bit/16-bit and 16-bit/16-bit instructions takethe same number of cycles to execute.
2.3.3 MULTI-BIT SHIFT SUPPORTThe PIC24F ALU supports both single bit andsingle-cycle, multi-bit arithmetic and logic shifts.Multi-bit shifts are implemented using a shifter block,capable of performing up to a 15-bit arithmetic rightshift, or up to a 15-bit left shift, in a single cycle. Allmulti-bit shift instructions only support Register DirectAddressing for both the operand source and resultdestination.
A full summary of instructions that use the shiftoperation is provided below in Table 2-2.
TABLE 2-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATIONInstruction Description
ASR Arithmetic shift right source register by one or more bits.SL Shift left source register by one or more bits.LSR Logical shift right source register by one or more bits.
DS39881C-page 22 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.0 MEMORY ORGANIZATIONAs Harvard architecture devices, PIC24F micro-controllers feature separate program and data memoryspaces and busses. This architecture also allows thedirect access of program memory from the data spaceduring code execution.
3.1 Program Address SpaceThe program address memory space of thePIC24FJ64GA004 family devices is 4M instructions.The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-gram execution, or from table operation or data spaceremapping, as described in Section 3.3 �InterfacingProgram and Data Memory Spaces�.
User access to the program memory space is restrictedto the lower half of the address range (000000h to7FFFFFh). The exception is the use of TBLRD/TBLWToperations which use TBLPAG<7> to permit access tothe Configuration bits and Device ID sections of theconfiguration memory space.
Memory maps for the PIC24FJ64GA004 family ofdevices are shown in Figure 3-1.
FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES
000000h
0000FEh
000002h
000100h
F8000EhF80010h
FEFFFEh
FFFFFFh
000004h
000200h0001FEh000104h
Reset Address
User FlashProgram Memory(11K instructions)
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector TableReserved
Interrupt Vector Table
PIC24FJ32GA
Con
figur
atio
n M
emor
y Sp
ace
Use
r Mem
ory
Spac
e
Flash Config Words
Note: Memory areas are not shown to scale.
Reset Address
Device Config Registers
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector TableReserved
Interrupt Vector Table
PIC24FJ48GA
FF0000h
F7FFFEhF80000hDevice Config Registers
800000h7FFFFFh
Reserved
Reserved
Flash Config Words
00AC00h00ABFEh
UnimplementedRead �0�
UnimplementedRead �0�
Reset Address
Device Config Registers
User FlashProgram Memory(22K instructions)
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector TableReserved
Interrupt Vector Table
PIC24FJ64GA
Reserved
Flash Config Words
UnimplementedRead �0�
Reset Address
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector TableReserved
Interrupt Vector Table
PIC24FJ16GA
Flash Config Words
Device Config Registers
Reserved
UnimplementedRead �0�
005800h0057FEh
002C00h002BFEh
User FlashProgram Memory(5.5K instructions)
008400h0083FEh
User FlashProgram Memory(16K instructions)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 23
PIC24FJ64GA004 FAMILY
3.1.1 PROGRAM MEMORYORGANIZATIONThe program memory space is organized inword-addressable blocks. Although it is treated as24 bits wide, it is more appropriate to think of eachaddress of the program memory as a lower and upperword, with the upper byte of the upper word beingunimplemented. The lower word always has an evenaddress, while the upper word has an odd address(Figure 3-2).
Program memory addresses are always word-alignedon the lower word, and addresses are incremented ordecremented by two during code execution. Thisarrangement also provides compatibility with datamemory space addressing and makes it possible toaccess data in the program memory space.
3.1.2 HARD MEMORY VECTORSAll PIC24F devices reserve the addresses between00000h and 000200h for hard coded program execu-tion vectors. A hardware Reset vector is provided toredirect code execution from the default value of thePC on device Reset to the actual start of code. A GOTOinstruction is programmed by the user at 000000h withthe actual address for the start of code at 000002h.
PIC24F devices also have two interrupt vector tables,located from 000004h to 0000FFh and 000100h to0001FFh. These vector tables allow each of the manydevice interrupt sources to be handled by separateISRs. A more detailed discussion of the interrupt vectortables is provided in Section 6.1 �Interrupt VectorTable�.
3.1.3 FLASH CONFIGURATION WORDSIn PIC24FJ64GA004 family devices, the top two wordsof on-chip program memory are reserved for configura-tion information. On device Reset, the configurationinformation is copied into the appropriate Configurationregisters. The addresses of the Flash ConfigurationWord for devices in the PIC24FJ64GA004 family areshown in Table 3-1. Their location in the memory mapis shown with the other memory vectors in Figure 3-1.
The Configuration Words in program memory are acompact format. The actual Configuration bits aremapped in several different registers in the configurationmemory space. Their order in the Flash ConfigurationWords do not reflect a corresponding arrangement in theconfiguration space. Additional details on the deviceConfiguration Words are provided in Section 23.1�Configuration Bits�.
TABLE 3-1: FLASH CONFIGURATION WORDS FOR PIC24FJ64GA004 FAMILY DEVICES
FIGURE 3-2: PROGRAM MEMORY ORGANIZATION
DeviceProgram Memory
(K words)
Configuration Word
Addresses
PIC24FJ16GA 5.5 002BFCh:002BFEh
PIC24FJ32GA 11 0057FCh:0057FEh
PIC24FJ48GA 16 0083FCh:0083FEh
PIC24FJ64GA 22 00ABFCh:00ABFEh
0816
PC Address
000000h000002h000004h000006h
230000000000000000
0000000000000000
Program Memory�Phantom� Byte
(read as �0�)
least significant wordmost significant word
Instruction Width
000001h000003h000005h000007h
mswAddress (lsw Address)
DS39881C-page 24 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.2 Data Address SpaceThe PIC24F core has a separate, 16-bit wide data mem-ory space, addressable as a single linear range. Thedata space is accessed using two Address GenerationUnits (AGUs), one each for read and write operations.The data space memory map is shown in Figure 3-3.All Effective Addresses (EAs) in the data memory spaceare 16 bits wide and point to bytes within the data space.This gives a data space address range of 64 Kbytes or32K words. The lower half of the data memory space(that is, when EA<15> = 0) is used for implementedmemory addresses, while the upper half (EA<15> = 1) isreserved for the program space visibility area (seeSection 3.3.3 �Reading Data From Program MemoryUsing Program Space Visibility�).
PIC24FJ64GA family devices implement a total of8 Kbytes of data memory. Should an EA point to alocation outside of this area, an all zero word or byte willbe returned.
3.2.1 DATA SPACE WIDTHThe data memory space is organized inbyte-addressable, 16-bit wide blocks. Data is alignedin data memory and registers as 16-bit words, but alldata space EAs resolve to bytes. The Least SignificantBytes of each word have even addresses, while theMost Significant Bytes have odd addresses.
FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)
0000h07FEh
FFFEh
LSBAddressLSBMSB
MSBAddress
0001h07FFh
1FFFh
FFFFh
8001h 8000h7FFFh
0801h 0800h
2001h
Near
1FFEh
SFRSFR Space
Data RAM
2000h
7FFFh
Program SpaceVisibility Area
Note 1: Data memory areas are not shown to scale.2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.
27FEh(2)
2800h27FFh(2)
2801h
Space
Data SpaceImplemented
Data RAM
UnimplementedRead as �0�
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 25
PIC24FJ64GA004 FAMILY
3.2.2 DATA MEMORY ORGANIZATIONAND ALIGNMENTTo maintain backward compatibility with PIC® devicesand improve data space memory usage efficiency, thePIC24F instruction set supports both word and byteoperations. As a consequence of byte accessibility, allEffective Address (EA) calculations are internally scaledto step through word-aligned memory. For example, thecore recognizes that Post-Modified Register IndirectAddressing mode [Ws++] will result in a value of Ws + 1for byte operations and Ws + 2 for word operations.
Data byte reads will read the complete word which con-tains the byte, using the LSb of any EA to determinewhich byte to select. The selected byte is placed ontothe LSB of the data path. That is, data memory and reg-isters are organized as two parallel, byte-wide entitieswith shared (word) address decode but separate writelines. Data byte writes only write to the correspondingside of the array or register which matches the byteaddress.
All word accesses must be aligned to an even address.Misaligned word data fetches are not supported, socare must be taken when mixing byte and word opera-tions, or translating from 8-bit MCU code. If amisaligned read or write is attempted, an address errortrap will be generated. If the error occurred on a read,the instruction underway is completed; if it occurred ona write, the instruction will be executed but the write willnot occur. In either case, a trap is then executed, allow-ing the system and/or user to examine the machinestate prior to execution of the address Fault.
All byte loads into any W register are loaded into theLeast Significant Byte. The Most Significant Byte is notmodified.
A sign-extend instruction (SE) is provided to allowusers to translate 8-bit signed data to 16-bit signedvalues. Alternatively, for 16-bit unsigned data, userscan clear the MSB of any W register by executing azero-extend (ZE) instruction on the appropriateaddress.
Although most instructions are capable of operating onword or byte data sizes, it should be noted that someinstructions operate only on words.
3.2.3 NEAR DATA SPACEThe 8-Kbyte area between 0000h and 1FFFh isreferred to as the near data space. Locations in thisspace are directly addressable via a 13-bit absoluteaddress field within all memory direct instructions. Theremainder of the data space is addressable indirectly.Additionally, the whole data space is addressable usingMOV instructions, which support Memory DirectAddressing with a 16-bit address field.
3.2.4 SFR SPACEThe first 2 Kbytes of the near data space, from 0000hto 07FFh, are primarily occupied with Special FunctionRegisters (SFRs). These are used by the PIC24F coreand peripheral modules for controlling the operation ofthe device.
SFRs are distributed among the modules that theycontrol and are generally grouped together by module.Much of the SFR space contains unused addresses;these are read as �0�. A diagram of the SFR space,showing where SFRs are actually implemented, isshown in Table 3-2. Each implemented area indicatesa 32-byte region where at least one address is imple-mented as an SFR. A complete listing of implementedSFRs, including their addresses, is shown in Tables 3-3through 3-24.
TABLE 3-2: IMPLEMENTED REGIONS OF SFR DATA SPACESFR Space Address
xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0
000h Core ICN Interrupts �100h Timers Capture � Compare � � �200h I2C� UART SPI � � I/O300h A/D � � � � � �400h � � � � � � � �500h � � � � � � � �600h PMP RTC/Comp CRC � PPS700h � � System NVM/PMD � � � �
Legend: � = No implemented SFRs in this block
DS39881C-page 26 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TAB
LE 3
-3:
CPU
CO
RE
REG
ISTE
RS
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
WR
EG
000
00W
orki
ng R
egis
ter 0
0000
WR
EG
100
02W
orki
ng R
egis
ter 1
0000
WR
EG
200
04W
orki
ng R
egis
ter 2
0000
WR
EG
300
06W
orki
ng R
egis
ter 3
0000
WR
EG
400
08W
orki
ng R
egis
ter 4
0000
WR
EG
500
0AW
orki
ng R
egis
ter 5
0000
WR
EG
600
0CW
orki
ng R
egis
ter 6
0000
WR
EG
700
0EW
orki
ng R
egis
ter 7
0000
WR
EG
800
10W
orki
ng R
egis
ter 8
0000
WR
EG
900
12W
orki
ng R
egis
ter 9
0000
WR
EG
1000
14W
orki
ng R
egis
ter 1
00000
WR
EG
1100
16W
orki
ng R
egis
ter 1
10000
WR
EG
1200
18W
orki
ng R
egis
ter 1
20000
WR
EG
1300
1AW
orki
ng R
egis
ter 1
30000
WR
EG
1400
1CW
orki
ng R
egis
ter 1
40000
WR
EG
1500
1EW
orki
ng R
egis
ter 1
50800
SP
LIM
0020
Stac
k P
oint
er L
imit
Valu
e R
egis
ter
xxxx
PC
L00
2EP
rogr
am C
ount
er L
ow B
yte
Reg
iste
r0000
PC
H00
30�
��
��
��
�P
rogr
am C
ount
er R
egis
ter H
igh
Byt
e0000
TBLP
AG
0032
��
��
��
��
Tabl
e M
emor
y P
age
Add
ress
Reg
iste
r0000
PS
VPA
G00
34�
��
��
��
�P
rogr
am S
pace
Vis
ibili
ty P
age
Addr
ess
Reg
iste
r0000
RC
OU
NT
0036
Rep
eat L
oop
Cou
nter
Reg
iste
rxxxx
SR
0042
��
��
��
�D
CIP
L2IP
L1IP
L0R
AN
OV
ZC
0000
CO
RC
ON
0044
��
��
��
��
��
��
IPL3
PS
V�
�0000
DIS
ICN
T00
52�
�D
isab
le In
terr
upts
Cou
nter
Reg
iste
rxxxx
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-4:
ICN
REG
ISTE
R M
AP
File
Na
me
Addr
Bit 1
5Bi
t 14
Bit 1
3Bi
t 12
Bit 1
1Bi
t 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Rese
ts
CNE
N100
60C
N15I
ECN
14IE
CN13
IECN
12IE
CN1
1IE
CN10
IE(1
)C
N9IE
(1)
CN8
IE(1
)CN
7IE
CN6I
EC
N5IE
CN4I
ECN
3IE
CN2I
EC
N1IE
CN0
IE0000
CNE
N200
62�
CN30
IECN
29IE
CN28
IE(1
)C
N27I
ECN
26IE
(1)
CN25
IE(1
)CN
24IE
CN2
3IE
CN2
2IE
CN21
IECN
20IE
(1)
CN1
9IE(1
)C
N18I
E(1)
CN17
IE(1
)CN
16IE
0000
CNP
U100
68C
N15P
UECN
14PU
ECN
13PU
ECN
12PU
EC
N11P
UE
CN10
PUE(1
)C
N9PU
E(1)
CN8
PUE(1
)CN
7PUE
CN6P
UEC
N5PU
ECN
4PU
ECN
3PUE
CN2P
UEC
N1PU
EC
N0PU
E0000
CNP
U200
6A�
CN30
PUE
CN29
PUE
CN28
PUE(1
)C
N27P
UE
CN26
PUE(1
)CN
25PU
E(1)
CN24
PUE
CN2
3PU
EC
N22P
UE
CN21
PUE
CN20
PUE(1
)C
N19P
UE(1
)C
N18P
UE(1
)CN
17PU
E(1)
CN16
PUE
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�. R
eset
val
ues
are
show
n in
hex
adec
imal
.No
te1:
Bits
are
not
ava
ilabl
e on
28-
pin
devic
es; r
ead
as �0
�.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 27
PIC24FJ64GA004 FAMILY
TABLE
3-5
:IN
TER
RU
PT C
ON
TRO
LLER
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
INTC
ON
100
80N
STD
IS�
��
��
��
��
�M
ATH
ERR
ADD
RER
RST
KER
RO
SCFA
IL�
0000
INTC
ON
200
82AL
TIVT
DIS
I�
��
��
��
��
��
INT2
EPIN
T1EP
INT0
EP0000
IFS0
0084
��
AD1I
FU
1TXI
FU
1RXI
FSP
I1IF
SPF1
IFT3
IFT2
IFO
C2I
FIC
2IF
�T1
IFO
C1I
FIC
1IF
INT0
IF0000
IFS1
0086
U2T
XIF
U2R
XIF
INT2
IFT5
IFT4
IFO
C4I
FO
C3I
F�
��
�IN
T1IF
CN
IFC
MIF
MI2
C1I
FSI
2C1I
F0000
IFS2
0088
��
PMPI
F�
��
OC
5IF
�IC
5IF
IC4I
FIC
3IF
��
�SP
I2IF
SPF2
IF0000
IFS3
008A
�R
TCIF
��
��
��
��
��
�M
I2C
2IF
SI2C
2IF
�0000
IFS4
008C
��
��
��
�LV
DIF
��
��
CR
CIF
U2E
RIF
U1E
RIF
�0000
IEC
000
94�
�AD
1IE
U1T
XIE
U1R
XIE
SPI1
IESP
F1IE
T3IE
T2IE
OC
2IE
IC2I
E�
T1IE
OC
1IE
IC1I
EIN
T0IE
0000
IEC
100
96U
2TXI
EU
2RXI
EIN
T2IE
T5IE
T4IE
OC
4IE
OC
3IE
��
��
INT1
IEC
NIE
CM
IEM
I2C
1IE
SI2C
1IE
0000
IEC
200
98�
�PM
PIE
��
�O
C5I
E�
IC5I
EIC
4IE
IC3I
E�
��
SPI2
IESP
F2IE
0000
IEC
300
9A�
RTC
IE�
��
��
��
��
��
MI2
C2I
ESI
2C2I
E�
0000
IEC
400
9C�
��
��
��
LVD
IE�
��
�C
RC
IEU
2ER
IEU
1ER
IE�
0000
IPC
000
A4�
T1IP
2T1
IP1
T1IP
0�
OC
1IP2
OC
1IP1
OC
1IP0
�IC
1IP2
IC1I
P1IC
1IP0
�IN
T0IP
2IN
T0IP
1IN
T0IP
04444
IPC
100
A6�
T2IP
2T2
IP1
T2IP
0�
OC
2IP2
OC
2IP1
OC
2IP0
�IC
2IP2
IC2I
P1IC
2IP0
��
��
4444
IPC
200
A8�
U1R
XIP2
U1R
XIP1
U1R
XIP0
�SP
I1IP
2SP
I1IP
1SP
I1IP
0�
SPF1
IP2
SPF1
IP1
SPF1
IP0
�T3
IP2
T3IP
1T3
IP0
4444
IPC
300
AA�
��
��
��
��
AD1I
P2AD
1IP1
AD1I
P0�
U1T
XIP2
U1T
XIP1
U1T
XIP0
4444
IPC
400
AC�
CN
IP2
CN
IP1
CN
IP0
�C
MIP
2C
MIP
1C
MIP
0�
MI2
C1P
2M
I2C
1P1
MI2
C1P
0�
SI2C
1P2
SI2C
1P1
SI2C
1P0
4444
IPC
500
AE�
��
��
��
��
��
��
INT1
IP2
INT1
IP1
INT1
IP0
4444
IPC
600
B0�
T4IP
2T4
IP1
T4IP
0�
OC
4IP2
OC
4IP1
OC
4IP0
�O
C3I
P2O
C3I
P1O
C3I
P0�
��
�4444
IPC
700
B2�
U2T
XIP2
U2T
XIP1
U2T
XIP0
�U
2RXI
P2U
2RXI
P1U
2RXI
P0�
INT2
IP2
INT2
IP1
INT2
IP0
�T5
IP2
T5IP
1T5
IP0
4444
IPC
800
B4�
��
��
��
��
SPI2
IP2
SPI2
IP1
SPI2
IP0
�SP
F2IP
2SP
F2IP
1SP
F2IP
04444
IPC
900
B6�
IC5I
P2IC
5IP1
IC5I
P0�
IC4I
P2IC
4IP1
IC4I
P0�
IC3I
P2IC
3IP1
IC3I
P0�
��
�4444
IPC
1000
B8�
��
��
��
��
OC
5IP2
OC
5IP1
OC
5IP0
��
��
4444
IPC
1100
BA�
��
��
��
��
PMPI
P2PM
PIP1
PMPI
P0�
��
�4444
IPC
1200
BC�
��
��
MI2
C2P
2M
I2C
2P1
MI2
C2P
0�
SI2C
2P2
SI2C
2P1
SI2C
2P0
��
��
4444
IPC
1500
C2
��
��
�R
TCIP
2R
TCIP
1R
TCIP
0�
��
��
��
�4444
IPC
1600
C4
�C
RC
IP2
CR
CIP
1C
RC
IP0
�U
2ER
IP2
U2E
RIP
1U
2ER
IP0
�U
1ER
IP2
U1E
RIP
1U
1ER
IP0
��
��
4444
IPC
1800
C8
��
��
��
��
��
��
�LV
DIP
2LV
DIP
1LV
DIP
04444
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
DS39881C-page 28 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TAB
LE 3
-6:
TIM
ER R
EGIS
TER
MA
P
File
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
TMR
101
00Ti
mer
1 R
egis
ter
0000
PR
101
02Ti
mer
1 P
erio
d R
egis
ter
FFFF
T1C
ON
0104
TON
�TS
IDL
��
��
��
TGAT
ETC
KP
S1TC
KPS
0�
TSY
NC
TCS
�0000
TMR
201
06Ti
mer
2 R
egis
ter
0000
TMR
3HLD
0108
Tim
er3
Hol
ding
Reg
iste
r (fo
r 32-
bit t
imer
ope
ratio
ns o
nly)
0000
TMR
301
0ATi
mer
3 R
egis
ter
0000
PR
201
0CTi
mer
2 P
erio
d R
egis
ter
FFFF
PR
301
0ETi
mer
3 P
erio
d R
egis
ter
FFFF
T2C
ON
0110
TON
�TS
IDL
��
��
��
TGAT
ETC
KPS
1TC
KPS
0T3
2�
TCS
�0000
T3C
ON
0112
TON
�TS
IDL
��
��
��
TGAT
ETC
KPS
1TC
KPS
0�
�TC
S�
0000
TMR
401
14Ti
mer
4 R
egis
ter
0000
TMR
5HLD
0116
Tim
er5
Hol
ding
Reg
iste
r (fo
r 32-
bit o
pera
tions
onl
y)0000
TMR
501
18Ti
mer
5 R
egis
ter
0000
PR
401
1ATi
mer
4 P
erio
d R
egis
ter
FFFF
PR
501
1CTi
mer
5 P
erio
d R
egis
ter
FFFF
T4C
ON
011E
TON
�TS
IDL
��
��
��
TGAT
ETC
KPS
1TC
KPS
0T3
2�
TCS
�0000
T5C
ON
0120
TON
�TS
IDL
��
��
��
TGAT
ETC
KPS
1TC
KPS
0�
�TC
S�
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-7:
INPU
T C
APT
UR
E R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
IC1B
UF
0140
Inpu
t 1 C
aptu
re R
egis
ter
FFFF
IC1C
ON
0142
��
ICS
IDL
��
��
�IC
TMR
ICI1
ICI0
ICO
VIC
BNE
ICM
2IC
M1
ICM
00000
IC2B
UF
0144
Inpu
t 2 C
aptu
re R
egis
ter
FFFF
IC2C
ON
0146
��
ICS
IDL
��
��
�IC
TMR
ICI1
ICI0
ICO
VIC
BNE
ICM
2IC
M1
ICM
00000
IC3B
UF
0148
Inpu
t 3 C
aptu
re R
egis
ter
FFFF
IC3C
ON
014A
��
ICS
IDL
��
��
�IC
TMR
ICI1
ICI0
ICO
VIC
BNE
ICM
2IC
M1
ICM
00000
IC4B
UF
014C
Inpu
t 4 C
aptu
re R
egis
ter
FFFF
IC4C
ON
014E
��
ICS
IDL
��
��
�IC
TMR
ICI1
ICI0
ICO
VIC
BNE
ICM
2IC
M1
ICM
00000
IC5B
UF
0150
Inpu
t 5 C
aptu
re R
egis
ter
FFFF
IC5C
ON
0152
��
ICS
IDL
��
��
�IC
TMR
ICI1
ICI0
ICO
VIC
BNE
ICM
2IC
M1
ICM
00000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 29
PIC24FJ64GA004 FAMILY
TAB
LE 3
-8:
OU
TPU
T C
OM
PAR
E R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
OC
1RS
0180
Out
put C
ompa
re 1
Sec
onda
ry R
egis
ter
FFFF
OC
1R01
82O
utpu
t Com
pare
1 R
egis
ter
FFFF
OC
1CO
N01
84�
�O
CS
IDL
��
��
��
��
OC
FLT
OC
TSEL
OC
M2
OC
M1
OC
M0
0000
OC
2RS
0186
Out
put C
ompa
re 2
Sec
onda
ry R
egis
ter
FFFF
OC
2R01
88O
utpu
t Com
pare
2 R
egis
ter
FFFF
OC
2CO
N01
8A�
�O
CS
IDL
��
��
��
��
OC
FLT
OC
TSEL
OC
M2
OC
M1
OC
M0
0000
OC
3RS
018C
Out
put C
ompa
re 3
Sec
onda
ry R
egis
ter
FFFF
OC
3R01
8EO
utpu
t Com
pare
3 R
egis
ter
FFFF
OC
3CO
N01
90�
�O
CS
IDL
��
��
��
��
OC
FLT
OC
TSEL
OC
M2
OC
M1
OC
M0
0000
OC
4RS
0192
Out
put C
ompa
re 4
Sec
onda
ry R
egis
ter
FFFF
OC
4R01
94O
utpu
t Com
pare
4 R
egis
ter
FFFF
OC
4CO
N01
96�
�O
CS
IDL
��
��
��
��
OC
FLT
OC
TSEL
OC
M2
OC
M1
OC
M0
0000
OC
5RS
0198
Out
put C
ompa
re 5
Sec
onda
ry R
egis
ter
FFFF
OC
5R01
9AO
utpu
t Com
pare
5 R
egis
ter
FFFF
OC
5CO
N01
9C�
�O
CS
IDL
��
��
��
��
OC
FLT
OC
TSEL
OC
M2
OC
M1
OC
M0
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-9:
I2 C�
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
I2C
1RC
V02
00�
��
��
��
�R
ecei
ve R
egis
ter 1
0000
I2C
1TR
N02
02�
��
��
��
�Tr
ansm
it R
egis
ter 1
00FF
I2C
1BR
G02
04�
��
��
��
Bau
d R
ate
Gen
erat
or R
egis
ter 1
0000
I2C
1CO
N02
06I2
CE
N�
I2C
SID
LSC
LRE
LIP
MIE
NA1
0MD
ISS
LWS
MEN
GC
EN
STR
EN
AC
KD
TA
CK
EN
RC
EN
PEN
RSE
NS
EN
1000
I2C
1STA
T02
08A
CK
STA
TTR
STA
T�
��
BC
LG
CS
TAT
ADD
10IW
CO
LI2
CO
VD
/AP
SR
/WR
BF
TBF
0000
I2C
1AD
D02
0A�
��
��
�A
ddre
ss R
egis
ter 1
0000
I2C
1MS
K02
0C�
��
��
�A
MS
K9
AMS
K8
AMS
K7
AM
SK6
AM
SK5
AM
SK4
AM
SK
3A
MS
K2
AM
SK
1A
MSK
00000
I2C
2RC
V02
10�
��
��
��
�R
ecei
ve R
egis
ter 2
0000
I2C
2TR
N02
12�
��
��
��
�Tr
ansm
it R
egis
ter 2
00FF
I2C
2BR
G02
14�
��
��
��
Bau
d R
ate
Gen
erat
or R
egis
ter 2
0000
I2C
2CO
N02
16I2
CE
N�
I2C
SID
LSC
LRE
LIP
MIE
NA1
0MD
ISS
LWS
MEN
GC
EN
STR
EN
AC
KD
TA
CK
EN
RC
EN
PEN
RSE
NS
EN
1000
I2C
2STA
T02
18AC
KS
TAT
TRS
TAT
��
�B
CL
GC
STA
TAD
D10
IWC
OL
I2C
OV
D/A
PS
R/W
RB
FTB
F0000
I2C
2AD
D02
1A�
��
��
�A
ddre
ss R
egis
ter 2
0000
I2C
2MS
K02
1C�
��
��
�A
MS
K9
AMS
K8
AMS
K7
AM
SK6
AM
SK5
AM
SK4
AM
SK
3A
MS
K2
AM
SK
1A
MSK
00000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
DS39881C-page 30 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TAB
LE 3
-10:
UA
RT
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
U1M
OD
E02
20U
ARTE
N�
USI
DL
IREN
RTS
MD
�U
EN1
UEN
0W
AKE
LPBA
CK
ABAU
DR
XIN
VBR
GH
PDSE
L1PD
SEL0
STSE
L0000
U1S
TA02
22U
TXIS
EL1
UTX
INV
UTX
ISEL
0�
UTX
BRK
UTX
ENU
TXBF
TRM
TU
RXI
SEL1
UR
XISE
L0AD
DEN
RID
LEPE
RR
FER
RO
ERR
UR
XDA
0110
U1T
XREG
0224
��
��
��
�U
TX8
UTX
7U
TX6
UTX
5U
TX4
UTX
3U
TX2
UTX
1U
TX0
0000
U1R
XREG
0226
��
��
��
�U
RX8
UR
X7U
RX6
UR
X5U
RX4
UR
X3U
RX2
UR
X1U
RX0
0000
U1B
RG
0228
Baud
Rat
e G
ener
ator
Pre
scal
er R
egis
ter
0000
U2M
OD
E02
30U
ARTE
N�
USI
DL
IREN
RTS
MD
�U
EN1
UEN
0W
AKE
LPBA
CK
ABAU
DR
XIN
VBR
GH
PDSE
L1PD
SEL0
STSE
L0000
U2S
TA02
32U
TXIS
EL1
UTX
INV
UTX
ISEL
0�
UTX
BRK
UTX
ENU
TXBF
TRM
TU
RC
ISEL
1U
RC
ISEL
0AD
DEN
RID
LEPE
RR
FER
RO
ERR
UR
XDA
0110
U2T
XREG
0234
��
��
��
�U
TX8
UTX
7U
TX6
UTX
5U
TX4
UTX
3U
TX2
UTX
1U
TX0
0000
U2R
XREG
0236
��
��
��
�U
RX8
UR
X7U
RX6
UR
X5U
RX4
UR
X3U
RX2
UR
X1U
RX0
0000
U2B
RG
0238
Baud
Rat
e G
ener
ator
Pre
scal
er0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-11:
SPI R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
SPI1
STAT
0240
SPIE
N�
SPIS
IDL
��
SPIB
EC2
SPIB
EC1
SPIB
EC0
SRM
PTSP
IRO
VSR
XMPT
SISE
L2SI
SEL1
SISE
L0SP
ITBF
SPIR
BF0000
SPI1
CO
N1
0242
��
�D
ISSC
KD
ISSD
OM
OD
E16
SMP
CKE
SSEN
CKP
MST
ENSP
RE2
SPR
E1SP
RE0
PPR
E1PP
RE0
0000
SPI1
CO
N2
0244
FRM
ENSP
IFSD
SPIF
POL
��
��
��
��
��
�SP
IFE
SPIB
EN0000
SPI1
BUF
0248
SPI1
Tra
nsm
it/R
ecei
ve B
uffe
r0000
SPI2
STAT
0260
SPIE
N�
SPIS
IDL
��
SPIB
EC2
SPIB
EC1
SPIB
EC0
SRM
PTSP
IRO
VSR
XMPT
SISE
L2SI
SEL1
SISE
L0SP
ITBF
SPIR
BF0000
SPI2
CO
N1
0262
��
�D
ISSC
KD
ISSD
OM
OD
E16
SMP
CKE
SSEN
CKP
MST
ENSP
RE2
SPR
E1SP
RE0
PPR
E1PP
RE0
0000
SPI2
CO
N2
0264
FRM
ENSP
IFSD
SPIF
POL
��
��
��
��
��
�SP
IFE
SPIB
EN0000
SPI2
BUF
0268
SPI2
Tra
nsm
it/R
ecei
ve B
uffe
r0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 31
PIC24FJ64GA004 FAMILY
TABLE
3-1
2:PO
RTA
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
TRIS
A02
C0
��
��
�TR
ISA1
0(1)
TRIS
A9(1
)TR
ISA8
(1)
TRIS
A7(1
)�
�TR
ISA4
TRIS
A3(2
)TR
ISA2
(3)
TRIS
A1TR
ISA0
079F
POR
TA02
C2
��
��
�R
A10(1
)R
A9(1
)R
A8(1
)R
A7(1
)�
�R
A4R
A3(2
)R
A2(3
)R
A1R
A00000
LATA
02C
4�
��
��
LATA
10(1
)LA
TA9(1
)LA
TA8(1
)LA
TA7(1
)�
�LA
TA4
LATA
3(2)
LATA
2(3)
LATA
1LA
TA0
0000
OD
CA
02C
6�
��
��
OD
A10(1
)O
DA9
(1)
OD
A8(1
)O
DA7
(1)
��
OD
A4O
DA3
(2)
OD
A2(3
)O
DA1
OD
A00000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
Not
e1:
Bits
are
not
ava
ilabl
e on
28-
pin
devi
ces;
read
as
�0�.
2:B
its a
re a
vaila
ble
only
whe
n th
e pr
imar
y os
cilla
tor i
s di
sabl
ed (P
OS
CM
D<1
:0>
=00
); ot
herw
ise
read
as
�0�.
3:B
its a
re a
vaila
ble
only
whe
n th
e pr
imar
y os
cilla
tor i
s di
sabl
ed o
r EC
mod
e is
sel
ecte
d (P
OS
CM
D<1
:0>
=00
or 1
1) a
nd C
LKO
is d
isab
led
(OSC
IOFN
C=0
); ot
herw
ise,
read
as
�0�.
TAB
LE 3
-13:
POR
TB R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
TRIS
B02
C8
TRIS
B15
TRIS
B14
TRIS
B13
TRIS
B12
TRIS
B11
TRIS
B10
TRIS
B9
TRIS
B8
TRIS
B7
TRIS
B6TR
ISB
5TR
ISB
4TR
ISB
3TR
ISB
2TR
ISB
1TR
ISB0
FFFF
PO
RTB
02C
AR
B15
RB1
4R
B13
RB
12R
B11
RB
10R
B9
RB
8R
B7R
B6
RB
5R
B4
RB
3R
B2R
B1
RB
00000
LATB
02C
CLA
TB15
LATB
14LA
TB13
LATB
12LA
TB11
LATB
10LA
TB9
LATB
8LA
TB7
LATB
6LA
TB5
LATB
4LA
TB3
LATB
2LA
TB1
LATB
00000
OD
CB
02C
EO
DB
15O
DB
14O
DB
13O
DB
12O
DB
11O
DB1
0O
DB9
OD
B8
OD
B7
OD
B6
OD
B5
OD
B4O
DB
3O
DB
2O
DB
1O
DB
00000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-14:
POR
TC R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
TRIS
C(1
)02
D0
��
��
��
TRIS
C9
TRIS
C8
TRIS
C7
TRIS
C6
TRIS
C5
TRIS
C4
TRIS
C3
TRIS
C2
TRIS
C1
TRIS
C0
03FF
PO
RTC
(1)
02D
2�
��
��
�R
C9
RC
8R
C7
RC
6R
C5
RC
4R
C3
RC
2R
C1
RC
00000
LATC
(1)
02D
4�
��
��
�LA
TC9
LATC
8LA
TC7
LATC
6LA
TC5
LATC
4LA
TC3
LATC
2LA
TC1
LATC
00000
OD
CC
(1)
02D
6�
��
��
�O
DC
9O
SC
8O
DC
7O
DC
6O
DC
5O
DC
4O
DC
3O
DC
2O
DC
1O
DC
00000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
Not
e1:
Bits
are
not
ava
ilabl
e on
28-
pin
devi
ces;
read
as
�0�.
TAB
LE 3
-15:
PAD
CO
NFI
GU
RA
TIO
N R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
PAD
CFG
102
FC�
��
��
��
��
��
��
�R
TSE
CS
EL
PM
PTTL
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
DS39881C-page 32 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TAB
LE 3
-16:
AD
C R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
ADC
1BU
F003
00AD
C D
ata
Buffe
r 0xxxx
ADC
1BU
F103
02AD
C D
ata
Buffe
r 1xxxx
ADC
1BU
F203
04AD
C D
ata
Buffe
r 2xxxx
ADC
1BU
F303
06AD
C D
ata
Buffe
r 3xxxx
ADC
1BU
F403
08AD
C D
ata
Buffe
r 4xxxx
ADC
1BU
F503
0AAD
C D
ata
Buffe
r 5xxxx
ADC
1BU
F603
0CAD
C D
ata
Buffe
r 6xxxx
ADC
1BU
F703
0EAD
C D
ata
Buffe
r 7xxxx
ADC
1BU
F803
10AD
C D
ata
Buffe
r 8xxxx
ADC
1BU
F903
12AD
C D
ata
Buffe
r 9xxxx
ADC
1BU
FA03
14AD
C D
ata
Buffe
r 10
xxxx
ADC
1BU
FB03
16AD
C D
ata
Buffe
r 11
xxxx
ADC
1BU
FC03
18AD
C D
ata
Buffe
r 12
xxxx
ADC
1BU
FD03
1AAD
C D
ata
Buffe
r 13
xxxx
ADC
1BU
FE03
1CAD
C D
ata
Buffe
r 14
xxxx
ADC
1BU
FF03
1EAD
C D
ata
Buffe
r 15
xxxx
AD1C
ON
103
20AD
ON
�AD
SID
L�
��
FOR
M1
FOR
M0
SSR
C2
SSR
C1
SSR
C0
��
ASAM
SAM
PD
ON
E0000
AD1C
ON
203
22VC
FG2
VCFG
1VC
FG0
��
CSC
NA
��
BUFS
�SM
PI3
SMPI
2SM
PI1
SMPI
0BU
FMAL
TS0000
AD1C
ON
303
24AD
RC
��
SAM
C4
SAM
C3
SAM
C2
SAM
C1
SAM
C0
ADC
S7AD
CS6
ADC
S5AD
CS4
ADC
S3AD
CS2
ADC
S1AD
CS0
0000
AD1C
HS
0328
CH
0NB
��
�C
H0S
B3C
H0S
B2C
H0S
B1C
H0S
B0C
H0N
A�
��
CH
0SA3
CH
0SA2
CH
0SA1
CH
0SA0
0000
AD1P
CFG
032C
PCFG
15�
�PC
FG12
PCFG
11PC
FG10
PCFG
9PC
FG8(1
)PC
FG7(1
)PC
FG6(1
)PC
FG5
PCFG
4PC
FG3
PCFG
2PC
FG1
PCFG
00000
AD1C
SSL
0330
CSS
L15
��
CSS
L12
CSS
L11
CSS
L10
CSS
L9C
SSL8
(1)
CSS
L7(1
)C
SSL6
(1)
CSS
L5C
SSL4
CSS
L3C
SSL2
CSS
L1C
SSL0
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
Not
e1:
Bits
are
not
ava
ilabl
e on
28-
pin
devi
ces;
read
as
�0�.
TAB
LE 3
-17:
PAR
ALL
EL M
AST
ER/S
LAVE
PO
RT
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
PM
CO
N06
00P
MP
EN
�P
SID
LAD
RM
UX1
ADR
MU
X0PT
BEE
NPT
WR
EN
PTR
DE
NC
SF1
CS
F0A
LP�
CS
1PB
EP
WR
SP
RD
SP
0000
PM
MO
DE
0602
BU
SY
IRQ
M1
IRQ
M0
INC
M1
INC
M0
MO
DE1
6M
OD
E1M
OD
E0
WA
ITB
1W
AIT
B0
WA
ITM
3W
AIT
M2
WA
ITM
1W
AIT
M0
WA
ITE
1W
AITE
00000
PM
AD
DR
0604
�C
S1�
��
ADD
R10
ADD
R9
ADD
R8
ADD
R7
ADD
R6
ADD
R5
ADD
R4
ADD
R3
ADD
R2
ADD
R1
ADD
R0
0000
PMD
OU
T1Pa
ralle
l Por
t Dat
a O
ut R
egis
ter 1
(Buf
fers
0 a
nd 1
)0000
PMD
OU
T206
06Pa
ralle
l Por
t Dat
a O
ut R
egis
ter 2
(Buf
fers
2 a
nd 3
)0000
PM
DIN
106
08Pa
ralle
l Por
t Dat
a In
Reg
iste
r 1 (B
uffe
rs 0
and
1)
0000
PM
DIN
206
0APa
ralle
l Por
t Dat
a In
Reg
iste
r 2 (B
uffe
rs 2
and
3)
0000
PM
AEN
060C
�PT
EN14
��
�PT
EN10
PTEN
9PT
EN8
PTEN
7PT
EN6
PTEN
5PT
EN4
PTEN
3PT
EN2
PTEN
1PT
EN0
0000
PM
STA
T06
0EIB
FIB
OV
��
IB3F
IB2F
IB1F
IB0F
OB
EO
BU
F�
�O
B3E
OB
2EO
B1E
OB
0E0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 33
PIC24FJ64GA004 FAMILY
TAB
LE 3
-18:
REA
L-TI
ME
CLO
CK
AN
D C
ALE
ND
AR
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
ALR
MVA
L06
20Al
arm
Val
ue R
egis
ter W
indo
w B
ased
on
ALR
MPT
R<1
:0>
xxxx
ALC
FGR
PT06
22AL
RM
ENC
HIM
EAM
ASK3
AMAS
K2AM
ASK1
AMAS
K0AL
RM
PTR
1AL
RM
PTR
0AR
PT7
ARPT
6AR
PT5
ARPT
4AR
PT3
ARPT
2AR
PT1
ARPT
00000
RTC
VAL
0624
RTC
C V
alue
Reg
iste
r Win
dow
Bas
ed o
n R
TCPT
R<1
:0>
xxxx
RC
FGC
AL06
26R
TCEN
�R
TCW
REN
RTC
SYN
CH
ALFS
ECR
TCO
ER
TCPT
R1
RTC
PTR
0C
AL7
CAL
6C
AL5
CAL
4C
AL3
CAL
2C
AL1
CAL
00000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-19:
DU
AL
CO
MPA
RA
TOR
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
CM
CO
N06
30C
MID
L�
C2E
VT
C1E
VT
C2E
NC
1EN
C2O
UTE
NC
1OU
TEN
C2O
UT
C1O
UT
C2I
NV
C1I
NV
C2N
EG
C2P
OS
C1N
EG
C1P
OS
0000
CV
RC
ON
0632
��
��
��
��
CVR
EN
CV
RO
EC
VR
RC
VR
SSC
VR
3C
VR
2C
VR
1C
VR0
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
TAB
LE 3
-20:
CR
C R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
CR
CC
ON
0640
��
CS
IDL
VW
OR
D4
VW
OR
D3
VWO
RD
2V
WO
RD
1V
WO
RD
0C
RC
FUL
CR
CM
PT�
CR
CG
OP
LEN
3PL
EN
2P
LEN
1P
LEN
00040
CR
CXO
R06
42X1
5X1
4X1
3X1
2X1
1X1
0X9
X8X7
X6X5
X4X3
X2X1
�0000
CR
CD
AT06
44C
RC
Dat
a In
put R
egis
ter
0000
CR
CW
DAT
0646
CR
C R
esul
t Reg
iste
r0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
DS39881C-page 34 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE
3-2
1:PE
RIP
HER
AL
PIN
SEL
ECT
REG
ISTE
R M
AP
File
N
ame
Add
rB
it 15
Bit
14B
it 13
Bit
12B
it 11
Bit
10B
it 9
Bit
8B
it 7
Bit
6B
it 5
Bit
4B
it 3
Bit
2B
it 1
Bit
0A
ll R
eset
s
RP
INR
006
80�
��
INT1
R4
INT1
R3
INT1
R2
INT1
R1
INT1
R0
��
��
��
��
1F00
RP
INR
106
82�
��
��
��
��
��
INT2
R4
INT2
R3
INT2
R2
INT2
R1
INT2
R0
001F
RP
INR
306
86�
��
T3C
KR4
T3C
KR3
T3C
KR2
T3C
KR1
T3C
KR0
��
�T2
CKR
4T2
CKR
3T2
CKR
2T2
CKR
1T2
CKR
01F1F
RP
INR
406
88�
��
T5C
KR4
T5C
KR3
T5C
KR2
T5C
KR1
T5C
KR0
��
�T4
CKR
4T4
CKR
3T4
CKR
2T4
CKR
1T4
CKR
01F1F
RP
INR
706
8E�
��
IC2R
4IC
2R3
IC2R
2IC
2R1
IC2R
0�
��
IC1R
4IC
1R3
IC1R
2IC
1R1
IC1R
01F1F
RP
INR
806
90�
��
IC4R
4IC
4R3
IC4R
2IC
4R1
IC4R
0�
��
IC3R
4IC
3R3
IC3R
2IC
3R1
IC3R
01F1F
RP
INR
906
92�
��
��
��
��
��
IC5R
4IC
5R3
IC5R
2IC
5R1
IC5R
0001F
RP
INR
1106
96�
��
OC
FBR
4O
CFB
R3
OC
FBR
2O
CFB
R1
OC
FBR
0�
��
OC
FAR
4O
CFA
R3
OC
FAR
2O
CFA
R1
OC
FAR
01F1F
RP
INR
1806
A4
��
�U
1CTS
R4
U1C
TSR
3U
1CTS
R2
U1C
TSR
1U
1CTS
R0
��
�U
1RXR
4U
1RXR
3U
1RXR
2U
1RXR
1U
1RXR
01F1F
RP
INR
1906
A6
��
�U
2CTS
R4
U2C
TSR
3U
2CTS
R2
U2C
TSR
1U
2CTS
R0
��
�U
2RXR
4U
2RXR
3U
2RXR
2U
2RXR
1U
2RXR
01F1F
RP
INR
2006
A8
��
�SC
K1R
4SC
K1R
3SC
K1R
2SC
K1R
1SC
K1R
0�
��
SDI1
R4
SDI1
R3
SDI1
R2
SDI1
R1
SDI1
R0
1F1F
RP
INR
2106
AA
��
��
��
��
��
�SS
1R4
SS1R
3SS
1R2
SS1R
1SS
1R0
001F
RP
INR
2206
AC
��
�SC
K2R
4SC
K2R
3SC
K2R
2SC
K2R
1SC
K2R
0�
��
SDI2
R4
SDI2
R3
SDI2
R2
SDI2
R1
SDI2
R0
1F1F
RP
INR
2306
AE
��
��
��
��
��
�SS
2R4
SS2R
3SS
2R2
SS2R
1SS
2R0
001F
RP
OR
006
C0
��
�R
P1R
4R
P1R
3R
P1R
2R
P1R
1R
P1R
0�
��
RP0
R4
RP0
R3
RP0
R2
RP0
R1
RP0
R0
0000
RP
OR
106
C2
��
�R
P3R
4R
P3R
3R
P3R
2R
P3R
1R
P3R
0�
��
RP2
R4
RP2
R3
RP2
R2
RP2
R1
RP2
R0
0000
RP
OR
206
C4
��
�R
P5R
4R
P5R
3R
P5R
2R
P5R
1R
P5R
0�
��
RP4
R4
RP4
R3
RP4
R2
RP4
R1
RP4
R0
0000
RP
OR
306
C6
��
�R
P7R
4R
P7R
3R
P7R
2R
P7R
1R
P7R
0�
��
RP6
R4
RP6
R3
RP6
R2
RP6
R1
RP6
R0
0000
RP
OR
406
C8
��
�R
P9R
4R
P9R
3R
P9R
2R
P9R
1R
P9R
0�
��
RP8
R4
RP8
R3
RP8
R2
RP8
R1
RP8
R0
0000
RP
OR
506
CA
��
�R
P11R
4R
P11R
3R
P11R
2R
P11R
1R
P11R
0�
��
RP1
0R4
RP1
0R3
RP1
0R2
RP1
0R1
RP1
0R0
0000
RP
OR
606
CC
��
�R
P13R
4R
P13R
3R
P13R
2R
P13R
1R
P13R
0�
��
RP1
2R4
RP1
2R3
RP1
2R2
RP1
2R1
RP1
2R0
0000
RP
OR
706
CE
��
�R
P15R
4R
P15R
3R
P15R
2R
P15R
1R
P15R
0�
��
RP1
4R4
RP1
4R3
RP1
4R2
RP1
4R1
RP1
4R0
0000
RP
OR
806
D0
��
�R
P17R
4(1)
RP1
7R3(1
)R
P17R
2(1)
RP1
7R1(1
)R
P17R
0(1)
��
�R
P16R
4(1)
RP1
6R3(1
)R
P16R
2(1)
RP1
6R1(1
)R
P16R
0(1)
0000
RP
OR
906
D2
��
�R
P19R
4(1)
RP1
9R3(1
)R
P19R
2(1)
RP1
9R1(1
)R
P19R
0(1)
��
�R
P18R
4(1)
RP1
8R3(1
)R
P18R
2(1)
RP1
8R1(1
)R
P18R
0(1)
0000
RP
OR
1006
D4
��
�R
P21R
4(1)
RP2
1R3(1
)R
P21R
2(1)
RP2
1R1(1
)R
P21R
0(1)
��
�R
P20R
4(1)
RP2
0R3(1
)R
P20R
2(1)
RP2
0R1(1
)R
P20R
0(1)
0000
RP
OR
1106
D6
��
�R
P23R
4(1)
RP2
3R3(1
)R
P23R
2(1)
RP2
3R1(1
)R
P23R
0(1)
��
�R
P22R
4(1)
RP2
2R3(1
)R
P22R
2(1)
RP2
2R1(1
)R
P22R
0(1)
0000
RP
OR
1206
D8
��
�R
P25R
4(1)
RP2
5R3(1
)R
P25R
2(1)
RP2
5R1(1
)R
P25R
0(1)
��
�R
P24R
4(1)
RP2
4R3(1
)R
P24R
2(1)
RP2
4R1(1
)R
P24R
0(1)
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
Not
e1:
Bits
are
onl
y av
aila
ble
on th
e 44
-pin
dev
ices
; oth
erw
ise,
they
read
as
�0�.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 35
PIC24FJ64GA004 FAMILY
TABLE
3-2
2:C
LOC
K C
ON
TRO
L R
EGIS
TER
MA
PFi
le
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
RC
ON
0740
TRAP
RIO
PUW
R�
��
�C
MVR
EGS
EXTR
SWR
SWD
TEN
WD
TOSL
EEP
IDLE
BOR
POR
(Not
e 1)
OSC
CO
N07
42�
CO
SC2
CO
SC1
CO
SC0
�N
OSC
2N
OSC
1N
OSC
0C
LKLO
CK
IOLO
CK
LOC
K�
CF
�SO
SCEN
OSW
EN(N
ote
2)C
LKD
IV07
44R
OI
DO
ZE2
DO
ZE1
DO
ZE0
DO
ZEN
RC
DIV
2R
CD
IV1
RC
DIV
0�
��
��
��
�3140
OSC
TUN
0748
��
��
��
��
��
TUN
5TU
N4
TUN
3TU
N2
TUN
1TU
N0
0000
Lege
nd:
� =
uni
mpl
emen
ted,
read
as
�0�.
Res
et v
alue
s ar
e sh
own
in h
exad
ecim
al.
Not
e1:
RC
ON
regi
ster
Res
et v
alue
s ar
e de
pend
ent o
n ty
pe o
f Res
et.
2:O
SCC
ON
regi
ster
Res
et v
alue
s ar
e de
pend
ent o
n co
nfig
urat
ion
fuse
s an
d by
type
of R
eset
.
TAB
LE 3
-23:
NVM
REG
ISTE
R M
AP
File
Nam
eA
ddr
Bit
15B
it 14
Bit
13B
it 12
Bit
11B
it 10
Bit
9B
it 8
Bit
7B
it 6
Bit
5B
it 4
Bit
3B
it 2
Bit
1B
it 0
All
Res
ets
NVM
CO
N07
60W
RW
RE
NW
RER
R�
��
��
�E
RAS
E�
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it 14
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it 12
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ets
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DS39881C-page 36 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.2.5 SOFTWARE STACKIn addition to its use as a working register, the W15register in PIC24F devices is also used as a SoftwareStack Pointer. The pointer always points to the firstavailable free word and grows from lower to higheraddresses. It pre-decrements for stack pops andpost-increments for stack pushes, as shown inFigure 3-4. Note that for a PC push during any CALLinstruction, the MSB of the PC is zero-extended beforethe push, ensuring that the MSB is always clear.
The Stack Pointer Limit Value register (SPLIM), associ-ated with the Stack Pointer, sets an upper addressboundary for the stack. SPLIM is uninitialized at Reset.As is the case for the Stack Pointer, SPLIM<0> isforced to �0� because all stack operations must beword-aligned. Whenever an EA is generated usingW15 as a source or destination pointer, the resultingaddress is compared with the value in SPLIM. If thecontents of the Stack Pointer (W15) and the SPLIMregister are equal, and a push operation is performed,a stack error trap will not occur. The stack error trap willoccur on a subsequent push operation. Thus, forexample, if it is desirable to cause a stack error trapwhen the stack grows beyond address 2000h in RAM,initialize the SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap isgenerated when the Stack Pointer address is found tobe less than 0800h. This prevents the stack frominterfering with the Special Function Register (SFR)space.
A write to the SPLIM register should not be immediatelyfollowed by an indirect read operation using W15.
FIGURE 3-4: CALL STACK FRAME
3.3 Interfacing Program and Data Memory Spaces
The PIC24F architecture uses a 24-bit wide programspace and 16-bit wide data space. The architecture isalso a modified Harvard scheme, meaning that datacan also be present in the program space. To use thisdata successfully, it must be accessed in a way thatpreserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architectureprovides two methods by which program space can beaccessed during operation:
� Using table instructions to access individual bytes or words anywhere in the program space
� Remapping a portion of the program space into the data space (program space visibility)
Table instructions allow an application to read or writeto small areas of the program memory. This makes themethod ideal for accessing data tables that need to beupdated from time to time. It also allows access to allbytes of the program word. The remapping methodallows an application to access a large block of data ona read-only basis, which is ideal for look ups from alarge table of static data. It can only access the leastsignificant word of the program word.
3.3.1 ADDRESSING PROGRAM SPACESince the address ranges for the data and programspaces are 16 and 24 bits, respectively, a method isneeded to create a 23-bit or 24-bit program addressfrom 16-bit data registers. The solution depends on theinterface method to be used.
For table operations, the 8-bit Table Memory PageAddress register (TBLPAG) is used to define a 32K wordregion within the program space. This is concatenatedwith a 16-bit EA to arrive at a full 24-bit program spaceaddress. In this format, the Most Significant bit ofTBLPAG is used to determine if the operation occurs inthe user memory (TBLPAG<7> = 0) or the configurationmemory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program SpaceVisibility Page Address register (PSVPAG) is used todefine a 16K word page in the program space. Whenthe Most Significant bit of the EA is �1�, PSVPAG is con-catenated with the lower 15 bits of the EA to form a23-bit program space address. Unlike table operations,this limits remapping operations strictly to the usermemory area.
Table 3-25 and Figure 3-5 show how the program EA iscreated for table operations and remapping accessesfrom the data EA. Here, P<23:0> refers to a programspace word, whereas D<15:0> refers to a data spaceword.
Note: A PC push during exception processingwill concatenate the SRL register to theMSB of the PC prior to the push.
<Free Word>
PC<15:0>000000000
015
W15 (before CALL)
W15 (after CALL)
Stac
k G
row
s To
war
dsH
ighe
r Add
ress
0000h
PC<22:16>
POP : [--W15]PUSH : [W15++]
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 37
PIC24FJ64GA004 FAMILY
TABLE 3-25: PROGRAM SPACE ADDRESS CONSTRUCTIONFIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Access Type AccessSpace
Program Space Address<23> <22:16> <15> <14:1> <0>
Instruction Access(Code Execution)
User 0 PC<22:1> 0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT(Byte/Word Read/Write)
User TBLPAG<7:0> Data EA<15:0>0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>1xxx xxxx xxxx xxxx xxxx xxxx
Program Space Visibility(Block Remap/Read)
User 0 PSVPAG<7:0> Data EA<14:0>(1)
0 xxxx xxxx xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always �1� in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>.
0Program Counter
23 Bits
1
PSVPAG
8 Bits
EA
15 Bits
Program Counter(1)
Select
TBLPAG
8 Bits
EA
16 Bits
Byte Select
0
0
1/0
User/Configuration
Table Operations(2)
Program Space Visibility(1)
Space Select
24 Bits
23 Bits
(Remapping)
1/0
0
Note 1: The LSb of program space addresses is always fixed as �0� in order to maintain word alignment ofdata in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in theconfiguration memory space.
DS39881C-page 38 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.3.2 DATA ACCESS FROM PROGRAMMEMORY USING TABLE INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a directmethod of reading or writing the lower word of anyaddress within the program space without going throughdata space. The TBLRDH and TBLWTH instructions arethe only method to read or write the upper 8 bits of aprogram space word as data.
The PC is incremented by two for each successive24-bit program word. This allows program memoryaddresses to directly map to data space addresses.Program memory can thus be regarded as two 16-bitword-wide address spaces, residing side by side, eachwith the same address range. TBLRDL and TBLWTLaccess the space which contains the least significantdata word, and TBLRDH and TBLWTH access the spacewhich contains the upper data byte.
Two table instructions are provided to move byte orword-sized (16-bit) data to and from program space.Both function as either byte or word operations.
1. TBLRDL (Table Read Low): In Word mode, itmaps the lower word of the program spacelocation (P<15:0>) to a data address (D<15:0>).In Byte mode, either the upper or lower byte ofthe lower program word is mapped to the lowerbyte of a data address. The upper byte isselected when byte select is �1�; the lower byteis selected when it is �0�.
2. TBLRDH (Table Read High): In Word mode, itmaps the entire upper word of a program address(P<23:16>) to a data address. Note thatD<15:8>, the �phantom� byte, will always be �0�.In Byte mode, it maps the upper or lower byte ofthe program word to D<7:0> of the dataaddress, as above. Note that the data willalways be �0� when the upper �phantom� byte isselected (byte select = 1).
In a similar fashion, two table instructions, TBLWTHand TBLWTL, are used to write individual bytes orwords to a program space address. The details oftheir operation are explained in Section 4.0 �FlashProgram Memory�.
For all table operations, the area of program memoryspace to be accessed is determined by the TableMemory Page Address register (TBLPAG). TBLPAGcovers the entire program memory space of thedevice, including user and configuration spaces. WhenTBLPAG<7> = 0, the table page is located in the usermemory space. When TBLPAG<7> = 1, the page islocated in configuration space.
FIGURE 3-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Note: Only table read operations will execute inthe configuration memory space, and onlythen, in implemented areas such as theDevice ID. Table write operations are notallowed.
0816230000000000000000
0000000000000000
�Phantom� Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
23 15 0
TBLPAG02
000000h
800000h
020000h
030000h
Program Space
Data EA<15:0>
The address for the table operation is determined by the data EAwithin the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid inthe user memory area.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 39
PIC24FJ64GA004 FAMILY
3.3.3 READING DATA FROM PROGRAMMEMORY USING PROGRAM SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally bemapped into any 16K word page of the program space.This provides transparent access of stored constantdata from the data space without the need to usespecial instructions (i.e., TBLRDL/H).
Program space access through the data space occurs ifthe Most Significant bit of the data space EA is �1�, andprogram space visibility is enabled by setting the PSV bitin the CPU Control register (CORCON<2>). The loca-tion of the program memory space to be mapped into thedata space is determined by the Program Space Visibil-ity Page Address register (PSVPAG). This 8-bit registerdefines any one of 256 possible pages of 16K words inprogram space. In effect, PSVPAG functions as theupper 8 bits of the program memory address, with the15 bits of the EA functioning as the lower bits. Note thatby incrementing the PC by 2 for each program memoryword, the lower 15 bits of data space addresses directlymap to the lower 15 bits in the corresponding programspace addresses.
Data reads to this area add an additional cycle to theinstruction being executed, since two program memoryfetches are required.
Although each data space address, 8000h and higher,maps directly into a corresponding program memoryaddress (see Figure 3-7), only the lower 16 bits of the
24-bit program word are used to contain the data. Theupper 8 bits of any program space locations used asdata should be programmed with �1111 1111� or�0000 0000� to force a NOP. This prevents possibleissues should the area of code ever be accidentallyexecuted.
For operations that use PSV and are executed outsidea REPEAT loop, the MOV and MOV.D instructions willrequire one instruction cycle in addition to the specifiedexecution time. All other instructions will require twoinstruction cycles in addition to the specified executiontime.
For operations that use PSV which are executed insidea REPEAT loop, there will be some instances thatrequire two instruction cycles in addition to thespecified execution time of the instruction:
� Execution in the first iteration� Execution in the last iteration� Execution prior to exiting the loop due to an
interrupt� Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow theinstruction accessing data, using PSV, to execute in asingle cycle.
FIGURE 3-7: PROGRAM SPACE VISIBILITY OPERATION
Note: PSV access is temporarily disabled duringtable reads/writes.
23 15 0PSVPAGData SpaceProgram Space
0000h
8000h
FFFFh
02000000h
800000h
010000h
018000h
When CORCON<2> = 1 and EA<15> = 1:
PSV Area
The data in the page designated by PSVPAG is mapped into the upper half of the data memory space....
Data EA<14:0>
...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.
DS39881C-page 40 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.0 FLASH PROGRAM MEMORY
The PIC24FJ64GA004 family of devices contains inter-nal Flash program memory for storing and executingapplication code. The memory is readable, writable anderasable when operating with VDD over 2.25V.
Flash memory can be programmed in four ways:
� In-Circuit Serial Programming� (ICSP�)� Run-Time Self-Programming (RTSP)� JTAG� Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24FJ64GA004 family device to beserially programmed while in the end application circuit.This is simply done with two lines for the programmingclock and programming data (which are named PGCxand PGDx, respectively), and three other lines forpower (VDD), ground (VSS) and Master Clear (MCLR).This allows customers to manufacture boards withunprogrammed devices and then program the micro-controller just before shipping the product. This alsoallows the most recent firmware or a custom firmwareto be programmed.
RTSP is accomplished using TBLRD (table read) andTBLWT (table write) instructions. With RTSP, the usermay write program memory data in blocks of 64 instruc-tions (192 bytes) at a time, and erase program memoryin blocks of 512 instructions (1536 bytes) at a time.
4.1 Table Instructions and Flash Programming
Regardless of the method used, all programming ofFlash memory is done with the table read and tablewrite instructions. These allow direct read and writeaccess to the program memory space from the datamemory while the device is in normal operating mode.The 24-bit target address in the program memory isformed using the TBLPAG<7:0> bits and the EffectiveAddress (EA) from a W register specified in the tableinstruction, as shown in Figure 4-1.
The TBLRDL and the TBLWTL instructions are used toread or write to bits<15:0> of program memory.TBLRDL and TBLWTL can access program memory inboth Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to reador write to bits<23:16> of program memory. TBLRDHand TBLWTH can also access program memory in Wordor Byte mode.
FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 4. Program Memory�(DS39715).
0Program Counter
24 Bits
Program
TBLPAG Reg
8 Bits
Working Reg EA
16 Bits
Using
Byte24-Bit EA
0
1/0
Select
TableInstruction
Counter
Using
User/ConfigurationSpace Select
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 41
PIC24FJ64GA004 FAMILY
4.2 RTSP OperationThe PIC24F Flash program memory array is organizedinto rows of 64 instructions or 192 bytes. RTSP allowsthe user to erase blocks of eight rows (512 instructions)at a time and to program one row at a time. It is alsopossible to program single words.The 8-row erase blocks and single row write blocks areedge-aligned, from the beginning of program memory, onboundaries of 1536 bytes and 192 bytes, respectively.
When data is written to program memory using TBLWTinstructions, the data is not written directly to memory.Instead, data written using table writes is stored inholding latches until the programming sequence isexecuted.
Any number of TBLWT instructions can be executedand a write will be successfully performed. However,64 TBLWT instructions are required to write the full rowof memory.
To ensure that no data is corrupted during a write, anyunused addresses should be programmed withFFFFFFh. This is because the holding latches reset toan unknown state, so if the addresses are left in theReset state, they may overwrite the locations on rowswhich were not rewritten.
The basic sequence for RTSP programming is to set upa Table Pointer, then do a series of TBLWT instructionsto load the buffers. Programming is performed bysetting the control bits in the NVMCON register.
Data can be loaded in any order and the holding regis-ters can be written to multiple times before performinga write operation. Subsequent writes, however, willwipe out any previous writes.
All of the table write operations are single-word writes(2 instruction cycles), because only the buffers are writ-ten. A programming cycle is required for programmingeach row.
4.3 JTAG OperationThe PIC24F family supports JTAG programming andboundary scan. Boundary scan can improve the manu-facturing process by verifying pin to PCB connectivity.Programming can be performed with industry standardJTAG programmers supporting Serial Vector Format(SVF).
4.4 Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses anon-board bootloader, known as the program executive,to manage the programming process. Using an SPIdata frame format, the program executive can erase,program and verify program memory. For moreinformation on Enhanced ICSP, see the deviceprogramming specification.
4.5 Control RegistersThere are two SFRs used to read and write theprogram Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 4-1) controls whichblocks are to be erased, which memory type is to beprogrammed and when the programming cycle starts.
NVMKEY is a write-only register that is used for writeprotection. To start a programming or erase sequence,the user must consecutively write 55h and AAh to theNVMKEY register. Refer to Section 4.6 �ProgrammingOperations� for further details.
4.6 Programming OperationsA complete programming sequence is necessary forprogramming or erasing the internal Flash in RTSPmode. During a programming or erase operation, theprocessor stalls (waits) until the operation is finished.Setting the WR bit (NVMCON<15>) starts the opera-tion and the WR bit is automatically cleared when theoperation is finished.
Configuration Word values are stored in the last twolocations of program memory. Performing a page eraseoperation on the last page of program memory clearsthese values and enables code protection. As a result,avoid performing page erase operations on the lastpage of program memory.
Note: Writing to a location multiple times withouterasing it is not recommended.
DS39881C-page 42 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0WR WREN WRERR � � � � �
bit 15 bit 8
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0� ERASE � � NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1)
bit 7 bit 0
Legend: SO = Set Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit1 = Enable Flash program/erase operations0 = Inhibit Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)0 = The program or erase operation completed normally
bit 12-7 Unimplemented: Read as �0�bit 6 ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command
bit 5-4 Unimplemented: Read as �0�bit 3-0 NVMOP3:NVMOP0: NVM Operation Select bits(1)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(2) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1: All other combinations of NVMOP3:NVMOP0 are unimplemented.2: Available in ICSP� mode only. Refer to device programming specification.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 43
PIC24FJ64GA004 FAMILY
4.6.1 PROGRAMMING ALGORITHM FORFLASH PROGRAM MEMORYThe user can program one row of Flash program memoryat a time. To do this, it is necessary to erase the 8-rowerase block containing the desired row. The generalprocess is:
1. Read eight rows of program memory(512 instructions) and store in data RAM.
2. Update the program data in RAM with thedesired new data.
3. Erase the block (see Example 4-1):a) Set the NVMOP bits (NVMCON<3:0>) to
�0010� to configure for block erase. Set theERASE (NVMCON<6>) and WREN(NVMCON<14>) bits.
b) Write the starting address of the block to beerased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.d) Write AAh to NVMKEY.e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-tion of the erase cycle. When the erase isdone, the WR bit is cleared automatically.
4. Write the first 64 instructions from data RAM intothe program memory buffers (see Example 4-1).
5. Write the program block to Flash memory:a) Set the NVMOP bits to �0001� to configure
for row programming. Clear the ERASE bitand set the WREN bit.
b) Write 55h to NVMKEY.c) Write AAh to NVMKEY.d) Set the WR bit. The programming cycle
begins and the CPU stalls for the durationof the write cycle. When the write to Flashmemory is done, the WR bit is clearedautomatically.
6. Repeat steps 4 and 5, using the next available64 instructions from the block in data RAM byincrementing the value in TBLPAG, until all512 instructions are written back to Flashmemory.
For protection against accidental operations, the writeinitiate sequence for NVMKEY must be used to allowany erase or program operation to proceed. After theprogramming command has been executed, the usermust wait for the programming time until programmingis complete. The two instructions following the start ofthe programming sequence should be NOPs, as shownin Example 4-3.
EXAMPLE 4-1: ERASING A PROGRAM MEMORY BLOCK ; Set up NVMCON for block erase operation
MOV #0x4042, W0 ;MOV W0, NVMCON ; Initialize NVMCON
; Init pointer to row to be ERASEDMOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFRMOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointerTBLWTL W0, [W0] ; Set base address of erase blockDISI #5 ; Block all interrupts with priority <7
; for next 5 instructionsMOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ;MOV W1, NVMKEY ; Write the AA keyBSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the eraseNOP ; command is asserted
DS39881C-page 44 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
EXAMPLE 4-2: LOADING THE WRITE BUFFERSEXAMPLE 4-3: INITIATING A PROGRAMMING SEQUENCE
; Set up NVMCON for row programming operationsMOV #0x4001, W0 ;MOV W0, NVMCON ; Initialize NVMCON
; Set up a pointer to the first program memory location to be written; program memory selected, and writes enabled
MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFRMOV #0x6000, W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches; 0th_program_word
MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch
; 1st_program_wordMOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch
; 2nd_program_wordMOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch���
; 63rd_program_wordMOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0] ; Write PM high byte into program latch
DISI #5 ; Block all interrupts with priority <7; for next 5 instructions
MOV #0x55, W0MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ;MOV W1, NVMKEY ; Write the AA keyBSET NVMCON, #WR ; Start the erase sequence NOP ; 2 NOPs required after setting WRNOP ;BTSC NVMCON, #15 ; Wait for the sequence to be completedBRA $-2 ;
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 45
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4.6.2 PROGRAMMING A SINGLE WORDOF FLASH PROGRAM MEMORYIf a Flash location has been erased, it can be pro-grammed using table write instructions to write aninstruction word (24-bit) into the write latch. TheTBLPAG register is loaded with the 8 Most SignificantBytes of the Flash address. The TBLWTL and TBLWTH
instructions write the desired data into the write latchesand specify the lower 16 bits of the program memoryaddress to write to. To configure the NVMCON registerfor a word write, set the NVMOP bits (NVMCON<3:0>)to �0011�. The write is performed by executing theunlock sequence and setting the WR bit (seeExample 4-4).
EXAMPLE 4-4: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY; Setup a pointer to data Program Memory
MOV #tblpage(PROG_ADDR), W0 ;MOV W0, TBLPAG ;Initialize PM Page Boundary SFRMOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address
MOV #LOW_WORD_N, W2 ;MOV #HIGH_BYTE_N, W3 ;TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch
; Setup NVMCON for programming one word to data Program MemoryMOV #0x4003, W0 ;MOV W0, NVMCON ; Set NVMOP bits to 0011
DISI #5 ; Disable interrupts while the KEY sequence is writtenMOV #0x55, W0 ; Write the key sequenceMOV W0, NVMKEYMOV #0xAA, W0MOV W0, NVMKEYBSET NVMCON, #WR ; Start the write cycleNOP ; 2 NOPs required after setting WRNOP ;
DS39881C-page 46 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
5.0 RESETS
The Reset module combines all Reset sources andcontrols the device Master Reset Signal, SYSRST. Thefollowing is a list of device Reset sources:
� POR: Power-on Reset � MCLR: Pin Reset� SWR: RESET Instruction� WDT: Watchdog Timer Reset� BOR: Brown-out Reset� CM: Configuration Mismatch Reset� TRAPR: Trap Conflict Reset� IOPUWR: Illegal Opcode Reset� UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module isshown in Figure 5-1.
Any active source of Reset will make the SYSRSTsignal active. Many registers associated with the CPUand peripherals are forced to a known Reset state.Most registers are unaffected by a Reset; their status isunknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding statusbit in the RCON register to indicate the type of Reset(see Register 5-1). A Power-on Reset will clear all bitsexcept for the BOR and POR bits (RCON<1:0>) whichare set. The user may set or clear any bit at any timeduring code execution. The RCON bits only serve asstatus bits. Setting a particular Reset status bit insoftware will not cause a device Reset to occur.
The RCON register also has other bits associated withthe Watchdog Timer and device power-saving states.The function of these bits is discussed in other sectionsof this manual.
FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 7. Reset� (DS39712).
Note: Refer to the specific peripheral or CPUsection of this manual for register Resetstates.
Note: The status bits in the RCON registershould be cleared after they are read sothat the next RCON register value after adevice Reset will be meaningful.
MCLR
VDD
VDD RiseDetect
POR
Sleep or Idle
Brown-outReset
Enable Voltage Regulator
RESETInstruction
WDTModule
Glitch Filter
BOR
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
Configuration Mismatch
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 47
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REGISTER 5-1: RCON: RESET CONTROL REGISTER(1)R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0TRAPR IOPUWR � � � � CM VREGS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit1 = A Trap Conflict Reset has occurred0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10 Unimplemented: Read as �0�bit 9 CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred0 = A Configuration Word Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby Enable bit1 = Regulator remains active during Sleep0 = Regulator goes to standby during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit1 = A Master Clear (pin) Reset has occurred0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit1 = A RESET instruction has been executed0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit1 = WDT time-out has occurred0 = WDT time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit1 = Device has been in Sleep mode0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up From Idle Flag bit1 = Device has been in Idle mode0 = Device has not been in Idle mode
bit 1 BOR: Brown-out Reset Flag bit1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset.0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit1 = A Power-up Reset has occurred0 = A Power-up Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
2: If the FWDTEN Configuration bit is �1� (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
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TABLE 5-1: RESET FLAG BIT OPERATION5.1 Clock Source Selection at ResetIf clock switching is enabled, the system clock source atdevice Reset is chosen as shown in Table 5-2. If clockswitching is disabled, the system clock source is alwaysselected according to the oscillator Configuration bits.Refer to Section 7.0 �Oscillator Configuration� forfurther details.
TABLE 5-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED)
5.2 Device Reset TimesThe Reset times for various types of device Reset aresummarized in Table 5-3. Note that the system Resetsignal, SYSRST, is released after the POR and PWRTdelay times expire.
The time that the device actually begins to executecode will also depend on the system oscillator delays,which include the Oscillator Start-up Timer (OST) andthe PLL lock time. The OST and PLL lock times occurin parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which theFSCM begins to monitor the system clock source afterthe SYSRST signal is released.
Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap Conflict Event PORIOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR
CM (RCON<9>) Configuration Mismatch Reset POR
EXTR (RCON<7>) MCLR Reset PORSWR (RCON<6>) RESET Instruction PORWDTO (RCON<4>) WDT Time-out PWRSAV Instruction, PORSLEEP (RCON<3>) PWRSAV #SLEEP Instruction PORIDLE (RCON<2>) PWRSAV #IDLE Instruction PORBOR (RCON<1>) POR, BOR �POR (RCON<0>) POR �Note: All Reset flag bits may be set or cleared by the user software.
Reset Type Clock Source Determinant
POR FNOS Configuration bits(CW2<10:8>)BOR
MCLR COSC Control bits (OSCCON<14:12>)WDTO
SWR
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TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETSReset Type Clock Source SYSRST Delay System ClockDelay
FSCMDelay Notes
POR EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST � � 1, 2, 3ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6
BOR EC, FRC, FRCDIV, LPRC TSTARTUP + TRST � � 2, 3ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 2, 3, 5, 6XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 2, 3, 4, 6XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 2, 3, 4, 5, 6
MCLR Any Clock TRST � � 3WDT Any Clock TRST � � 3Software Any clock TRST � � 3Illegal Opcode Any Clock TRST � � 3Uninitialized W Any Clock TRST � � 3Trap Conflict Any Clock TRST � � 3Note 1: TPOR = Power-on Reset delay (10 μs nominal).
2: TSTARTUP = TVREG (10 μs nominal) if on-chip regulator is enabled or TPWRT (64 ms nominal) if on-chip regulator is disabled.
3: TRST = Internal state Reset time.4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.5: TLOCK = PLL lock time (2 ms nominal).6: TFSCM = Fail-Safe Clock Monitor delay.
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5.2.1 POR AND LONG OSCILLATORSTART-UP TIMESThe oscillator start-up circuitry and its associated delaytimers are not linked to the device Reset delays thatoccur at power-up. Some crystal circuits (especiallylow-frequency crystals) will have a relatively longstart-up time. Therefore, one or more of the followingconditions is possible after SYSRST is released:
� The oscillator circuit has not begun to oscillate.� The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).� The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a validclock source has been released to the system. There-fore, the oscillator and PLL start-up delays must beconsidered when the Reset delay time must be known.
5.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor thesystem clock source when SYSRST is released. If avalid clock source is not available at this time, thedevice will automatically switch to the FRC oscillatorand the user can switch to the desired crystal oscillatorin the Trap Service Routine.
5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources
When the system clock source is provided by a crystaloscillator and/or the PLL, a small delay, TFSCM, willautomatically be inserted after the POR and PWRTdelay times. The FSCM will not begin to monitor thesystem clock source until this delay expires. The FSCMdelay time is nominally 100 μs and provides additionaltime for the oscillator and/or PLL to stabilize. In mostcases, the FSCM delay will prevent an oscillator failuretrap at a device Reset when the PWRT is disabled.
5.3 Special Function Register Reset States
Most of the Special Function Registers (SFRs) associ-ated with the PIC24F CPU and peripherals are reset to aparticular value at a device Reset. The SFRs aregrouped by their peripheral or CPU function and theirReset values are specified in each section of this manual.
The Reset value for each SFR does not depend on thetype of Reset, with the exception of four registers. TheReset value for the Reset Control register, RCON, willdepend on the type of device Reset. The Reset valuefor the Oscillator Control register, OSCCON, willdepend on the type of Reset and the programmedvalues of the FNOSC bits in the CW2 register (seeTable 5-2). The RCFGCAL and NVMCON registers areonly affected by a POR.
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NOTES:DS39881C-page 52 Preliminary © 2008 Microchip Technology Inc.
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6.0 INTERRUPT CONTROLLER
The PIC24F interrupt controller reduces the numerousperipheral interrupt request signals to a single interruptrequest signal to the PIC24F CPU. It has the followingfeatures:
� Up to 8 processor exceptions and software traps� 7 user-selectable priority levels� Interrupt Vector Table (IVT) with up to 118 vectors� A unique vector for each interrupt or exception
source� Fixed priority within a specified user priority level� Alternate Interrupt Vector Table (AIVT) for debug
support� Fixed interrupt entry and return latencies
6.1 Interrupt Vector TableThe Interrupt Vector Table (IVT) is shown in Figure 6-1.The IVT resides in program memory, starting at location000004h. The IVT contains 126 vectors, consisting of8 non-maskable trap vectors, plus up to 118 sources ofinterrupt. In general, each interrupt source has its ownvector. Each interrupt vector contains a 24-bit wideaddress. The value programmed into each interruptvector location is the starting address of the associatedInterrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their naturalpriority; this is linked to their position in the vector table.All other things being equal, lower addresses have ahigher natural priority. For example, the interrupt asso-ciated with vector 0 will take priority over interrupts atany other vector address.
PIC24FJ64GA004 family devices implementnon-maskable traps and unique interrupts. These aresummarized in Table 6-1 and Table 6-2.
6.1.1 ALTERNATE INTERRUPT VECTOR TABLE
The Alternate Interrupt Vector Table (AIVT) is locatedafter the IVT, as shown in Figure 6-1. Access to theAIVT is provided by the ALTIVT control bit(INTCON2<15>). If the ALTIVT bit is set, all interruptand exception processes will use the alternate vectorsinstead of the default vectors. The alternate vectors areorganized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts byproviding a means to switch between an applicationand a support environment without requiring the inter-rupt vectors to be reprogrammed. This feature alsoenables switching between applications for evaluationof different software algorithms at run time. If the AIVTis not needed, the AIVT should be programmed withthe same addresses used in the IVT.
6.2 Reset SequenceA device Reset is not a true exception because theinterrupt controller is not involved in the Reset process.The PIC24F devices clear their registers in response toa Reset which forces the PC to zero. The micro-controller then begins program execution at location000000h. The user programs a GOTO instruction at theReset address, which redirects program execution tothe appropriate start-up routine.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 8. Interrupts� (DS39707).
Note: Any unimplemented or unused vectorlocations in the IVT and AIVT should beprogrammed with the address of a defaultinterrupt handler routine that contains aRESET instruction.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 53
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FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLETABLE 6-1: TRAP VECTOR DETAILSVector Number IVT Address AIVT Address Trap Source
0 000004h 000104h Reserved1 000006h 000106h Oscillator Failure2 000008h 000108h Address Error3 00000Ah 00010Ah Stack Error4 00000Ch 00010Ch Math Error5 00000Eh 00010Eh Reserved6 000010h 000110h Reserved7 000012h 0001172h Reserved
Reset � GOTO Instruction 000000hReset � GOTO Address 000002h
Reserved 000004hOscillator Fail Trap VectorAddress Error Trap Vector
Stack Error Trap VectorMath Error Trap Vector
ReservedReservedReserved
Interrupt Vector 0 000014hInterrupt Vector 1
���
Interrupt Vector 52 00007ChInterrupt Vector 53 00007EhInterrupt Vector 54 000080h
���
Interrupt Vector 116 0000FChInterrupt Vector 117 0000FEh
Reserved 000100hReserved 000102hReserved
Oscillator Fail Trap VectorAddress Error Trap Vector
Stack Error Trap VectorMath Error Trap Vector
ReservedReservedReserved
Interrupt Vector 0 000114hInterrupt Vector 1
���
Interrupt Vector 52 00017ChInterrupt Vector 53 00017EhInterrupt Vector 54 000180h
���
Interrupt Vector 116Interrupt Vector 117 0001FEh
Start of Code 000200h
Dec
reas
ing
Nat
ural
Ord
er P
riorit
y Interrupt Vector Table (IVT)(1)
Alternate Interrupt Vector Table (AIVT)(1)
Note 1: See Table 6-2 for the interrupt vector list.
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORSInterrupt Source Vector Number IVT Address AIVT
AddressInterrupt Bit Locations
Flag Enable Priority
ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4>Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8>CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12>External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0>External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0>External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4>I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4>I2C1 Slave Event 16 000034h 000034h IFS1<0> IEC1<0> IPC4<2:0>I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8>I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4>Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4>Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4>Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4>Input Capture 4 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8>Input Capture 5 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12>Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12>Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8>Output Compare 2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8>Output Compare 3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4>Output Compare 4 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8>Output Compare 5 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4>Parallel Master Port 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4>Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<13> IPC15<10:8>SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4>SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8>SPI2 Error 32 000054h 000154h IFS2<0> IEC0<0> IPC8<2:0>SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4>Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12>Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12>Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0>Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12>Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0>UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4>UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12>UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0>UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8>UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8>UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>LVD Low-Voltage Detect 72 0000A4h 000124h IFS4<8> IEC4<8> IPC17<2:0>
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6.3 Interrupt Control and StatusRegistersThe PIC24FJ64GA004 family of devices implements atotal of 28 registers for the interrupt controller:
� INTCON1 � INTCON2 � IFS0 through IFS4� IEC0 through IEC4� IPC0 through IPC12, IPC15, IPC16 and IPC18
Global interrupt control functions are controlled fromINTCON1 and INTCON2. INTCON1 contains the Inter-rupt Nesting Disable (NSTDIS) bit, as well as thecontrol and status flags for the processor trap sources.The INTCON2 register controls the external interruptrequest signal behavior and the use of the AlternateInterrupt Vector Table.
The IFSx registers maintain all of the interrupt requestflags. Each source of interrupt has a status bit which isset by the respective peripherals, or external signal,and is cleared via software.
The IECx registers maintain all of the interrupt enablebits. These control bits are used to individually enableinterrupts from the peripherals or external signals.
The IPCx registers are used to set the interrupt prioritylevel for each source of interrupt. Each user interruptsource can be assigned to one of eight priority levels.
The interrupt sources are assigned to the IFSx, IECxand IPCx registers in the same sequence that they arelisted in Table 6-2. For example, the INT0 (ExternalInterrupt 0) is shown as having a vector number and anatural order priority of 0. Thus, the INT0IF status bit isfound in IFS0<0>, the INT0IE enable bit in IEC0<0>and the INT0IP<2:0> priority bits in the first position ofIPC0 (IPC0<2:0>).
Although they are not specifically part of the interruptcontrol hardware, two of the CPU control registers con-tain bits that control interrupt functionality. The ALUSTATUS register (SR) contains the IPL2:IPL0 bits(SR<7:5>). These indicate the current CPU interruptpriority level. The user may change the current CPUpriority level by writing to the IPL bits.
The CORCON register contains the IPL3 bit, whichtogether with IPL2:IPL0, also indicates the current CPUpriority level. IPL3 is a read-only bit so that trap eventscannot be masked by the user software.
All interrupt registers are described in Register 6-1through Register 6-29, in the following pages.
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REGISTER 6-1: SR: ALU STATUS REGISTER (IN CPU)U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0� � � � � � � DC(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU interrupt priority level is 7 (15). User interrupts disabled.110 = CPU interrupt priority level is 6 (14)101 = CPU interrupt priority level is 5 (13)100 = CPU interrupt priority level is 4 (12)011 = CPU interrupt priority level is 3 (11)010 = CPU interrupt priority level is 2 (10)001 = CPU interrupt priority level is 1 (9)000 = CPU interrupt priority level is 0 (8)
Note 1: See Register 2-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.
2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 6-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0� � � � IPL3(2) PSV(1) � �
bit 7 bit 0
Legend: C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 3 IPL3: CPU Interrupt Priority Level Status bit(2)
1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or less
Note 1: See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.
2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level.
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REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0NSTDIS � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0� � � MATHERR ADDRERR STKERR OSCFAIL �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit1 = Interrupt nesting is disabled0 = Interrupt nesting is enabled
bit 14-5 Unimplemented: Read as �0� bit 4 MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred0 = Overflow trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit1 = Address error trap has occurred0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit1 = Stack error trap has occurred0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit1 = Oscillator failure trap has occurred0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as �0�
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REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0ALTIVT DISI � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0� � � � � INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit1 = Use Alternate Interrupt Vector Table0 = Use standard (default) vector table
bit 14 DISI: DISI Instruction Status bit1 = DISI instruction is active0 = DISI instruction is not active
bit 13-3 Unimplemented: Read as �0� bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge 0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit1 = Interrupt on negative edge 0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit1 = Interrupt on negative edge 0 = Interrupt on positive edge
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REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0T2IF OC2IF IC2IF � T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0� bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 8 T3IF: Timer3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 7 T2IF: Timer2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 4 Unimplemented: Read as �0� bit 3 T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 0 INT0IF: External Interrupt 0 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
DS39881C-page 60 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF �
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � INT1IF CNIF CMIF MI2C1IF SI2C1IF
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 13 INT2IF: External Interrupt 2 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 12 T5IF: Timer5 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 11 T4IF: Timer4 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 8-5 Unimplemented: Read as �0� bit 4 INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 2 CMIF: Comparator Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 61
PIC24FJ64GA004 FAMILY
REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0� � PMPIF � � � OC5IF �
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0IC5IF IC4IF IC3IF � � � SPI2IF SPF2IF
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0� bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 12-10 Unimplemented: Read as �0� bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 8 Unimplemented: Read as �0� bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 4-2 Unimplemented: Read as �0� bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 0 SPI2IF: SPI2 Fault Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
DS39881C-page 62 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0� RTCIF � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0� � � � � MI2C2IF SI2C2IF �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0� bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 13-3 Unimplemented: Read as �0� bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 0 Unimplemented: Read as �0�
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 63
PIC24FJ64GA004 FAMILY
REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0� � � � � � � LVDIF
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0� � � � CRCIF U2ERIF U1ERIF �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as �0� bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 7-4 Unimplemented: Read as �0� bit 3 CRCIF: CRC Generator Interrupt Flag Status bit
1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred
bit 0 Unimplemented: Read as �0�
DS39881C-page 64 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 65
REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0T2IE OC2IE IC2IE � T1IE OC1IE IC1IE INT0IE(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0� bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 8 T3IE: Timer3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 7 T2IE: Timer2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 4 Unimplemented: Read as �0� bit 3 T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 0 INT0IE: External Interrupt 0 Enable bit(1)
1 = Interrupt request enabled0 = Interrupt request not enabled
Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
PIC24FJ64GA004 FAMILY
REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0U2TXIE U2RXIE INT2IE(1) T5IE T4IE OC4IE OC3IE �
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � INT1IE(1) CNIE CMIE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 13 INT2IE: External Interrupt 2 Enable bit(1)
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 12 T5IE: Timer5 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 11 T4IE: Timer4 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 8-5 Unimplemented: Read as �0� bit 4 INT1IE: External Interrupt 1 Enable bit(1)
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 3 CNIE: Input Change Notification Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 2 CMIE: Comparator Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
DS39881C-page 66 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0� � PMPIE � � � OC5IE �
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0IC5IE IC4IE IC3IE � � � SPI2IE SPF2IE
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0�bit 13 PMPIE: Parallel Master Port Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 12-10 Unimplemented: Read as �0�bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 8 Unimplemented: Read as �0�bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 4-2 Unimplemented: Read as �0� bit 1 SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 67
PIC24FJ64GA004 FAMILY
REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0� RTCIE � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0� � � � � MI2C2IE SI2C2IE �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 13-3 Unimplemented: Read as �0�bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 0 Unimplemented: Read as �0�
DS39881C-page 68 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0� � � � � � � LVDIE
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0� � � � CRCIE U2ERIE U1ERIE �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as �0�bit 8 LVDIE: Low-Voltage Detect Interrupt Enable Status bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 7-4 Unimplemented: Read as �0�bit 3 CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request enabled0 = Interrupt request not enabled
bit 2 U2ERIE: UART2 Error Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 1 U1ERIE: UART1 Error Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled
bit 0 Unimplemented: Read as �0�
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 69
PIC24FJ64GA004 FAMILY
REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� T1IP2 T1IP1 T1IP0 � OC1IP2 OC1IP1 OC1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� IC1IP2 IC1IP1 IC1IP0 � INT0IP2 INT0IP1 INT0IP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 T1IP2:T1IP0: Timer1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3 Unimplemented: Read as �0� bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
DS39881C-page 70 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� T2IP2 T2IP1 T2IP0 � OC2IP2 OC2IP1 OC2IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� IC2IP2 IC2IP1 IC2IP0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 T2IP2:T2IP0: Timer2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 71
PIC24FJ64GA004 FAMILY
REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� U1RXIP2 U1RXIP1 U1RXIP0 � SPI1IP2 SPI1IP1 SPI1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� SPF1IP2 SPF1IP1 SPF1IP0 � T3IP2 T3IP1 T3IP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3 Unimplemented: Read as �0� bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
DS39881C-page 72 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� AD1IP2 AD1IP1 AD1IP0 � U1TXIP2 U1TXIP1 U1TXIP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as �0�bit 6-4 AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3 Unimplemented: Read as �0�bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 73
PIC24FJ64GA004 FAMILY
REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� CNIP2 CNIP1 CNIP0 � CMIP2 CMIP1 CMIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� MI2C1P2 MI2C1P1 MI2C1P0 � SI2C1P2 SI2C1P1 SI2C1P0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 CNIP2:CNIP0: Input Change Notification Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 CMIP2:CMIP0: Comparator Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3 Unimplemented: Read as �0� bit 2-0 SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
DS39881C-page 74 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0� � � � � INT1IP2 INT1IP1 INT1IP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as �0�bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 75
PIC24FJ64GA004 FAMILY
REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� T4IP2 T4IP1 T4IP0 � OC4IP2 OC4IP1 OC4IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� OC3IP2 OC3IP1 OC3IP0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 T4IP2:T4IP0: Timer4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
DS39881C-page 76 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� U2TXIP2 U2TXIP1 U2TXIP0 � U2RXIP2 U2RXIP1 U2RXIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� INT2IP2 INT2IP1 INT2IP0 � T5IP2 T5IP1 T5IP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 INT2IP2:INT2IP0: External Interrupt 2 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3 Unimplemented: Read as �0� bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 77
PIC24FJ64GA004 FAMILY
REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� SPI2IP2 SPI2IP1 SPI2IP0 � SPF2IP2 SPF2IP1 SPF2IP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as �0�bit 6-4 SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3 Unimplemented: Read as �0�bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
DS39881C-page 78 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 6-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� IC5IP2 IC5IP1 IC5IP0 � IC4IP2 IC4IP1 IC4IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� IC3IP2 IC3IP1 IC3IP0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
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REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� OC5IP2 OC5IP1 OC5IP0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as �0�bit 6-4 OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
REGISTER 6-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� PMPIP2 PMPIP1 PMPIP0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as �0�bit 6-4 PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
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REGISTER 6-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0� � � � � MI2C2P2 MI2C2P1 MI2C2P0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� SI2C2P2 SI2C2P1 SI2C2P0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as �0�bit 10-8 MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
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REGISTER 6-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0� � � � � RTCIP2 RTCIP1 RTCIP0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as �0�bit 10-8 RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7-0 Unimplemented: Read as �0�
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REGISTER 6-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0� CRCIP2 CRCIP1 CRCIP0 � U2ERIP2 U2ERIP1 U2ERIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0� U1ERIP2 U1ERIP1 U1ERIP0 � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 11 Unimplemented: Read as �0�bit 10-8 U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 7 Unimplemented: Read as �0�bit 6-4 U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as �0�
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REGISTER 6-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0� � � � � LVDIP2 LVDIP1 LVDIP0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as �0�bit 2-0 LVDIP2:LVDIP0: Low-Voltage Detect Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)���001 = Interrupt is priority 1000 = Interrupt source is disabled
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6.4 Interrupt Setup Procedures6.4.1 INITIALIZATIONTo configure an interrupt source:
1. Set the NSTDIS Control bit (INTCON1<15>) ifnested interrupts are not desired.
2. Select the user-assigned priority level for theinterrupt source by writing the control bits in theappropriate IPCx register. The priority level willdepend on the specific application and type ofinterrupt source. If multiple priority levels are notdesired, the IPCx register control bits for allenabled interrupt sources may be programmedto the same non-zero value.
3. Clear the interrupt flag status bit associated withthe peripheral in the associated IFSx register.
4. Enable the interrupt source by setting theinterrupt enable control bit associated with thesource in the appropriate IECx register.
6.4.2 INTERRUPT SERVICE ROUTINEThe method that is used to declare an ISR and initializethe IVT with the correct vector address will depend onthe programming language (i.e., �C� or assembler) andthe language development toolsuite that is used todevelop the application. In general, the user must clearthe interrupt flag in the appropriate IFSx register for thesource of the interrupt that the ISR handles. Otherwise,the ISR will be re-entered immediately after exiting theroutine. If the ISR is coded in assembly language, itmust be terminated using a RETFIE instruction tounstack the saved PC value, SRL value and old CPUpriority level.
6.4.3 TRAP SERVICE ROUTINEA Trap Service Routine (TSR) is coded like an ISR,except that the appropriate trap status flag in theINTCON1 register must be cleared to avoid re-entryinto the TSR.
6.4.4 INTERRUPT DISABLEAll user interrupts can be disabled using the followingprocedure:
1. Push the current SR value onto the softwarestack using the PUSH instruction.
2. Force the CPU to priority level 7 by inclusiveORing the value OEh with SRL.
To enable user interrupts, the POP instruction may beused to restore the previous SR value.
Note that only user interrupts with a priority level of 7 orless can be disabled. Trap sources (level 8-15) cannotbe disabled.
The DISI instruction provides a convenient way todisable interrupts of priority levels 1-6 for a fixed periodof time. Level 7 interrupt sources are not disabled bythe DISI instruction.
Note: At a device Reset, the IPCx registers areinitialized, such that all user interruptsources are assigned to priority level 4.
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NOTES:DS39881C-page 86 Preliminary © 2008 Microchip Technology Inc.
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7.0 OSCILLATOR CONFIGURATION
The oscillator system for PIC24FJ64GA004 familydevices has the following features:
� A total of four external and internal oscillator options as clock sources, providing 11 different clock modes
� On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources
� Software-controllable switching between various clock sources
� Software-controllable postscaler for selective clocking of CPU for system power savings
� A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown
A simplified diagram of the oscillator system is shownin Figure 7-1.
FIGURE 7-1: PIC24FJ64GA004 FAMILY CLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 6. Oscillator� (DS39700).
PIC24FJ64GA004 Family
Secondary Oscillator
SOSCENEnableOscillator
SOSCO
SOSCI
Clock Source Option for Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
CPU
Peripherals
Pos
tsca
ler
CLKDIV<10:8>
WDT, PWRT
8 MHzFRCDIV
31 kHz (nominal)
FRCOscillator
LPRCOscillator
SOSC
LPRC
Pos
tsca
ler
Clock Control LogicFail-Safe
ClockMonitor
CLKDIV<14:12>
FRC
CLKO
(nominal)
4 x PLL
XTPLL, HSPLLECPLL,FRCPLL
8 MHz4 MHz
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7.1 CPU Clocking SchemeThe system clock source can be provided by one offour sources:� Primary Oscillator (POSC) on the OSCI and OSCO pins
� Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins
� Fast Internal RC (FRC) Oscillator� Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have theoption of using the internal 4x PLL. The frequency ofthe FRC clock source can optionally be reduced by theprogrammable clock divider. The selected clock sourcegenerates the processor and peripheral clock sources.
The processor clock source is divided by two to pro-duce the internal instruction cycle clock, FCY. In thisdocument, the instruction cycle clock is also denotedby FOSC/2. The internal instruction cycle clock, FOSC/2,can be provided on the OSCO I/O pin for someoperating modes of the primary oscillator.
7.2 Initial Configuration on PORThe oscillator source (and operating mode) that isused at a device Power-on Reset event is selectedusing Configuration bit settings. The oscillator Config-uration bit settings are located in the Configurationregisters in the program memory (refer toSection 23.1 �Configuration Bits� for furtherdetails). The Primary Oscillator Configuration bits,POSCMD1:POSCMD0 (Configuration Word 2<1:0>),and the Initial Oscillator Select Configuration bits,FNOSC2:FNOSC0 (Configuration Word 2<10:8>),select the oscillator source that is used at a Power-onReset. The FRC primary oscillator with postscaler(FRCDIV) is the default (unprogrammed) selection.The secondary oscillator, or one of the internaloscillators, may be chosen by programming these bitlocations.
The Configuration bits allow users to choose betweenthe various clock modes, shown in Table 7-1.
7.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS
The FCKSM Configuration bits (ConfigurationWord 2<7:6>) are used to jointly configure device clockswitching and the Fail-Safe Clock Monitor (FSCM).Clock switching is enabled only when FCKSM1 isprogrammed (�0�). The FSCM is enabled only whenFCKSM1:FCKSM0 are both programmed (�00�).
TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source POSCMD1:POSCMD0
FNOSC2:FNOSC0 Note
Fast RC Oscillator with Postscaler (FRCDIV)
Internal 11 111 1, 2
(Reserved) Internal xx 110 1Low-Power RC Oscillator (LPRC) Internal 11 101 1Secondary (Timer1) Oscillator (SOSC)
Secondary 00 100 1
Primary Oscillator (XT) with PLL Module (XTPLL)
Primary 01 011
Primary Oscillator (EC) with PLL Module (ECPLL)
Primary 00 011
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010
Fast RC Oscillator with PLL Module (FRCPLL)
Internal 11 001 1
Fast RC Oscillator (FRC) Internal 11 000 1Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
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7.3 Control RegistersThe operation of the oscillator is controlled by threeSpecial Function Registers:
� OSCCON� CLKDIV� OSCTUN
The OSCCON register (Register 7-1) is the main con-trol register for the oscillator. It controls clock sourceswitching and allows the monitoring of clock sources.
The Clock Divider register (Register 7-2) controls thefeatures associated with Doze mode, as well as thepostscaler for the FRC oscillator.
The FRC Oscillator Tune register (Register 7-3) allowsthe user to fine tune the FRC oscillator over a range ofapproximately ±12%. Each bit increment or decrementchanges the factory calibrated frequency of the FRCoscillator by a fixed amount.
REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1)
� COSC2 COSC1 COSC0 � NOSC2 NOSC1 NOSC0bit 15 bit 8
R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 U-0 R/W-0 R/W-0CLKLOCK IOLOCK(2) LOCK � CF � SOSCEN OSWEN
bit 7 bit 0
Legend: CO = Clear Only bit SO = Set Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 COSC2:COSC0: Current Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)000 = Fast RC Oscillator (FRC)
bit 11 Unimplemented: Read as �0�bit 10-8 NOSC2:NOSC0: New Oscillator Selection bits(1)
111 = Fast RC Oscillator with Postscaler (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)000 = Fast RC Oscillator (FRC)
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is �1� once the IOLOCK bit is set, it cannot be cleared.3: Also resets to �0� during any valid clock switch or whenever a non-PLL Clock mode is selected.
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bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1):1 = Clock and PLL selections are locked0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bitIf FSCM is disabled (FCKSM1 = 0):Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6 IOLOCK: I/O Lock Enable bit(2)
1 = I/O lock is active0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 Unimplemented: Read as �0�bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure0 = No clock failure has been detected
bit 2 Unimplemented: Read as �0�bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable secondary oscillator0 = Disable secondary oscillator
bit 0 OSWEN: Oscillator Switch Enable bit1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits0 = Oscillator switch is complete
REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is �1� once the IOLOCK bit is set, it cannot be cleared.3: Also resets to �0� during any valid clock switch or whenever a non-PLL Clock mode is selected.
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REGISTER 7-2: CLKDIV: CLOCK DIVIDER REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0
bit 15 bit 8
U-0 U-1 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:10 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits 111 = 1:128110 = 1:64101 = 1:32100 = 1:16011 = 1:8010 = 1:4001 = 1:2000 = 1:1
bit 11 DOZEN: DOZE Enable bit(1)
1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio0 = CPU peripheral clock ratio set to 1:1
bit 10-8 RCDIV2:RCDIV0: FRC Postscaler Select bits111 = 31.25 kHz (divide by 256)110 = 125 kHz (divide by 64)101 = 250 kHz (divide by 32)100 = 500 kHz (divide by 16)011 = 1 MHz (divide by 8)010 = 2 MHz (divide by 4)001 = 4 MHz (divide by 2)000 = 8 MHz (divide by 1)
bit 7 Unimplemented: Read as �0�bit 6 Unimplemented: Read as �1�bit 5-0 Unimplemented: Read as �0�
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 91
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7.4 Clock Switching OperationWith few limitations, applications are free to switchbetween any of the four clock sources (POSC, SOSC,FRC and LPRC) under software control and at anytime. To limit the possible side effects that could resultfrom this flexibility, PIC24F devices have a safeguardlock built into the switching process.
7.4.1 ENABLING CLOCK SWITCHINGTo enable clock switching, the FCKSM1 Configurationbit in Flash Configuration Word 2 must be programmedto �0�. (Refer to Section 23.1 �Configuration Bits� forfurther details.) If the FCKSM1 Configuration bit isunprogrammed (�1�), the clock switching function andFail-Safe Clock Monitor function are disabled. This isthe default setting.
The NOSCx control bits (OSCCON<10:8>) do notcontrol the clock selection when clock switching is dis-abled. However, the COSCx bits (OSCCON<14:12>)will reflect the clock source selected by the FNOSCxConfiguration bits.
The OSWEN control bit (OSCCON<0>) has no effectwhen clock switching is disabled. It is held at �0� at alltimes.
REGISTER 7-3: OSCTUN: FRC Oscillator Tune Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as �0�bit 5-0 TUN5:TUN0: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation011110 = • • • 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency111111 = • • • 100001 = 100000 = Minimum frequency deviation
Note 1: Increments or decrements of TUN5:TUN0 may not change the FRC frequency in equal steps over the FRC tuning range, and may not be monotonic.
Note: The primary oscillator mode has threedifferent submodes (XT, HS and EC)which are determined by the POSCMDxConfiguration bits. While an applicationcan switch to and from primary oscillatormode in software, it cannot switchbetween the different primary submodeswithout reprogramming the device.
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7.4.2 OSCILLATOR SWITCHINGSEQUENCEAt a minimum, performing a clock switch requires thisbasic sequence:
1. If desired, read the COSCx bits(OSCCON<14:12>), to determine the currentoscillator source.
2. Perform the unlock sequence to allow a write tothe OSCCON register high byte.
3. Write the appropriate value to the NOSCx bits(OSCCON<10:8>) for the new oscillator source.
4. Perform the unlock sequence to allow a write tothe OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillatorswitch.
Once the basic sequence is completed, the systemclock hardware responds automatically as follows:
1. The clock switching hardware compares theCOSCx bits with the new value of the NOSCxbits. If they are the same, then the clock switchis a redundant operation. In this case, theOSWEN bit is cleared automatically and theclock switch is aborted.
2. If a valid clock switch has been initiated, theLOCK (OSCCON<5>) and CF (OSCCON<3>)bits are cleared.
3. The new oscillator is turned on by the hardwareif it is not currently running. If a crystal oscillatormust be turned on, the hardware will wait untilthe OST expires. If the new source is using thePLL, then the hardware waits until a PLL lock isdetected (LOCK = 1).
4. The hardware waits for 10 clock cycles from thenew clock source and then performs the clockswitch.
5. The hardware clears the OSWEN bit to indicate asuccessful clock transition. In addition, theNOSCx bit values are transferred to the COSCxbits.
6. The old clock source is turned off at this time,with the exception of LPRC (if WDT or FSCMare enabled) or SOSC (if SOSCEN remainsset).
A recommended code sequence for a clock switchincludes the following:
1. Disable interrupts during the OSCCON registerunlock and write sequence.
2. Execute the unlock sequence for the OSCCONhigh byte by writing 78h and 9Ah toOSCCON<15:8> in two back-to-backinstructions.
3. Write new oscillator source to the NOSCx bits inthe instruction immediately following the unlocksequence.
4. Execute the unlock sequence for the OSCCONlow byte by writing 46h and 57h toOSCCON<7:0> in two back-to-back instructions.
5. Set the OSWEN bit in the instruction immediatelyfollowing the unlock sequence.
6. Continue to execute code that is not clocksensitive (optional).
7. Invoke an appropriate amount of software delay(cycle counting) to allow the selected oscillatorand/or PLL to start and stabilize.
8. Check to see if OSWEN is �0�. If it is, the switchwas successful. If OSWEN is still set, thencheck the LOCK bit to determine the cause offailure.
The core sequence for unlocking the OSCCON registerand initiating a clock switch is shown in Example 7-1.
EXAMPLE 7-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING
Note 1: The processor will continue to executecode throughout the clock switchingsequence. Timing sensitive code shouldnot be executed during this time.
2: Direct clock switches between anyprimary oscillator mode with PLL andFRCPLL mode are not permitted. Thisapplies to clock switches in either direc-tion. In these instances, the applicationmust switch to FRC mode as a transitionclock source between the two PLLmodes.
;Place the new oscillator selection in W0;OSCCONH (high byte) Unlock SequenceMOV #OSCCONH, w1MOV #0x78, w2MOV #0x9A, w3MOV.b w2, [w1]MOV.b w3, [w1];Set new oscillator selectionMOV.b WREG, OSCCONH;OSCCONL (low byte) unlock sequenceMOV #OSCCONL, w1MOV #0x46, w2MOV #0x57, w3MOV.b w2, [w1]MOV.b w3, [w1];Start oscillator switch operationBSET OSCCON,#0
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 93
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NOTES:DS39881C-page 94 Preliminary © 2008 Microchip Technology Inc.
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8.0 POWER-SAVING FEATURES
The PIC24FJ64GA004 family of devices provides theability to manage power consumption by selectivelymanaging clocking to the CPU and the peripherals. Ingeneral, a lower clock frequency and a reduction in thenumber of circuits being clocked constitutes lowerconsumed power. All PIC24F devices manage powerconsumption in four different ways:
� Clock frequency� Instruction-based Sleep and Idle modes� Software controlled Doze mode� Selective peripheral control in software
Combinations of these methods can be used to selec-tively tailor an application�s power consumption, whilestill maintaining critical application features, such astiming-sensitive communications.
8.1 Clock Frequency and Clock Switching
PIC24F devices allow for a wide range of clockfrequencies to be selected under application control. Ifthe system clock configuration is not locked, users canchoose low-power or high-precision oscillators by simplychanging the NOSC bits. The process of changing a sys-tem clock during operation, as well as limitations to theprocess, are discussed in more detail in Section 7.0�Oscillator Configuration�.
8.2 Instruction-Based Power-Saving Modes
PIC24F devices have two special power-saving modesthat are entered through the execution of a specialPWRSAV instruction. Sleep mode stops clock operationand halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules tocontinue operation. The assembly syntax of thePWRSAV instruction is shown in Example 8-1.
Sleep and Idle modes can be exited as a result of anenabled interrupt, WDT time-out or a device Reset.When the device exits these modes, it is said to�wake-up�.
8.2.1 SLEEP MODESleep mode has these features:
� The system clock source is shut down. If an on-chip oscillator is used, it is turned off.
� The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current.
� The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled.
� The LPRC clock will continue to run in Sleep mode if the WDT is enabled.
� The WDT, if enabled, is automatically cleared prior to entering Sleep mode.
� Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode.
The device will wake-up from Sleep mode on any of thethese events:
� On any interrupt source that is individually enabled
� On any form of device Reset� On a WDT time-out
On wake-up from Sleep, the processor will restart withthe same clock source that was active when Sleepmode was entered.
EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 10. Power-Saving Features�(DS39698). Additional power-saving tipscan also be found in Appendix B: �Addi-tional Guidance for PIC24FJ64GA004Family Applications� of this document.
Note: SLEEP_MODE and IDLE_MODE are con-stants defined in the assembler includefile for the selected device.
PWRSAV #SLEEP_MODE ; Put the device into SLEEP modePWRSAV #IDLE_MODE ; Put the device into IDLE mode
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8.2.2 IDLE MODEIdle mode has these features:� The CPU will stop executing instructions.� The WDT is automatically cleared.� The system clock source remains active. By
default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 �Selective Peripheral Module Control�).
� If the WDT or FSCM is enabled, the LPRC will also remain active.
The device will wake from Idle mode on any of theseevents:
� Any interrupt that is individually enabled. � Any device Reset.� A WDT time-out.
On wake-up from Idle, the clock is reapplied to the CPUand instruction execution begins immediately, startingwith the instruction following the PWRSAV instruction orthe first instruction in the ISR.
8.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of aPWRSAV instruction will be held off until entry into Sleepor Idle mode has completed. The device will thenwake-up from Sleep or Idle mode.
8.3 Doze ModeGenerally, changing clock speed and invoking one ofthe power-saving modes are the preferred strategiesfor reducing power consumption. There may be cir-cumstances, however, where this is not practical. Forexample, it may be necessary for an application tomaintain uninterrupted synchronous communication,even while it is doing nothing else. Reducing systemclock speed may introduce communication errors,while using a power-saving mode may stopcommunications completely.
Doze mode is a simple and effective alternative methodto reduce power consumption while the device is stillexecuting code. In this mode, the system clock contin-ues to operate from the same source and at the samespeed. Peripheral modules continue to be clocked atthe same speed while the CPU clock speed is reduced.Synchronization between the two clock domains ismaintained, allowing the peripherals to access theSFRs while the CPU executes code at a slower rate.
Doze mode is enabled by setting the DOZEN bit(CLKDIV<11>). The ratio between peripheral and coreclock speed is determined by the DOZE2:DOZE0 bits(CLKDIV<14:12>). There are eight possibleconfigurations, from 1:1 to 1:256, with 1:1 being thedefault.
It is also possible to use Doze mode to selectivelyreduce power consumption in event driven applica-tions. This allows clock sensitive functions, such assynchronous communications, to continue withoutinterruption while the CPU Idles, waiting for somethingto invoke an interrupt routine. Enabling the automaticreturn to full-speed CPU operation on interrupts isenabled by setting the ROI bit (CLKDIV<15>). Bydefault, interrupt events have no effect on Doze modeoperation.
8.4 Selective Peripheral Module Control
Idle and Doze modes allow users to substantiallyreduce power consumption by slowing or stopping theCPU clock. Even so, peripheral modules still remainclocked and thus consume power. There may be caseswhere the application needs what these modes do notprovide: the allocation of power resources to CPUprocessing with minimal power consumption from theperipherals.
PIC24F devices address this requirement by allowingperipheral modules to be selectively disabled, reducingor eliminating their power consumption. This can bedone with two control bits:
� The Peripheral Enable bit, generically named, �XXXEN�, located in the module�s main control SFR.
� The Peripheral Module Disable (PMD) bit, generically named, �XXXMD�, located in one of the PMD control registers.
Both bits have similar functions in enabling or disablingits associated module. Setting the PMD bit for a moduledisables all clock sources to that module, reducing itspower consumption to an absolute minimum. In thisstate, the control and status registers associated withthe peripheral will also be disabled, so writes to thoseregisters will have no effect and read values will beinvalid. Many peripheral modules have a correspondingPMD bit.
In contrast, disabling a module by clearing its XXXENbit disables its functionality, but leaves its registersavailable to be read and written to. Power consumptionis reduced, but not by as much as the PMD bit does.Most peripheral modules have an enable bit;exceptions include capture, compare and RTCC.
To achieve more selective power savings, peripheralmodules can also be selectively disabled when thedevice enters Idle mode. This is done through thecontrol bit of the generic name format, �XXXIDL�. Bydefault, all modules that can operate during Idle modewill do so. Using the disable on Idle feature allows fur-ther reduction of power consumption during Idle mode,enhancing power savings for extremely critical powerapplications.
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9.0 I/O PORTS
All of the device pins (except VDD, VSS, MCLR andOSCI/CLKI) are shared between the peripherals andthe parallel I/O ports. All I/O input ports feature SchmittTrigger inputs for improved noise immunity.
9.1 Parallel I/O (PIO) PortsA parallel I/O port that shares a pin with a peripheral is,in general, subservient to the peripheral. The periph-eral�s output buffer data and control signals areprovided to a pair of multiplexers. The multiplexersselect whether the peripheral or the associated porthas ownership of the output data and control signals ofthe I/O pin. The logic also prevents �loop through�, inwhich a port�s digital output can drive the input of aperipheral that shares the same pin. Figure 9-1 showshow ports are shared with other peripherals and theassociated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral isactively driving an associated pin, the use of the pin asa general purpose output pin is disabled. The I/O pinmay be read, but the output driver for the parallel portbit will be disabled. If a peripheral is enabled, but theperipheral is not actively driving a pin, that pin may bedriven by a port.
All port pins have three registers directly associatedwith their operation as digital I/O. The Data Directionregister (TRISx) determines whether the pin is an inputor an output. If the data direction bit is a �1�, then the pinis an input. All port pins are defined as inputs after aReset. Reads from the Output Latch register (LATx),read the latch. Writes to the latch, write the latch.Reads from the port (PORTx), read the port pins, whilewrites to the port pins, write the latch.
Any bit and its associated data and control registersthat are not valid for a particular device will bedisabled. That means the corresponding LATx andTRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or func-tion that is defined as an input only, it is, nevertheless,regarded as a dedicated port because there is noother competing source of outputs.
FIGURE 9-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 12. I/O Ports with PeripheralPin Select (PPS)� (DS39711).
QD
CK
WR LAT +
TRIS Latch
I/O Pin
WR PORT
Data Bus
QD
CK
Data Latch
Read PORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output DataOutput Enable
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT
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9.1.1 OPEN-DRAIN CONFIGURATIONIn addition to the PORT, LAT and TRIS registers fordata control, each port pin can also be individually con-figured for either digital or open-drain output. This iscontrolled by the Open-Drain Control register, ODCx,associated with each port. Setting any of the bits con-figures the corresponding pin to act as an open-drainoutput.The open-drain feature allows the generation ofoutputs higher than VDD (e.g., 5V) on any desireddigital only pins by using external pull-up resistors. Themaximum open-drain voltage allowed is the same asthe maximum VIH specification.
9.2 Configuring Analog Port PinsThe use of the AD1PCFG and TRIS registers controlthe operation of the A/D port pins. The port pins that aredesired as analog inputs must have their correspond-ing TRIS bit set (input). If the TRIS bit is cleared(output), the digital output level (VOH or VOL) will beconverted.
When reading the PORT register, all pins configured asanalog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert ananalog input. Analog levels on any pin that is defined asa digital input (including the ANx pins) may cause theinput buffer to consume current that exceeds thedevice specifications.
9.2.1 I/O PORT WRITE/READ TIMINGOne instruction cycle is required between a portdirection change or port write operation and a readoperation of the same port. Typically, this instructionwould be a NOP.
9.3 Input Change NotificationThe input change notification function of the I/O portsallows the PIC24FJ64GA004 family of devices to gen-erate interrupt requests to the processor in response toa change of state on selected input pins. This feature iscapable of detecting input change of states even inSleep mode, when the clocks are disabled. Dependingon the device pin count, there are up to 22 external sig-nals (CN0 through CN21) that may be selected(enabled) for generating an interrupt request on achange of state.
There are four control registers associated with the CNmodule. The CNEN1 and CNEN2 registers contain theinterrupt enable control bits for each of the CN inputpins. Setting any of these bits enables a CN interruptfor the corresponding pins.
Each CN pin also has a weak pull-up connected to it.The pull-ups act as a current source that is connectedto the pin, and eliminate the need for external resistorswhen push button or keypad devices are connected.The pull-ups are enabled separately using the CNPU1and CNPU2 registers, which contain the control bits foreach of the CN pins. Setting any of the control bitsenables the weak pull-ups for the corresponding pins.
When the internal pull-up is selected, the pin pulls up toVDD � 0.7V (typical). Make sure that there is no externalpull-up source when the internal pull-ups are enabled,as the voltage difference can cause a current path.
EXAMPLE 9-1: PORT WRITE/READ EXAMPLE
Note: Pull-ups on change notification pinsshould always be disabled whenever theport pin is configured as a digital output.
MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputsMOV W0, TRISBB ; and PORTB<7:0> as outputsNOP ; Delay 1 cycleBTSS PORTB, #13 ; Next Instruction
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9.4 Peripheral Pin Select A major challenge in general purpose devices is provid-ing the largest possible set of peripheral features whileminimizing the conflict of features on I/O pins. The chal-lenge is even greater on low pin count devices similarto the PIC24FJ64GA family. In an application thatneeds to use more than one peripheral multiplexed onsingle pin, inconvenient workarounds in applicationcode or a complete redesign may be the only option.The peripheral pin select feature provides an alterna-tive to these choices by enabling the user�s peripheralset selection and their placement on a wide range ofI/O pins. By increasing the pinout options available ona particular device, users can better tailor themicrocontroller to their entire application, rather thantrimming the application to fit the device.
The peripheral pin select feature operates over a fixedsubset of digital I/O pins. Users may independentlymap the input and/or output of any one of many digitalperipherals to any one of these I/O pins. Peripheral pinselect is performed in software and generally does notrequire the device to be reprogrammed. Hardwaresafeguards are included that prevent accidental orspurious changes to the peripheral mapping once it hasbeen established.
9.4.1 AVAILABLE PINSThe peripheral pin select feature is used with a rangeof up to 26 pins; the number of available pins is depen-dent on the particular device and its pincount. Pins thatsupport the peripheral pin select feature include thedesignation �RPn� in their full pin designation, where�RP� designates a remappable peripheral and �n� is theremappable pin number. See Table 1-2 for pinoutoptions in Each Package Offering.
9.4.2 AVAILABLE PERIPHERALSThe peripherals managed by the peripheral pin selectare all digital only peripherals. These include generalserial communications (UART and SPI), general pur-pose timer clock inputs, timer related peripherals (inputcapture and output compare) and external interruptinputs. Also included are the outputs of the comparatormodule, since these are discrete digital signals.
The peripheral pin select module is not applied toI2C�, change notification inputs, RTCC alarm outputsor peripherals with analog inputs.
A key difference between pin select and non pin selectperipherals is that pin select peripherals are not asso-ciated with a default I/O pin. The peripheral mustalways be assigned to a specific I/O pin before it can beused. In contrast, non pin select peripherals are alwaysavailable on a default pin, assuming that the peripheralis active and not conflicting with another peripheral.
9.4.2.1 Peripheral Pin Select Function Priority
When a pin selectable peripheral is active on a givenI/O pin, it takes priority over all other digital I/O and dig-ital communication peripherals associated with the pin.Priority is given regardless of the type of peripheral thatis mapped. Pin select peripherals never take priorityover any analog functions associated with the pin.
9.4.3 CONTROLLING PERIPHERAL PIN SELECT
Peripheral pin select features are controlled throughtwo sets of Special Function Registers: one to mapperipheral inputs, and one to map outputs. Becausethey are separately controlled, a particular peripheral�sinput and output (if the peripheral has both) can beplaced on any selectable function pin withoutconstraint.
The association of a peripheral to a peripheral select-able pin is handled in two different ways, depending onif an input or an output is being mapped.
9.4.3.1 Input MappingThe inputs of the peripheral pin select options aremapped on the basis of the peripheral; that is, a controlregister associated with a peripheral dictates the pin itwill be mapped to. The RPINRx registers are used toconfigure peripheral input mapping (see Register 9-1through Register 9-14). Each register contains two setsof 5-bit fields, with each set associated with one of thepin selectable peripherals. Programming a givenperipheral�s bit field with an appropriate 5-bit valuemaps the RPn pin with that value to that peripheral. Forany given device, the valid range of values for any ofthe bit fields corresponds to the maximum number ofperipheral pin selections supported by the device.
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TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)9.4.3.2 Output MappingIn contrast to inputs, the outputs of the peripheral pinselect options are mapped on the basis of the pin. Inthis case, a control register associated with a particularpin dictates the peripheral output to be mapped. TheRPORx registers are used to control output mapping.Like the RPINRx registers, each register contains two5-bit fields; each field being associated with one RPnpin (see Register 9-15 through Register 9-27). Thevalue of the bit field corresponds to one of the periph-erals and that peripheral�s output is mapped to the pin(see Table 9-2).
Because of the mapping technique, the list of peripher-als for output mapping also includes a null value of�00000�. This permits any given pin to remain discon-nected from the output of any of the pin selectableperipherals.
Input Name Function Name Register ConfigurationBits
External Interrupt 1 INT1 RPINR0 INTR1<4:0>External Interrupt 2 INT2 RPINR1 INTR2R<4:0>Timer2 External Clock T2CK RPINR3 T2CKR<4:0>Timer3 External Clock T3CK RPINR3 T3CKR<4:0>Timer4 External Clock T4CK RPINR4 T4CKR<4:0>Timer5 External Clock T5CK RPINR4 T5CKR<4:0>Input Capture 1 IC1 RPINR7 IC1R<4:0>Input Capture 2 IC2 RPINR7 IC2R<4:0>Input Capture 3 IC3 RPINR8 IC3R<4:0>Input Capture 4 IC4 RPINR8 IC4R<4:0>Input Capture 5 IC5 RPINR9 IC5R<4:0>Output Compare Fault A OCFA RPINR11 OCFAR<4:0>Output Compare Fault B OCFB RPINR11 OCFBR<4:0>UART1 Receive U1RX RPINR18 U1RXR<4:0>UART1 Clear To Send U1CTS RPINR18 U1CTSR<4:0>UART2 Receive U2RX RPINR19 U2RXR<4:0>UART2 Clear To Send U2CTS RPINR19 U2CTSR<4:0>SPI1 Data Input SDI1 RPINR20 SDI1R<4:0>SPI1 Clock Input SCK1IN RPINR20 SCK1R<4:0>SPI1 Slave Select Input SS1IN RPINR21 SS1R<4:0>SPI2 Data Input SDI2 RPINR22 SDI2R<4:0>SPI2 Clock Input SCK2IN RPINR22 SCK2R<4:0>SPI2 Slave Select Input SS2IN RPINR23 SS2R<4:0>Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
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TABLE 9-2: SELECTABLE OUTPUTSOURCES (MAPS FUNCTION TO OUTPUT)
9.4.3.3 Mapping LimitationsThe control schema of the peripheral pin select isextremely flexible. Other than systematic blocks thatprevent signal contention caused by two physical pinsbeing configured as the same functional input or twofunctional outputs configured as the same pin, thereare no hardware enforced lock outs. The flexibilityextends to the point of allowing a single input to drivemultiple peripherals or a single functional output todrive multiple output pins.
9.4.4 CONTROLLING CONFIGURATION CHANGES
Because peripheral remapping can be changed duringrun time, some restrictions on peripheral remappingare needed to prevent accidental configurationchanges. PIC24F devices include three features toprevent alterations to the peripheral map:
� Control register lock sequence� Continuous state monitoring� Configuration bit remapping lock
9.4.4.1 Control Register LockUnder normal operation, writes to the RPINRx andRPORx registers are not allowed. Attempted writes willappear to execute normally, but the contents of theregisters will remain unchanged. To change these reg-isters, they must be unlocked in hardware. The registerlock is controlled by the IOLOCK bit (OSCCON<6>).Setting IOLOCK prevents writes to the controlregisters; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequencemust be executed:
1. Write 46h to OSCCON<7:0>.2. Write 57h to OSCCON<7:0>.3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator�s LOCKbit, IOLOCK remains in one state until changed. Thisallows all of the peripheral pin selects to be configuredwith a single unlock sequence followed by an update toall control registers, then locked with a second locksequence.
9.4.4.2 Continuous State MonitoringIn addition to being protected from direct writes, thecontents of the RPINRx and RPORx registers areconstantly monitored in hardware by shadow registers.If an unexpected change in any of the registers occurs(such as cell disturbances caused by ESD or otherexternal events), a Configuration Mismatch Reset willbe triggered.
9.4.4.3 Configuration Bit Pin Select LockAs an additional level of safety, the device can be con-figured to prevent more than one write session to theRPINRx and RPORx registers. The IOL1WAY(CW2<4>) Configuration bit blocks the IOLOCK bitfrom being cleared after it has been set once. IfIOLOCK remains set, the register unlock procedure willnot execute and the Peripheral Pin Select Control reg-isters cannot be written to. The only way to clear the bitand re-enable peripheral remapping is to perform adevice Reset.
In the default (unprogrammed) state, IOL1WAY is set,restricting users to one write session. ProgrammingIOL1WAY allows users unlimited access (with theproper use of the unlock sequence) to the PeripheralPin Select registers.
Function Output Function Number(1) Output Name
NULL(2) 0 NULLC1OUT 1 Comparator 1 OutputC2OUT 2 Comparator 2 OutputU1TX 3 UART1 TransmitU1RTS(3) 4 UART1 Request To SendU2TX 5 UART2 TransmitU2RTS(3) 6 UART2 Request To SendSDO1 7 SPI1 Data OutputSCK1OUT 8 SPI1 Clock OutputSS1OUT 9 SPI1 Slave Select OutputSDO2 10 SPI2 Data OutputSCK2OUT 11 SPI2 Clock OutputSS2OUT 12 SPI2 Slave Select OutputOC1 18 Output Compare 1OC2 19 Output Compare 2OC3 20 Output Compare 3OC4 21 Output Compare 4OC5 22 Output Compare 5Note 1: Value assigned to the RPn<4:0> pins corre-
sponds to the peripheral output function number.
2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.
3: IrDA® BCLK functionality uses this output.
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9.4.5 CONSIDERATIONS FORPERIPHERAL PIN SELECTIONThe ability to control peripheral pin selection introducesseveral considerations into application design thatcould be overlooked. This is particularly true for severalcommon peripherals that are available only asremappable peripherals.
The main consideration is that the peripheral pinselects are not available on default pins in the device�sdefault (Reset) state. Since all RPINRx registers resetto �11111� and all RPORx registers reset to �00000�, allperipheral pin select inputs are tied to RP31 and allperipheral pin select outputs are disconnected.
This situation requires the user to initialize the devicewith the proper peripheral configuration before anyother application code is executed. Since the IOLOCKbit resets in the unlocked state, it is not necessary toexecute the unlock sequence after the device hascome out of Reset. For application safety, however, it isbest to set IOLOCK and lock the configuration afterwriting to the control registers.
Because the unlock sequence is timing critical, it mustbe executed as an assembly language routine in thesame manner as changes to the oscillator configura-tion. If the bulk of the application is written in C oranother high-level language, the unlock sequenceshould be performed by writing inline assembly.
Choosing the configuration requires the review of allperipheral pin selects and their pin assignments,especially those that will not be used in the application.In all cases, unused pin-selectable peripherals shouldbe disabled completely. Unused peripherals shouldhave their inputs assigned to an unused RPn pinfunction. I/O pins with unused RPn functions should beconfigured with the null peripheral output.
The assignment of a peripheral to a particular pin doesnot automatically perform any other configuration of thepin�s I/O circuitry. In theory, this means adding apin-selectable output to a pin may mean inadvertentlydriving an existing peripheral input when the output isdriven. Users must be familiar with the behavior ofother fixed peripherals that share a remappable pin andknow when to enable or disable them. To be safe, fixeddigital peripherals that share the same pin should bedisabled when not in use.
Along these lines, configuring a remappable pin for aspecific peripheral does not automatically turn that fea-ture on. The peripheral must be specifically configuredfor operation and enabled, as if it were tied to a fixed pin.Where this happens in the application code (immediatelyfollowing device Reset and peripheral configuration orinside the main application routine) depends on theperipheral and its use in the application.
A final consideration is that peripheral pin select func-tions neither override analog inputs, nor reconfigurepins with analog functions for digital I/O. If a pin isconfigured as an analog input on device Reset, it mustbe explicitly reconfigured as digital I/O when used witha peripheral pin select.
Example 9-2 shows a configuration for bidirectionalcommunication with flow control using UART1. Thefollowing input and output functions are used:
� Input Functions: U1RX, U1CTS� Output Functions: U1TX, U1RTS
EXAMPLE 9-2: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS
Note: In tying peripheral pin select inputs toRP31, RP31 does not have to exist on adevice for the registers to be reset to it. //*************************************
// Unlock Registers//*************************************asm volatile ( "MOV #OSCCON, w1 \n"
"MOV #0x46, w2 \n""MOV #0x57, w3 \n""MOV.b w2, [w1] \n""MOV.b w3, [w1] \n""BCLR OSCCON,#6");
//***************************// Configure Input Functions// (See Table 9-1)//***************************
//***************************// Assign U1RX To Pin RP0//***************************RPINR18bits.U1RXR = 0;
//***************************// Assign U1CTS To Pin RP1//***************************RPINR18bits.U1CTSR = 1;
//***************************// Configure Output Functions// (See Table 9-2)//***************************
//***************************// Assign U1TX To Pin RP2//***************************RPOR1bits.RP2R = 3;
//***************************// Assign U1RTS To Pin RP3//***************************RPOR1bits.RP3R = 4;
//*************************************// Lock Registers//*************************************asm volatile ( "MOV #OSCCON, w1 \n"
"MOV #0x46, w2 \n""MOV #0x57, w3 \n""MOV.b w2, [w1] \n""MOV.b w3, [w1] \n""BSET OSCCON, #6" );
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9.5 Peripheral Pin Select RegistersThe PIC24FJ64GA004 family of devices implements atotal of 27 registers for remappable peripheralconfiguration:� Input Remappable Peripheral Registers (14)� Output Remappable Peripheral Registers (13)Note: Input and output register values can onlybe changed if OSCCON<IOLOCK> = 0.See Section 9.4.4.1 �Control RegisterLock� for a specific command sequence.
REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 INT1R4:INT1R0: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bitsbit 7-0 Unimplemented: Read as �0�
REGISTER 9-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � INT2R4 INT2R3 INT2R2 INT2R1 INT2R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as �0� bit 4-0 INT2R4:INT2R0: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
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REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 T3CKR4:T3CKR0: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 T2CKR4:T2CKR0: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits
REGISTER 9-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 T5CKR4:T5CKR0: Assign Timer5 External Clock (T5CK) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 T4CKR4:T4CKR0: Assign Timer4 External Clock (T4CK) to the Corresponding RPn Pin bits
DS39881C-page 104 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 9-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � IC1R4 IC1R3 IC1R2 IC1R1 IC1R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 IC2R4:IC2R0: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 IC1R4:IC1R0: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
REGISTER 9-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � IC4R4 IC4R3 IC4R2 IC4R1 IC4R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � IC3R4 IC3R3 IC3R2 IC3R1 IC3R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 105
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REGISTER 9-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � IC5R4 IC5R3 IC5R2 IC5R1 IC5R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as �0� bit 4-0 IC5R4:IC5R0: Assign Input Capture 5 (IC5) to the Corresponding RPn Pin bits
REGISTER 9-8: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 OCFBR4:OCFBR0: Assign Output Compare Fault B (OCFB) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 OCFAR4:OCFAR0: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
DS39881C-page 106 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 9-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 U1CTSR4:U1CTSR0: Assign UART1 Clear to Send (U1CTS) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 U1RXR4:U1RXR0: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
REGISTER 9-10: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 107
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REGISTER 9-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 SCK1R4:SCK1R0: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 SDI1R4:SDI1R0: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
REGISTER 9-12: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as �0� bit 4-0 SS1R4:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits
DS39881C-page 108 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 9-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 SCK2R4:SCK2R0: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn Pin bitsbit 7-5 Unimplemented: Read as �0� bit 4-0 SDI2R4:SDI2R0: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
REGISTER 9-14: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1� � � SS2R4 SS2R3 SS2R2 SS2R1 SS2R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as �0� bit 4-0 SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 109
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REGISTER 9-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP1R4 RP1R3 RP1R2 RP1R1 RP1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP0R4 RP0R3 RP0R2 RP0R1 RP0R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP1R4:RP1R0: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP0R4:RP0R0: Peripheral Output Function is Assigned to RP0 Output Pin bits
(see Table 9-2 for peripheral function numbers)
REGISTER 9-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP3R4 RP3R3 RP3R2 RP3R1 RP3R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP2R4 RP2R3 RP2R2 RP2R1 RP2R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP3R4:RP3R0: Peripheral Output Function is Assigned to RP3 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP2R4:RP2R0: Peripheral Output Function is Assigned to RP2 Output Pin bits
(see Table 9-2 for peripheral function numbers)
DS39881C-page 110 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 9-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP5R4 RP5R3 RP5R2 RP5R1 RP5R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP4R4 RP4R3 RP4R2 RP4R1 RP4R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP5R4:RP5R0: Peripheral Output Function is Assigned to RP5 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP4R4:RP4R0: Peripheral Output Function is Assigned to RP4 Output Pin bits
(see Table 9-2 for peripheral function numbers)
REGISTER 9-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP7R4 RP7R3 RP7R2 RP7R1 RP7R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP6R4 RP6R3 RP6R2 RP6R1 RP6R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP7R4:RP7R0: Peripheral Output Function is Assigned to RP7 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits
(see Table 9-2 for peripheral function numbers)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 111
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REGISTER 9-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP9R4 RP9R3 RP9R2 RP9R1 RP9R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP8R4 RP8R3 RP8R2 RP8R1 RP8R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP9R4:RP9R0: Peripheral Output Function is Assigned to RP9 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP8R4:RP8R0: Peripheral Output Function is Assigned to RP8 Output Pin bits
(see Table 9-2 for peripheral function numbers)
REGISTER 9-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP11R4 RP11R3 RP11R2 RP11R1 RP11R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP10R4 RP10R3 RP10R2 RP10R1 RP10R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP11R4:RP11R0: Peripheral Output Function is Assigned to RP11 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP10R4:RP10R0: Peripheral Output Function is Assigned to RP10 Output Pin bits
(see Table 9-2 for peripheral function numbers)
DS39881C-page 112 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 9-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP13R4 RP13R3 RP13R2 RP13R1 RP13R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP12R4 RP12R3 RP12R2 RP12R1 RP12R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP13R4:RP13R0: Peripheral Output Function is Assigned to RP13 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP12R4:RP12R0: Peripheral Output Function is Assigned to RP12 Output Pin bits
(see Table 9-2 for peripheral function numbers)
REGISTER 9-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP15R4 RP15R3 RP15R2 RP15R1 RP15R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP14R4 RP14R3 RP14R2 RP14R1 RP14R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP15R4:RP15R0: Peripheral Output Function is Assigned to RP15 Output Pin bits
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits
(see Table 9-2 for peripheral function numbers)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 113
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REGISTER 9-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP16R4(1) RP16R3(1) RP16R2(1) RP16R1(1) RP16R0(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP17R4:RP17R0: Peripheral Output Function is Assigned to RP17 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP16R4:RP16R0: Peripheral Output Function is Assigned to RP16 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)
Note 1: Bits are only available on the 44-pin devices; otherwise, they read as �0�.
REGISTER 9-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP19R4 RP19R3 RP19R2 RP19R1 RP19R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP18R4 RP18R3 RP18R2 RP18R1 RP18R0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP19R4:RP19R0: Peripheral Output Function is Assigned to RP19 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP18R4:RP18R0: Peripheral Output Function is Assigned to RP18 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)
Note 1: Bits are only available on the 44-pin devices; otherwise, they read as �0�.
DS39881C-page 114 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 9-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP21R4(1) RP21R3(1) RP21R2(1) RP21R1(1) RP21R0(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP20R4(1) RP20R3(1) RP20R2(1) RP20R1(1) RP20R0(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP21R4:RP21R0: Peripheral Output Function is Assigned to RP21 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP20R4:RP20R0: Peripheral Output Function is Assigned to RP20 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)
Note 1: Bits are only available on the 44-pin devices; otherwise, they read as �0�.
REGISTER 9-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP23R4(1) RP23R3(1) RP23R2(1) RP23R1(1) RP23R0(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP22R4(1) RP22R3(1) RP22R2(1) RP22R1(1) RP22R0(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP23R4:RP23R0: Peripheral Output Function is Assigned to RP23 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)
Note 1: Bits are only available on the 44-pin devices; otherwise, they read as �0�.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 115
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REGISTER 9-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP25R4(1) RP25R3(1) RP25R2(1) RP25R1(1) RP25R0(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � RP24R4(1) RP24R3(1) RP24R2(1) RP24R1(1) RP24R0(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0� bit 12-8 RP25R4:RP25R0: Peripheral Output Function is Assigned to RP25 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)bit 7-5 Unimplemented: Read as �0� bit 4-0 RP24R4:RP24R0: Peripheral Output Function is Assigned to RP24 Output Pin bits(1)
(see Table 9-2 for peripheral function numbers)
Note 1: Bits are only available on the 44-pin devices; otherwise, they read as �0�.
DS39881C-page 116 Preliminary © 2008 Microchip Technology Inc.
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10.0 TIMER1
The Timer1 module is a 16-bit timer which can serve asthe time counter for the Real-Time Clock (RTC), oroperate as a free-running, interval timer/counter.Timer1 can operate in three modes:
� 16-Bit Timer� 16-Bit Synchronous Counter� 16-Bit Asynchronous Counter
Timer1 also supports these features:
� Timer Gate Operation� Selectable Prescaler Settings� Timer Operation during CPU Idle and Sleep
modes� Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
Figure 10-1 presents a block diagram of the 16-bittimer module.
To configure Timer1 for operation:
1. Set the TON bit (= 1).2. Select the timer prescaler ratio using the
TCKPS1:TCKPS0 bits.3. Set the Clock and Gating modes using the TCS
and TGATE bits.4. Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.5. Load the timer period value into the PR1
register.6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP2:T1IP0, toset the interrupt priority.
FIGURE 10-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 14. Timers� (DS39704).
TON
Sync
SOSCI
SOSCO/
PR1
Set T1IF
EqualComparator
TMR1Reset
SOSCEN
1
0
TSYNC
Q
Q D
CK
TCKPS1:TCKPS0
Prescaler1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
1x
01
TGATE
00
GateSync
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 117
PIC24FJ64GA004 FAMILY
REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0TON � TSIDL � � � � �
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0� TGATE TCKPS1 TCKPS0 � TSYNC TCS �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 TON: Timer1 On bit1 = Starts 16-bit Timer10 = Stops 16-bit Timer1
bit 14 Unimplemented: Read as �0�bit 13 TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as �0�bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1: This bit is ignored.When TCS = 0: 1 = Gated time accumulation enabled0 = Gated time accumulation disabled
bit 5-4 TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits11 = 1:256 10 = 1:6401 = 1:8 00 = 1:1
bit 3 Unimplemented: Read as �0�bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1: 1 = Synchronize external clock input0 = Do not synchronize external clock inputWhen TCS = 0: This bit is ignored.
bit 1 TCS: Timer1 Clock Source Select bit1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as �0�
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PIC24FJ64GA004 FAMILY
11.0 TIMER2/3 AND TIMER4/5
The Timer2/3 and Timer4/5 modules are 32-bit timers,which can also be configured as four independent 16-bittimers with selectable operating modes.
As a 32-bit timer, Timer2/3 and Timer4/5 operate inthree modes:
� Two independent 16-bit timers (Timer2 and Timer3) with all 16-bit operating modes (except Asynchronous Counter mode)
� Single 32-bit timer� Single 32-bit synchronous counter
They also support these features:
� Timer gate operation� Selectable prescaler settings� Timer operation during Idle and Sleep modes� Interrupt on a 32-Bit Period register match� ADC Event Trigger (Timer4/5 only)
Individually, all four of the 16-bit timers can function assynchronous timers or counters. They also offer thefeatures listed above, except for the ADC EventTrigger; this is implemented only with Timer5. Theoperating modes and enabled features are determinedby setting the appropriate bit(s) in the T2CON, T3CON,T4CON and T5CON registers. T2CON and T4CON areshown in generic form in Register 11-1; T3CON andT5CON are shown in Register 11-2.
For 32-bit timer/counter operation, Timer2 and Timer4are the least significant word; Timer3 and Timer4 arethe most significant word of the 32-bit timers.
To configure Timer2/3 or Timer4/5 for 32-bit operation:
1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS1:TCKPS0 bits.3. Set the Clock and Gating modes using the TCS
and TGATE bits. If TCS is set to external clock,RPINRx (TxCK) must be configured to an avail-able RPn pin. See Section 9.4 �Peripheral PinSelect� for more information.
4. Load the timer period value. PR3 (or PR5) willcontain the most significant word of the valuewhile PR2 (or PR4) contains the least significantword.
5. If interrupts are required, set the interrupt enablebit, T3IE or T5IE; use the priority bits,T3IP2:T3IP0 or T5IP2:T5IP0, to set the interruptpriority. Note that while Timer2 or Timer4 con-trols the timer, the interrupt appears as a Timer3or Timer5 interrupt.
6. Set the TON bit (= 1).
The timer value, at any point, is stored in the registerpair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)always contains the most significant word of the count,while TMR2 (TMR4) contains the least significant word.
To configure any of the timers for individual 16-bitoperation:
1. Clear the T32 bit corresponding to that timer(T2CON<3> for Timer2 and Timer3 orT4CON<3> for Timer4 and Timer5).
2. Select the timer prescaler ratio using theTCKPS1:TCKPS0 bits.
3. Set the Clock and Gating modes using the TCSand TGATE bits. See Section 9.4 �PeripheralPin Select� for more information.
4. Load the timer period value into the PRx register.5. If interrupts are required, set the interrupt enable
bit, TxIE; use the priority bits, TxIP2:TxIP0, toset the interrupt priority.
6. Set the TON bit (TxCON<15> = 1).
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 14. Timers� (DS39704).
Note: For 32-bit operation, T3CON and T5CONcontrol bits are ignored. Only T2CON andT4CON control bits are used for setup andcontrol. Timer2 and Timer4 clock and gateinputs are utilized for the 32-bit timermodules, but an interrupt is generated withthe Timer3 or Timer5 interrupt flags.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 119
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FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAMTMR3 TMR2
Set T3IF (T5IF)
EqualComparator
PR3 PR2
Reset
LSB MSB
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers.
2: This peripheral�s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 �Peripheral Pin Select� for more information.
3: The ADC event trigger is available only on Timer2/3.
Data Bus<15:0>
TMR3HLD
Read TMR2 (TMR4)(1)
Write TMR2 (TMR4)(1)
16
16
16
Q
Q D
CK
TGATE
0
1
TON
TCKPS1:TCKPS0
Prescaler1, 8, 64, 256
2
TCY
TCS(2)TGATE(2)
Gate
T2CK
Sync
ADC Event Trigger(3)
Sync
(T4CK)
(PR5) (PR4)
(TMR5HLD)
(TMR5) (TMR4)
1x
01
00
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FIGURE 11-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAMFIGURE 11-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS1:TCKPS0
Prescaler1, 8, 64, 256
2
TCY TCS(1)
1x
01
TGATE(1)
00
Gate
T2CK
Sync
PR2 (PR4)
Set T2IF (T4IF)
EqualComparator
TMR2 (TMR4)Reset
Q
Q D
CK
TGATE
1
0
(T4CK)
Sync
Note 1: This peripheral�s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 �Peripheral Pin Select� for more information.
TONTCKPS1:TCKPS0
2
TCY TCS(1)
1x
01
TGATE(1)
00
T3CK
PR3 (PR5)
Set T3IF (T5IF)
EqualComparator
TMR3 (TMR5)Reset
Q
Q D
CK
TGATE
1
0
ADC Event Trigger(2)
(T5CK)Prescaler
1, 8, 64, 256
Sync
Note 1: This peripheral�s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 �Peripheral Pin Select� for more information.
2: The ADC event trigger is available only on Timer3.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 121
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REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTERR/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0TON � TSIDL � � � � �
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0� TGATE TCKPS1 TCKPS0 T32(1) � TCS(2) �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 TON: Timerx On bitWhen TxCON<3> = 1:1 = Starts 32-bit Timerx/y0 = Stops 32-bit Timerx/yWhen TxCON<3> = 0:1 = Starts 16-bit Timerx0 = Stops 16-bit Timerx
bit 14 Unimplemented: Read as �0�bit 13 TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as �0�bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1: This bit is ignored.When TCS = 0: 1 = Gated time accumulation enabled0 = Gated time accumulation disabled
bit 5-4 TCKPS1:TCKPS0: Timerx Input Clock Prescale Select bits11 = 1:256 10 = 1:6401 = 1:8 00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit(1)
1 = Timerx and Timery form a single 32-bit timer0 = Timerx and Timery act as two 16-bit timersIn 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 2 Unimplemented: Read as �0�bit 1 TCS: Timerx Clock Source Select bit(2)
1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as �0�
Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see
Section 9.4 �Peripheral Pin Select�.
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REGISTER 11-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0TON(1) � TSIDL(1) � � � � �
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0� TGATE(1) TCKPS1(1) TCKPS0(1) � � TCS(1,2) �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 TON: Timery On bit(1)
1 = Starts 16-bit Timery0 = Stops 16-bit Timery
bit 14 Unimplemented: Read as �0�bit 13 TSIDL: Stop in Idle Mode bit(1)
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as �0�bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled0 = Gated time accumulation disabled
bit 5-4 TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits(1)
11 = 1:256 10 = 1:6401 = 1:8 00 = 1:1
bit 3-2 Unimplemented: Read as �0�bit 1 TCS: Timery Clock Source Select bit(1,2)
1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as �0�
Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 123
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NOTES:DS39881C-page 124 Preliminary © 2008 Microchip Technology Inc.
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12.0 INPUT CAPTURE
FIGURE 12-1: INPUT CAPTURE BLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 15. Input Capture� (DS39701).
ICxBUF
ICx PinICM<2:0> (ICxCON<2:0>)
Mode Select3
1 0
Set Flag ICxIF(in IFSn Register)
TMRy TMRx
Edge Detection Logic
16 16
FIFOR/WLogic
ICI<1:0>
ICOV, ICBNE (ICxCON<4:3>)
ICxCONInterrupt
Logic
System Bus
From 16-Bit Timers
ICTMR(ICxCON<7>)
FIFO
PrescalerCounter(1, 4, 16)
andClock Synchronizer
Note 1: An �x� in a signal, register or bit name denotes the number of the capture channel.2: This peripheral�s inputs must be assigned to an available RPn pin before use. Please see Section 9.4
�Peripheral Pin Select� for more information.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 125
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12.1 Input Capture RegistersREGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0� � ICSIDL � � � � �
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0ICTMR ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0�bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode0 = Input capture module will continue to operate in CPU Idle mode
bit 12-8 Unimplemented: Read as �0�bit 7 ICTMR: Input Capture x Timer Select bit
1 = TMR2 contents are captured on capture event0 = TMR3 contents are captured on capture event
bit 6-5 ICI1:ICI0: Select Number of Captures per Interrupt bits11 = Interrupt on every fourth capture event10 = Interrupt on every third capture event01 = Interrupt on every second capture event00 = Interrupt on every capture event
bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)1 = Input capture overflow occurred0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only)1 = Input capture buffer is not empty, at least one more capture value can be read0 = Input capture buffer is empty
bit 2-0 ICM2:ICM0: Input Capture x Mode Select bits(1)
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edgedetect only, all other control bits are not applicable)
110 = Unused (module disabled)101 = Capture mode, every 16th rising edge100 = Capture mode, every 4th rising edge011 = Capture mode, every rising edge010 = Capture mode, every falling edge001 = Capture mode, every edge (rising and falling) � ICI<1:0> bits do not control interrupt generation
for this mode000 = Input capture module turned off
Note 1: RPINRx (ICxRx) must be configured to an available RPn pin. For more information, see Section 9.4 �Peripheral Pin Select�.
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13.0 OUTPUT COMPARE
13.1 Setup for Single Output Pulse Generation
When the OCM control bits (OCxCON<2:0>) are set to�100�, the selected output compare channel initializesthe OCx pin to the low state and generates a singleoutput pulse.To generate a single output pulse, the following stepsare required (these steps assume the timer source isinitially turned off, but this is not a requirement for themodule operation):1. Determine the instruction clock cycle time. Take
into account the frequency of the external clockto the timer source (if one is used) and the timerprescaler settings.
2. Calculate time to the rising edge of the outputpulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulsebased on the desired pulse width and the time tothe rising edge of the pulse.
4. Write the values computed in steps 2 and 3above into the Output Compare x register,OCxR, and the Output Compare x Secondaryregister, OCxRS, respectively.
5. Set Timer Period register, PRy, to value equal toor greater than value in OCxRS, the OutputCompare x Secondary register.
6. Set the OCM bits to �100� and the OCTSEL(OCxCON<3>) bit to the desired timer source.The OCx pin state will now be driven low.
7. Set the TON (TyCON<15>) bit to �1�, whichenables the compare time base to count.
8. Upon the first match between TMRy and OCxR,the OCx pin will be driven high.
9. When the incrementing timer, TMRy, matches theOutput Compare x Secondary register, OCxRS,the second and trailing edge (high-to-low) of thepulse is driven onto the OCx pin. No additionalpulses are driven onto the OCx pin and it remainsat low. As a result of the second compare matchevent, the OCxIF interrupt flag bit is set, whichwill result in an interrupt if it is enabled, by set-ting the OCxIE bit. For further information onperipheral interrupts, refer to Section 6.0�Interrupt Controller�.
10. To initiate another single pulse output, change theTimer and Compare register settings, if needed,and then issue a write to set the OCM bits to �100�.Disabling and re-enabling of the timer and clear-ing the TMRy register are not required, but maybe advantageous for defining a pulse from aknown event time boundary.
The output compare module does not have to be dis-abled after the falling edge of the output pulse. Anotherpulse can be initiated by rewriting the value of theOCxCON register.
13.2 Setup for Continuous Output Pulse Generation
When the OCM control bits (OCxCON<2:0>) are set to�101�, the selected output compare channel initializesthe OCx pin to the low state and generates outputpulses on each and every compare match event.For the user to configure the module for the generationof a continuous stream of output pulses, the followingsteps are required (these steps assume the timersource is initially turned off, but this is not a requirementfor the module operation):1. Determine the instruction clock cycle time. Take
into account the frequency of the external clockto the timer source (if one is used) and the timerprescaler settings.
2. Calculate time to the rising edge of the outputpulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulsebased on the desired pulse width and the time tothe rising edge of the pulse.
4. Write the values computed in step 2 and 3 aboveinto the Output Compare x register, OCxR, andthe Output Compare x Secondary register,OCxRS, respectively.
5. Set Timer Period register, PRy, to value equal toor greater than value in OCxRS.
6. Set the OCM bits to �101� and the OCTSEL bit tothe desired timer source. The OCx pin state willnow be driven low.
7. Enable the compare time base by setting the TON(TyCON<15>) bit to �1�.
8. Upon the first match between TMRy and OCxR,the OCx pin will be driven high.
9. When the compare time base, TMRy, matches theOCxRS, the second and trailing edge (high-to-low)of the pulse is driven onto the OCx pin.
10. As a result of the second compare match event,the OCxIF interrupt flag bit set.
11. When the compare time base and the value in itsrespective Timer Period register match, the TMRyregister resets to 0x0000 and resumes counting.
12. Steps 8 through 11 are repeated and a continuousstream of pulses is generated indefinitely. TheOCxIF flag is set on each OCxRS/TMRy comparematch event.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 16. Output Compare�(DS39706).
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 127
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13.3 Pulse-Width Modulation ModeThe following steps should be taken when configuringthe output compare module for PWM operation:
1. Set the PWM period by writing to the selectedTimer Period register (PRy).
2. Set the PWM duty cycle by writing to the OCxRSregister.
3. Write the OCxR register with the initial duty cycle.4. Enable interrupts, if required, for the timer and
output compare modules. The output compareinterrupt is required for PWM Fault pin utilization.
5. Configure the output compare module for one oftwo PWM Operation modes by writing to theOutput Compare Mode bits, OCM<2:0>(OCxCON<2:0>).
6. Set the TMRy prescale value and enable the timebase by setting TON (TxCON<15>) = 1.
13.3.1 PWM PERIODThe PWM period is specified by writing to PRy, theTimer Period register. The PWM period can becalculated using Equation 13-1.
EQUATION 13-1: CALCULATING THE PWM PERIOD(1)
13.3.2 PWM DUTY CYCLEThe PWM duty cycle is specified by writing to theOCxRS register. The OCxRS register can be written toat any time, but the duty cycle value is not latched intoOCxR until a match between PRy and TMRy occurs(i.e., the period is complete). This provides a doublebuffer for the PWM duty cycle and is essential for glitch-less PWM operation. In the PWM mode, OCxR is aread-only register.
Some important boundary parameters of the PWM dutycycle include:
� If the Output Compare x register, OCxR, is loaded with 0000h, the OCx pin will remain low (0% duty cycle).
� If OCxR is greater than PRy (Timer Period register), the pin will remain high (100% duty cycle).
� If OCxR is equal to PRy, the OCx pin will be low for one time base count value and high for all other count values.
See Example 13-1 for PWM mode timing details.Table 13-1 shows example PWM frequencies andresolutions for a device operating at 10 MIPS.
EQUATION 13-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
Note: This peripheral contains input and outputfunctions that may need to be configuredby the peripheral pin select. SeeSection 9.4 �Peripheral Pin Select� formore information.
Note: The OCxR register should be initializedbefore the output compare module is firstenabled. The OCxR register becomes aRead-Only Duty Cycle register when themodule is operated in the PWM modes.The value held in OCxR will become thePWM duty cycle for the first PWM period.The contents of the Output Compare xSecondary register, OCxRS, will not betransferred into OCxR until a time baseperiod match occurs.
Note: A PRy value of N will produce a PWMperiod of N + 1 time base count cycles. Forexample, a value of 7 written into the PRyregister will yield a period consisting of8 time base cycles.
PWM Period = [(PRy) + 1] � TCY � (Timer Prescale Value)
PWM Frequency = 1/[PWM Period]where:
Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
( )Maximum PWM Resolution (bits) =
FCY FPWM � (Timer Prescale Value)
log10
log10(2)bits
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
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EXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
TABLE 13-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001FhResolution (bits) 16 16 15 12 10 7 5Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001FhResolution (bits) 16 16 15 12 10 7 5Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.
TCY = 2 * Tosc = 62.5 nsPWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 μsPWM Period = (PR2 + 1) � TCY � (Timer 2 Prescale Value)19.2 μs = (PR2 + 1) � 62.5 ns � 1 PR2 = 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:PWM Resolution = log10(FCY/FPWM)/log102) bits
= (log10(16 MHz/52.08 kHz)/log102) bits= 8.3 bits
Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 129
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FIGURE 13-1: OUTPUT COMPARE MODULE BLOCK DIAGRAMComparator
OutputLogic
QSR
OCM2:OCM0
Output Enable
OCx(1)
Set Flag bitOCxIF(1)
OCxRS(1)
Mode Select(4)
3
Note 1: Where �x� is shown, reference is made to the registers associated with the respective output compare channels 1 through 5.
2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time
bases associated with the module.4: This peripheral�s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 9.4
�Peripheral Pin Select� section for more information.
OCTSEL 0 1
16 16
OCFA or OCFB(2)
TMR register inputsfrom time bases(see Note 3).
Period match signalsfrom time bases(see Note 3).
0 1
OCxR(1)
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13.4 Output Compare RegisterREGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0� � OCSIDL � � � � �
bit 15 bit 8
U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0� � � OCFLT OCTSEL OCM2(1) OCM1(1) OCM0(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0�bit 13 OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x will halt in CPU Idle mode0 = Output Compare x will continue to operate in CPU Idle mode
bit 12-5 Unimplemented: Read as �0�bit 4 OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3 OCTSEL: Output Compare x Timer Select bit1 = Timer3 is the clock source for Output Compare x0 = Timer2 is the clock source for Output Compare xRefer to the device data sheet for specific time bases available to the output compare module.
bit 2-0 OCM2:OCM0: Output Compare x Mode Select bits(1)
111 = PWM mode on OCx, Fault pin, OCFx, enabled(2)
110 = PWM mode on OCx, Fault pin, OCFx, disabled(2)
101 = Initialize OCx pin low, generate continuous output pulses on OCx pin100 = Initialize OCx pin low, generate single output pulse on OCx pin011 = Compare event toggles OCx pin010 = Initialize OCx pin high, compare event forces OCx pin low001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled
Note 1: RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 9.4 �Peripheral Pin Select�.
2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 131
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NOTES:DS39881C-page 132 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
14.0 SERIAL PERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) module is asynchronous serial interface useful for communicatingwith other peripheral or microcontroller devices. Theseperipheral devices may be serial EEPROMs, shift reg-isters, display drivers, A/D Converters, etc. The SPImodule is compatible with Motorola�s SPI and SIOPinterfaces.
The module supports operation in two buffer modes. InStandard mode, data is shifted through a single serialbuffer. In Enhanced Buffer mode, data is shiftedthrough an 8-level FIFO buffer.
The module also supports a basic framed SPI protocolwhile operating in either Master or Slave mode. A totalof four framed SPI configurations are supported.
The SPI serial interface consists of four pins:
� SDIx: Serial Data Input� SDOx: Serial Data Output� SCKx: Shift Clock Input or Output� SSx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using 2,3 or 4 pins. In the 3-pin mode, SSx is not used. In the2-pin mode, both SDOx and SSx are not used.
Block diagrams of the module in Standard andEnhanced modes are shown in Figure 14-1 andFigure 14-2.
Depending on the pin count, devices of thePIC24FJ64GA004 family offer one or two SPI moduleson a single device.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 23. Serial Peripheral Interface(SPI)� (DS39699)
Note: Do not perform read-modify-write opera-tions (such as bit-oriented instructions) onthe SPIxBUF register in either Standard orEnhanced Buffer mode.
Note: In this section, the SPI modules arereferred to together as SPIx or separatelyas SPI1 and SPI2. Special Function Reg-isters will follow a similar notation. Forexample, SPIxCON1 or SPIxCON2 refersto the control register for the SPI1 or SPI2module.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 133
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To set up the SPI module for the Standard Master modeof operation:1. If using interrupts:a) Clear the SPIxIF bit in the respective IFSx
register.b) Set the SPIxIE bit in the respective IECx
register.c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.2. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).4. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will startas soon as data is written to the SPIxBUFregister.
To set up the SPI module for the Standard Slave modeof operation:
1. Clear the SPIxBUF register.2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSxregister.
b) Set the SPIxIE bit in the respective IECxregister.
c) Write the SPIxIP bits in the respective IPCxregister to set the interrupt priority.
3. Write the desired settings to the SPIxCON1and SPIxCON2 registers with MSTEN(SPIxCON1<5>) = 0.
4. Clear the SMP bit.5. If the CKE bit is set, then the SSEN bit
(SPIxCON1<7>) must be set to enable the SSxpin.
6. Clear the SPIROV bit (SPIxSTAT<6>).7. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 14-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
Internal Data Bus
SDIx
SDOx
SSx/FSYNCx
SCKx
SPIxSRbit 0
Shift Control
EdgeSelect
FCYPrimary1:1/4/16/64
Enable
Prescaler
SyncClock
Control
SPIxBUF
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
SecondaryPrescaler
1:1 to 1:8
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To set up the SPI module for the Enhanced BufferMaster mode of operation:1. If using interrupts:a) Clear the SPIxIF bit in the respective IFSx
register.b) Set the SPIxIE bit in the respective IECx
register.c) Write the SPIxIP bits in the respective IPCx
register.2. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).5. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).6. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will startas soon as data is written to the SPIxBUFregister.
To set up the SPI module for the Enhanced BufferSlave mode of operation:
1. Clear the SPIxBUF register.2. If using interrupts:
� Clear the SPIxIF bit in the respective IFSx register.
� Set the SPIxIE bit in the respective IECx register.
� Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 andSPIxCON2 registers with MSTEN(SPIxCON1<5>) = 0.
4. Clear the SMP bit.5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.6. Clear the SPIROV bit (SPIxSTAT<6>).7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).8. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 14-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal Data Bus
SDIx
SDOx
SSx/FSYNCx
SCKx
SPIxSR
bit0
Shift Control
EdgeSelect
FCYPrimary1:1/4/16/64
Enable
PrescalerSecondaryPrescaler
1:1 to 1:8
SyncClock
Control
SPIxBUF
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
8-Level FIFOTransmit Buffer
8-Level FIFOReceive Buffer
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 135
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REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTERR/W-0 U-0 R/W-0 U-0 U-0 R-0 R-0 R-0SPIEN(1) � SPISIDL � � SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPIx Enable bit(1)
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins0 = Disables module
bit 14 Unimplemented: Read as �0�bit 13 SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode0 = Continues module operation in Idle mode
bit 12-11 Unimplemented: Read as �0�bit 10-8 SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:Number of SPI transfers pending.Slave mode:Number of SPI transfers unread.
bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)1 = SPIx Shift register is empty and ready to send or receive0 = SPIx Shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit1 = A new byte/word is completely received and discarded. The user software has not read the previous
data in the SPIxBUF register.0 = No overflow has occurred
bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)1 = Receive FIFO is empty 0 = Receive FIFO is not empty
bit 4-2 SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set)110 = Interrupt when last bit is shifted into SPIxSR; as a result, the TX FIFO is empty101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set)010 = Interrupt when SPIx receive buffer is 3/4 or more full001 = Interrupt when data is available in receive buffer (SRMPT bit is set)000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
(SRXMPT bit is set)
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 �Peripheral Pin Select� for more information.
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bit 1 SPITBF: SPIx Transmit Buffer Full Status bit1 = Transmit not yet started, SPIxTXB is full0 = Transmit started, SPIxTXB is emptyIn Standard Buffer mode:Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.In Enhanced Buffer mode:Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit1 = Receive complete, SPIxRXB is full0 = Receive is not complete, SPIxRXB is emptyIn Standard Buffer mode:Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.In Enhanced Buffer mode:Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unreadbuffer location.Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.
REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 �Peripheral Pin Select� for more information.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 137
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REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0� � � DISSCK(1) DISSDO(2) MODE16 SMP CKE(3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0SSEN(4) CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0�bit 12 DISSCK: Disables SCKx pin bit (SPI Master modes only)(1)
1 = Internal SPI clock is disabled; pin functions as I/O0 = Internal SPI clock is enabled
bit 11 DISSDO: Disables SDOx pin bit(2)
1 = SDOx pin is not used by module; pin functions as I/O0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit1 = Communication is word-wide (16 bits)0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bitMaster mode:1 = Input data sampled at end of data output time0 = Input data sampled at middle of data output timeSlave mode:SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)(4)
1 = SSx pin used for Slave mode0 = SSx pin not used by module; pin controlled by port function
bit 6 CKP: Clock Polarity Select bit1 = Idle state for clock is a high level; active state is a low level0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit1 = Master mode0 = Slave mode
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to �0� for the Framed SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
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bit 4-2 SPRE2:SPRE0: Secondary Prescale bits (Master mode)111 = Secondary prescale 1:1110 = Secondary prescale 2:1...000 = Secondary prescale 8:1
bit 1-0 PPRE1:PPRE0: Primary Prescale bits (Master mode)11 = Primary prescale 1:110 = Primary prescale 4:101 = Primary prescale 16:100 = Primary prescale 64:1
REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to �0� for the Framed SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0FRMEN SPIFSD SPIFPOL � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0� � � � � � SPIFE SPIBEN
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPIx Support bit1 = Framed SPIx support enabled0 = Framed SPIx support disabled
bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit1 = Frame sync pulse input (slave)0 = Frame sync pulse output (master)
bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)1 = Frame sync pulse is active-high0 = Frame sync pulse is active-low
bit 12-2 Unimplemented: Read as �0�bit 1 SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock0 = Frame sync pulse precedes first bit clock
bit 0 SPIBEN: Enhanced Buffer Enable bit1 = Enhanced Buffer enabled0 = Enhanced Buffer disabled (Legacy mode)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 139
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FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE)FIGURE 14-4: SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Serial Receive Buffer(SPIxRXB)(2)
Shift Register(SPIxSR)
LSbMSb
SDIx
SDOx
PROCESSOR 2 (SPI Slave)
SCKx
SSx(1)
Serial Transmit Buffer(SPIxTXB)(2)
Serial Receive Buffer(SPIxRXB)(2)
Shift Register(SPIxSR)
MSb LSb
SDOx
SDIx
PROCESSOR 1 (SPI Master)
Serial Clock
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SCKx
Serial Transmit Buffer(SPIxTXB)(2)
MSTEN (SPIxCON1<5>) = 1)
SPIx Buffer(SPIxBUF)(2)
SPIx Buffer(SPIxBUF)(2)
Shift Register(SPIxSR)
LSbMSb
SDIx
SDOx
PROCESSOR 2 (SPI Enhanced Buffer Slave)
SCKx
SSx(1)
Shift Register(SPIxSR)
MSb LSb
SDOx
SDIx
PROCESSOR 1 (SPI Enhanced Buffer Master)
Serial Clock
SSEN (SPIxCON1<7>) = 1,
Note 1: Using the SSx pin in Slave mode of operation is optional.2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SSx
SCKx
8-Level FIFO Buffer
MSTEN (SPIxCON1<5>) = 1 and
SPIx Buffer(SPIxBUF)(2)
8-Level FIFO Buffer
SPIx Buffer(SPIxBUF)(2)
SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 andSPIBEN (SPIxCON2<0>) = 1
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FIGURE 14-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAMFIGURE 14-6: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame SyncPulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Slave, Frame Slave)
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame SyncPulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
SPI Master, Frame Slave)
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame Sync.Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Slave, Frame Slave)
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame SyncPulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Master, Frame Slave)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 141
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EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)TABLE 14-1: SAMPLE SCK FREQUENCIES(1,2)
FCY = 16 MHzSecondary Prescaler Settings
1:1 2:1 4:1 6:1 8:1
Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 20004:1 4000 2000 1000 667 500
16:1 1000 500 250 167 12564:1 250 125 63 42 31
FCY = 5 MHz
Primary Prescaler Settings 1:1 5000 2500 1250 833 6254:1 1250 625 313 208 156
16:1 313 156 78 52 3964:1 78 39 20 13 10
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.2: SCKx frequencies shown in kHz.
Primary Prescaler * Secondary Prescaler
FCY FSCK =
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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15.0 INTER-INTEGRATED CIRCUIT (I2C�)
The Inter-Integrated Circuit� (I2C�) module is a serialinterface useful for communicating with other periph-eral or microcontroller devices. These peripheraldevices may be serial EEPROMs, display drivers, A/DConverters, etc.
The I2C module supports these features:
� Independent master and slave logic� 7-bit and 10-bit device addresses� General call address, as defined in the I2C protocol� Clock stretching to provide delays for the
processor to respond to a slave data request� Both 100 kHz and 400 kHz bus specifications.� Configurable address masking� Multi-Master modes to prevent loss of messages
in arbitration� Bus Repeater mode, allowing the acceptance of
all messages as a slave regardless of the address� Automatic SCL
A block diagram of the module is shown in Figure 15-1.
15.1 Peripheral Remapping OptionsThe I2C modules are tied to fixed pin assignments, andcannot be reassigned to alternate pins using peripheralpin select. To allow some flexibility with peripheralmultiplexing, the I2C1 module in all devices, can bereassigned to the alternate pins, designated as ASCL1and ASDA1 during device configuration.
Pin assignment is controlled by the I2C1SEL Configu-ration bit; programming this bit (= 0) multiplexes themodule to the ASCL1 and ASDA1 pins.
15.2 Communicating as a Master in a Single Master Environment
The details of sending a message in Master modedepends on the communications protocol for the devicebeing communicated with. Typically, the sequence ofevents is as follows:
1. Assert a Start condition on SDAx and SCLx.2. Send the I2C device address byte to the slave
with a write indication.3. Wait for and verify an Acknowledge from the
slave.4. Send the first data byte (sometimes known as
the command) to the slave.5. Wait for and verify an Acknowledge from the
slave.6. Send the serial memory address low byte to the
slave.7. Repeat steps 4 and 5 until all data bytes are
sent.8. Assert a Repeated Start condition on SDAx and
SCLx.9. Send the device address byte to the slave with
a read indication.10. Wait for and verify an Acknowledge from the
slave.11. Enable master reception to receive serial
memory data.12. Generate an ACK or NACK condition at the end
of a received byte of data.13. Generate a Stop condition on SDAx and SCLx.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 24. Inter-Integrated Circuit(I2C�)� (DS39702).
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 143
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FIGURE 15-1: I2C� BLOCK DIAGRAMI2CxRCV
InternalData Bus
SCLx
SDAx
Shift
Match Detect
I2CxADD
Start and Stop Bit Detect
Clock
Address Match
ClockStretching
I2CxTRN
LSBShift Clock
BRG Down Counter
ReloadControl
TCY/2
Start and StopBit Generation
AcknowledgeGeneration
CollisionDetect
I2CxCON
I2CxSTAT
Con
trol L
ogic
Read
LSB
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2CxMSK
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15.3 Setting Baud Rate WhenOperating as a Bus MasterTo compute the Baud Rate Generator reload value, useEquation 15-1.
EQUATION 15-1: COMPUTING BAUD RATE RELOAD VALUE(1)
15.4 Slave Address MaskingThe I2CxMSK register (Register 15-3) designatesaddress bit positions as �don�t care� for both 7-Bit and10-Bit Addressing modes. Setting a particular bit loca-tion (= 1) in the I2CxMSK register causes the slavemodule to respond whether the corresponding addressbit value is a �0� or a �1�. For example, when I2CxMSKis set to �00100000�, the slave module will detect bothaddresses, �0000000� and �00100000�.
To enable address masking, the IPMI (IntelligentPeripheral Management Interface) must be disabled byclearing the IPMIEN bit (I2CxCON<11>).
TABLE 15-1: I2C� CLOCK RATES(1)
TABLE 15-2: I2C� RESERVED ADDRESSES(1)
I2CxBRG FCYFSCL------------ FCY
10 000 000, ,------------------------------�⎝ ⎠
⎛ ⎞ 1�=
FSCLFCY
I2CxBRG 1 FCY10 000 000, ,------------------------------+ +
----------------------------------------------------------------------=
or
Note 1: Based on FCY = FOSC/2; Doze mode andPLL are disabled.
Note: As a result of changes in the I2C� proto-col, the addresses in Table 15-2 arereserved and will not be Acknowledged inSlave mode. This includes any addressmask settings that include any of theseaddresses.
RequiredSystem
FSCLFCY
I2CxBRG Value ActualFSCL(Decimal) (Hexadecimal)
100 kHz 16 MHz 157 9D 100 kHz100 kHz 8 MHz 78 4E 100 kHz100 kHz 4 MHz 39 27 99 kHz400 kHz 16 MHz 37 25 404 kHz400 kHz 8 MHz 18 12 404 kHz400 kHz 4 MHz 9 9 385 kHz400 kHz 2 MHz 4 4 385 kHz1 MHz 16 MHz 13 D 1.026 MHz1 MHz 8 MHz 6 6 1.026 MHz1 MHz 4 MHz 3 3 0.909 MHz
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Slave Address
R/W Bit Description
0000 000 0 General Call Address(2)
0000 000 1 Start Byte
0000 001 x Cbus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte(3)
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.2: Address will be Acknowledged only if GCEN = 1.3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 145
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REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0I2CEN � I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HCGCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins0 = Disables I2Cx module. All I2C� pins are controlled by port functions.
bit 14 Unimplemented: Read as �0�bit 13 I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode0 = Continues module operation in Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C Slave)1 = Releases SCLx clock0 = Holds SCLx clock low (clock stretch)If STREN = 1:Bit is R/W (i.e., software may write �0� to initiate stretch and write �1� to release clock). Hardware clear atbeginning of slave transmission. Hardware clear at end of slave reception.If STREN = 0:Bit is R/S (i.e., software may only write �1� to release clock). Hardware clear at beginning of slave transmission.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit1 = IPMI Support mode is enabled; all addresses Acknowledged0 = IPMI mode is disabled
bit 10 A10M: 10-Bit Slave Addressing bit1 = I2CxADD is a 10-bit slave address0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit1 = Slew rate control disabled0 = Slew rate control enabled
bit 8 SMEN: SMBus Input Levels bit1 = Enables I/O pin thresholds compliant with SMBus specification0 = Disables SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)0 = General call address disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)Used in conjunction with SCLREL bit.1 = Enables software or receive clock stretching0 = Disables software or receive clock stretching
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bit 5 ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.)Value that will be transmitted when the software initiates an Acknowledge sequence.1 = Sends NACK during Acknowledge0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.)1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
clear at end of master Acknowledge sequence.0 = Acknowledge sequence not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.0 = Receives sequence not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.0 = Stop condition not in progress
bit 1 RSEN: Repeated Start Condition Enabled bit (when operating as I2C master)1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master
Repeated Start sequence.0 = Repeated Start condition not in progress
bit 0 SEN: Start Condition Enabled bit (when operating as I2C master)1 = Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.0 = Start condition not in progress
REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
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REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTERR-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSCACKSTAT TRSTAT � � � BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D/A P S R/W RBF TBFbit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable, Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last0 = ACK was detected lastHardware set or clear at end of Acknowledge.
bit 14 TRSTAT: Transmit Status bit (When operating as I2C� master. Applicable to master transmit operation.)1 = Master transmit is in progress (8 bits + ACK)0 = Master transmit is not in progressHardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as �0�bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation0 = No collisionHardware set at detection of bus collision.
bit 9 GCSTAT: General Call Status bit1 = General call address was received0 = General call address was not receivedHardware set when address matches general call address. Hardware clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit1 = 10-bit address was matched0 = 10-bit address was not matchedHardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7 IWCOL: Write Collision Detect bit1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collisionHardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: Receive Overflow Flag bit1 = A byte was received while the I2CxRCV register is still holding the previous byte0 = No overflowHardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D/A: Data/Address bit (when operating as I2C slave)1 = Indicates that the last byte received was data0 = Indicates that the last byte received was device addressHardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte.
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bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last0 = Stop bit was not detected lastHardware set or clear when Start, Repeated Start or Stop detected.
bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last0 = Start bit was not detected lastHardware set or clear when Start, Repeated Start or Stop detected.
bit 2 R/W: Read/Write Information bit (when operating as I2C slave)1 = Read � indicates data transfer is output from slave0 = Write � indicates data transfer is input to slaveHardware set or clear after reception of I2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full0 = Receive not complete, I2CxRCV is emptyHardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit1 = Transmit in progress, I2CxTRN is full0 = Transmit complete, I2CxTRN is emptyHardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
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REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0� � � � � � AMSK9 AMSK8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as �0�bit 9-0 AMSK9:AMSK0: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match not required in this position0 = Disable masking for bit x; bit match required in this position
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16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
The Universal Asynchronous Receiver Transmitter(UART) module is one of the serial I/O modules availablein the PIC24F device family. The UART is a full-duplexasynchronous system that can communicate withperipheral devices, such as personal computers, LIN,RS-232 and RS-485 interfaces. The module also sup-ports a hardware flow control option with the UxCTS andUxRTS pins and also includes an IrDA® encoder anddecoder.
The primary features of the UART module are:
� Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX Pins
� Even, Odd or No Parity Options (for 8-bit data)� One or Two Stop bits� Hardware Flow Control Option with UxCTS and
UxRTS Pins
� Fully Integrated Baud Rate Generator with 16-Bit Prescaler
� Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS
� 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer
� 4-Deep FIFO Receive Data Buffer� Parity, Framing and Buffer Overrun Error Detection� Support for 9-bit mode with Address Detect
(9th bit = 1)� Transmit and Receive Interrupts� Loopback mode for Diagnostic Support� Support for Sync and Break Characters� Supports Automatic Baud Rate Detection� IrDA Encoder and Decoder Logic� 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown inFigure 16-1. The UART module consists of these keyimportant hardware elements:
� Baud Rate Generator� Asynchronous Transmitter� Asynchronous Receiver
FIGURE 16-1: UART SIMPLIFIED BLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 21. UART� (DS39708).
UxRX
IrDA®
Hardware Flow Control
UARTx Receiver
UARTx Transmitter UxTX
UxCTSUxRTS
BCLKx
Baud Rate Generator
Note: This peripheral�s inputs and outputs must be assigned to an available RPn pin before use. Pleasesee Section 9.4 �Peripheral Pin Select� for more information.
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16.1 UART Baud Rate Generator (BRG)The UART module includes a dedicated 16-bit BaudRate Generator. The UxBRG register controls theperiod of a free-running, 16-bit timer. Equation 16-1shows the formula for computation of the baud ratewith BRGH = 0.EQUATION 16-1: UART BAUD RATE WITH BRGH = 0(1)
Example 16-1 shows the calculation of the baud rateerror for the following conditions:
� FCY = 4 MHz � Desired Baud Rate = 9600
The maximum baud rate (BRGH = 0) possible isFCY/16 (for UxBRG = 0) and the minimum baud ratepossible is FCY/(16 * 65536).
Equation 16-2 shows the formula for computation ofthe baud rate with BRGH = 1.
EQUATION 16-2: UART BAUD RATE WITH BRGH = 1(1)
The maximum baud rate (BRGH = 1) possible is FCY/4(for UxBRG = 0) and the minimum baud rate possibleis FCY/(4 * 65536).
Writing a new value to the UxBRG register causes theBRG timer to be reset (cleared). This ensures the BRGdoes not wait for a timer overflow before generating thenew baud rate.
EXAMPLE 16-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Baud Rate = FCY
16 � (UxBRG + 1)
FCY16 � Baud Rate
UxBRG = � 1
Baud Rate = FCY
4 � (UxBRG + 1)
FCY4 � Baud Rate
UxBRG = � 1
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Desired Baud Rate = FCY/(16 (UxBRG + 1)) Solving for UxBRG value:
UxBRG = ((FCY/Desired Baud Rate)/16) � 1UxBRG = ((4000000/9600)/16) � 1 UxBRG = 25
Calculated Baud Rate= 4000000/(16 (25 + 1)) = 9615
Error = (Calculated Baud Rate � Desired Baud Rate)Desired Baud Rate
= (9615 � 9600)/9600 = 0.16%
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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16.2 Transmitting in 8-Bit Data Mode1. Set up the UART:a) Write appropriate values for data, parity andStop bits.
b) Write appropriate baud rate value to theUxBRG register.
c) Set up transmit and receive interrupt enableand priority bits.
2. Enable the UART.3. Set the UTXEN bit (causes a transmit interrupt
2 cycles after being set).4. Write data byte to lower byte of UxTXREG word.
The value will be immediately transferred to theTransmit Shift Register (TSR), and the serial bitstream will start shifting out with next rising edgeof the baud clock.
5. Alternately, the data byte may be transferredwhile UTXEN = 0, and then the user may setUTXEN. This will cause the serial bit stream tobegin immediately because the baud clock willstart from a cleared state.
6. A transmit interrupt will be generated as perinterrupt control bit, UTXISELx.
16.3 Transmitting in 9-Bit Data Mode1. Set up the UART (as described in Section 16.2
�Transmitting in 8-Bit Data Mode�).2. Enable the UART.3. Set the UTXEN bit (causes a transmit interrupt
2 cycles after being set).4. Write UxTXREG as a 16-bit value only.5. A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. Serial bit stream willstart shifting out with the first rising edge of thebaud clock.
6. A transmit interrupt will be generated as per thesetting of control bit, UTXISELx.
16.4 Break and Sync Transmit Sequence
The following sequence will send a message frameheader made up of a Break, followed by an auto-baudSync byte.
1. Configure the UART for the desired mode.2. Set UTXEN and UTXBRK � sets up the Break
character.3. Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).4. Write �55h� to UxTXREG � loads the Sync
character into the transmit FIFO.5. After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character nowtransmits.
16.5 Receiving in 8-Bit or 9-Bit Data Mode
1. Set up the UART (as described in Section 16.2�Transmitting in 8-Bit Data Mode�).
2. Enable the UART.3. A receive interrupt will be generated when one
or more data characters have been received asper interrupt control bit, URXISELx.
4. Read the OERR bit to determine if an overrunerror has occurred. The OERR bit must be resetin software.
5. Read UxRXREG.
The act of reading the UxRXREG character will movethe next character to the top of the receive FIFO,including a new set of PERR and FERR values.
16.6 Operation of UxCTS and UxRTS Control Pins
UARTx Clear to Send (UxCTS) and Request to Send(UxRTS) are the two hardware controlled pins that areassociated with the UART module. These two pinsallow the UART to operate in Simplex and Flow Controlmode. They are implemented to control the transmis-sion and reception between the Data TerminalEquipment (DTE). The UEN<1:0> bits in the UxMODEregister configure these pins.
16.7 Infrared SupportThe UART module provides two types of infrared UARTsupport: one is the IrDA clock output to support exter-nal IrDA encoder and decoder device (legacy modulesupport), and the other is the full implementation of theIrDA encoder and decoder. Note that because the IrDAmodes require a 16x baud clock, they will only workwhen the BRGH bit (UxMODE<3>) is �0�.
16.7.1 EXTERNAL IrDA SUPPORT � IrDA CLOCK OUTPUT
To support external IrDA encoder and decoder devices,the BCLKx pin (same as the UxRTS pin) can beconfigured to generate the 16x baud clock. WithUEN<1:0> = 11, the BCLKx pin will output the 16xbaud clock if the UART module is enabled. It can beused to support the IrDA codec chip.
16.7.2 BUILT-IN IrDA ENCODER AND DECODER
The UART has full implementation of the IrDA encoderand decoder as part of the UART module. The built-inIrDA encoder and decoder functionality is enabledusing the IREN bit (UxMODE<12>). When enabled(IREN = 1), the receive pin (UxRX) acts as the inputfrom the infrared receiver. The transmit pin (UxTX) actsas the output to the infrared transmitter.
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REGISTER 16-1: UxMODE: UARTx MODE REGISTERR/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(3) R/W-0(3)
UARTEN(1) � USIDL IREN(2) RTSMD � UEN1 UEN0bit 15 bit 8
R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimalbit 14 Unimplemented: Read as �0�bit 13 USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder enabled0 = IrDA encoder and decoder disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit1 = UxRTS pin in Simplex mode0 = UxRTS pin in Flow Control mode
bit 10 Unimplemented: Read as �0�bit 9-8 UEN1:UEN0: UARTx Enable bits(3)
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT
latches
bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in
hardware on following rising edge0 = No wake-up enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit1 = Enable Loopback mode0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit1 = Enable baud rate measurement on the next character � requires reception of a Sync field (55h);
cleared in hardware upon completion0 = Baud rate measurement disabled or completed
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).3: Bit availability depends on pin availability.
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bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is �0�0 = UxRX Idle state is �1�
bit 3 BRGH: High Baud Rate Enable bit1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL1:PDSEL0: Parity and Data Selection bits11 = 9-bit data, no parity10 = 8-bit data, odd parity01 = 8-bit data, even parity00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit1 = Two Stop bits0 = One Stop bit
REGISTER 16-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).3: Bit availability depends on pin availability.
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REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTERR/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1UTXISEL1 UTXINV UTXISEL0 � UTXBRK UTXEN(1) UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
transmit buffer becomes empty01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit
If IREN = 0:1 = UxTX Idle �0�0 = UxTX Idle �1�If IREN = 1:1 = UxTX Idle �1�0 = UxTX Idle �0�
bit 12 Unimplemented: Read as �0�bit 11 UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission � Start bit, followed by twelve �0� bits, followed by Stop bit;cleared by hardware upon completion
0 = Sync Break transmission disabled or completedbit 10 UTXEN: Transmit Enable bit(1)
1 = Transmit enabled, UxTX pin controlled by UARTx0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by
the PORT register.bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer.
Receive buffer has one or more characters.
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
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bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.0 = Address Detect mode disabled
bit 4 RIDLE: Receiver Idle bit (read-only)1 = Receiver is Idle0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)1 = Parity error has been detected for the current character (character at the top of the receive FIFO)0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)1 = Framing error has been detected for the current character (character at the top of the receive FIFO)0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)1 = Receive buffer has overflowed0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset
the receiver buffer and the RSR to the empty state)bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data; at least one more character can be read0 = Receive buffer is empty
REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
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REGISTER 16-3: UxTXREG: UARTx TRANSMIT REGISTERU-x U-x U-x U-x U-x U-x U-x W-x� � � � � � � UTX8
bit 15 bit 8
W-x W-x W-x W-x W-x W-x W-x W-xUTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as �0�bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode)bit 7-0 UTX7:UTX0: Data of the Transmitted Character bits
REGISTER 16-4: UxRXREG: UARTx RECEIVE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0� � � � � � � URX8
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0URX7 URX6 URX5 URX4 URX3 URX2 URX1 URX0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as �0�bit 8 URX8: Data of the Received Character bit (in 9-bit mode)bit 7-0 URX7:URX0: Data of the Received Character bits
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17.0 PARALLEL MASTER PORT (PMP)
The Parallel Master Port (PMP) module is a parallel8-bit I/O module, specifically designed to communicatewith a wide variety of parallel devices, such as commu-nication peripherals, LCDs, external memory devicesand microcontrollers. Because the interface to parallelperipherals varies significantly, the PMP is highlyconfigurable.
Key features of the PMP module include:
� Up to 16 Programmable Address Lines� One Chip Select Line� Programmable Strobe Options:
- Individual Read and Write Strobes or;- Read/Write Strobe with Enable Strobe
� Address Auto-Increment/Auto-Decrement� Programmable Address/Data Multiplexing� Programmable Polarity on Control Signals� Legacy Parallel Slave Port Support� Enhanced Parallel Slave Support:
- Address Support- 4-Byte Deep Auto-Incrementing Buffer
� Programmable Wait States� Selectable Input Voltage Levels
FIGURE 17-1: PMP MODULE OVERVIEW
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 13. Parallel Master Port(PMP)� (DS39713).
Note: A number of the pins for the PMP are notpresent on PIC24FJ64GA004 devices.Refer to the specific device�s pinout todetermine which pins are available.
PMA<0>
PMBE
PMRD
PMWR
PMD<7:0>
PMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<10:2>
PMALL
PMALH
PMA<7:0>PMA<15:8>
EEPROM
Address BusData BusControl Lines
PIC24F
LCD FIFOMicrocontroller
8-Bit Data
Up to 11-Bit Address
Parallel Master Port
Buffer
Note 1: PMA<10:2> are not available on 28-pin devices.
(1)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 159
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REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTERR/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PMPEN � PSIDL ADRMUX1(1) ADRMUX0(1) PTBEEN PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0CSF1 CSF0 ALP � CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 PMPEN: Parallel Master Port Enable bit1 = PMP enabled0 = PMP disabled, no off-chip access performed
bit 14 Unimplemented: Read as �0�bit 13 PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1)
11 = Reserved10 = All 16 bits of address are multiplexed on PMD<7:0> pins01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
PMA<10:8>00 = Address and data appear on separate pins
bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)1 = PMBE port enabled0 = PMBE port disabled
bit 9 PTWREN: Write Enable Strobe Port Enable bit1 = PMWR/PMENB port enabled0 = PMWR/PMENB port disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit1 = PMRD/PMWR port enabled0 = PMRD/PMWR port disabled
bit 7-6 CSF1:CSF0: Chip Select Function bits11 = Reserved10 = PMCS1 functions as chip set01 = Reserved00 = Reserved
bit 5 ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)0 = Active-low (PMALL and PMALH)
bit 4 Unimplemented: Read as �0�bit 3 CS1P: Chip Select 1 Polarity bit(2)
1 = Active-high (PMCS1/PMCS1)0 = Active-low (PMCS1/PMCS1)
Note 1: PMA<10:2> are not available on 28-pin devices.2: These bits have no effect when their corresponding pins are used as address lines.
DS39881C-page 160 Preliminary © 2008 Microchip Technology Inc.
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bit 2 BEP: Byte Enable Polarity bit1 = Byte enable active-high (PMBE)0 = Byte enable active-low (PMBE)
bit 1 WRSP: Write Strobe Polarity bitFor Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):1 = Write strobe active-high (PMWR)0 = Write strobe active-low (PMWR)For Master Mode 1 (PMMODE<9:8> = 11):1 = Enable strobe active-high (PMENB)0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bitFor Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):1 = Read strobe active-high (PMRD)0 = Read strobe active-low (PMRD)For Master Mode 1 (PMMODE<9:8> = 11):1 = Read/write strobe active-high (PMRD/PMWR)0 = Read/write strobe active-low (PMRD/PMWR)
REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
Note 1: PMA<10:2> are not available on 28-pin devices.2: These bits have no effect when their corresponding pins are used as address lines.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 161
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REGISTER 17-2: PMMODE: Parallel Port Mode RegisterR-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 BUSY: Busy bit (Master mode only)1 = Port is busy (not useful when the processor stall is active)0 = Port is not busy
bit 14-13 IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)10 = No interrupt generated, processor stall activated01 = Interrupt generated at the end of the read/write cycle00 = No interrupt generated
bit 12-11 INCM1:INCM0: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only)10 = Decrement ADDR<10:0> by 1 every read/write cycle01 = Increment ADDR<10:0> by 1 every read/write cycle00 = No increment or decrement of address
bit 10 MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer
bit 9-8 MODE1:MODE0: Parallel Port Mode Select bits11 = Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)10 = Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)
bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1)
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY
bit 5-2 WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits1111 = Wait of additional 15 TCY...0001 = Wait of additional 1 TCY0000 = No additional wait cycles (operation forced into one TCY)
bit 1-0 WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1)
11 = Wait of 4 TCY10 = Wait of 3 TCY01 = Wait of 2 TCY00 = Wait of 1 TCY
Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
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REGISTER 17-3: PMADDR: PARALLEL PORT ADDRESS REGISTERU-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0� CS1 � � � ADDR<10:8>(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADDR<7:0>(1)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14 CS1: Chip Select 1 bit
1 = Chip select 1 is active0 = Chip select 1 is inactive
bit 13-11 Unimplemented: Read as �0�bit 10-0 ADDR10:ADDR0: Parallel Port Destination Address bits(1)
Note 1: PMA<10:2> are not available on 28-pin devices.
REGISTER 17-4: PMAEN: PARALLEL PORT ENABLE REGISTER
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0� PTEN14 � � � PTEN10(1) PTEN9(1) PTEN8(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PTEN7(1) PTEN6(1) PTEN5(1) PTEN4(1) PTEN3(1) PTEN2(1) PTEN1 PTEN0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14 PTEN14: PMCS1 Strobe Enable bit
1 = PMCS1 functions as chip select0 = PMCS1 pin functions as port I/O
bit 13-11 Unimplemented: Read as �0�bit 10-2 PTEN10:PTEN2: PMP Address Port Enable bits(1)
1 = PMA<10:2> function as PMP address lines0 = PMA<10:2> function as port I/O
bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL0 = PMA1 and PMA0 pads functions as port I/O
Note 1: PMA<10:2> are not available on 28-pin devices.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 163
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REGISTER 17-5: PMSTAT: PARALLEL PORT STATUS REGISTERR-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0IBF IBOV � � IB3F IB2F IB1F IB0F
bit 15 bit 8
R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1OBE OBUF � � OB3E OB2E OB1E OB0E
bit 7 bit 0
Legend: HS = Hardware Set bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software)0 = No overflow occurred
bit 13-12 Unimplemented: Read as �0�bit 11-8 IB3F:IB0F Input Buffer x Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)0 = Input buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software)0 = No underflow occurred
bit 5-4 Unimplemented: Read as �0�bit 3-0 OB3E:OB0E Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)0 = Output buffer contains data that has not been transmitted
DS39881C-page 164 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 17-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0� � � � � � RTSECSEL(1) PMPTTL
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as �0�bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin0 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers0 = PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 165
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FIGURE 17-2: LEGACY PARALLEL SLAVE PORT EXAMPLEFIGURE 17-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
TABLE 17-1: SLAVE MODE ADDRESS RESOLUTION
FIGURE 17-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT)
PMA<1:0> Output Register (Buffer) Input Register (Buffer)
00 PMDOUT1<7:0> (0) PMDIN1<7:0> (0)01 PMDOUT1<15:8> (1) PMDIN1<15:8> (1)10 PMDOUT2<7:0> (2) PMDIN2<7:0> (2)11 PMDOUT2<15:8> (3) PMDIN2<15:8> (3)
PMD<7:0>
PMRD
PMWR
Master Address BusData BusControl Lines
PMCS1
PMD<7:0>
PMRD
PMWR
PIC24F Slave
PMCS1
PMD<7:0>
PMRD
PMWR
Master
PMCS1
PMA<1:0>
Address BusData BusControl Lines
PMRD
PMWR
PIC24F Slave
PMCS1PMDOUT1L (0)PMDOUT1H (1)PMDOUT2L (2)PMDOUT2H (3)
PMDIN1L (0)PMDIN1H (1)PMDIN2L (2)PMDIN2H (3)
PMD<7:0> WriteAddressDecode
ReadAddressDecode
PMA<1:0>
PMRD
PMWR
PMD<7:0>
PMCS1
PMA<10:0>PIC24F
Address BusData BusControl Lines
DS39881C-page 166 Preliminary © 2008 Microchip Technology Inc.
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FIGURE 17-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READAND WRITE STROBES, SINGLE CHIP SELECT)
FIGURE 17-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT)
FIGURE 17-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PMRD
PMWR
PMD<7:0>
PMCS1
PMA<10:8>
PMALL
PMA<7:0>
PIC24F
Address BusMultiplexedData andAddress BusControl Lines
PMRD
PMWR
PMD<7:0>
PMCS1
PMALH
PMA<15:8>PIC24F
MultiplexedData andAddress BusControl Lines
PMALL
PMA<7:0>
PMD<7:0>
PMALH
D<7:0>
373 A<15:0>
D<7:0>
A<7:0>
373
PMRD
PMWR
OE WR
CE
PIC24F
Address BusData BusControl Lines
PMCS1
PMALL
A<15:8>
PMA<10:8>
D<7:0>
373 A<10:0>
D<7:0>
A<7:0>
PMRD
PMWR
OE WRCE
PIC24F
Address BusData BusControl Lines
PMCS1
PMALL
A<10:8>
PMD<7:0>
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 167
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FIGURE 17-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATIONFIGURE 17-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA)
FIGURE 17-11: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA)
FIGURE 17-12: LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
ALE
PMRDPMWR
RDWR
CS
PIC24F
Address BusData BusControl Lines
PMCS1PMALL
AD<7:0>
Parallel Peripheral
PMD<7:0>
PMA<n:0> A<n:0>
D<7:0>
PMRDPMWR
OE
WR
CE
PIC24F
Address BusData BusControl Lines
PMCS1
PMD<7:0>
Parallel EEPROM
PMA<n:0> A<n:1>
D<7:0>
PMRDPMWR
OEWR
CE
PIC24F
Address BusData BusControl Lines
PMCS1
PMD<7:0>
Parallel EEPROM
PMBE A0
PMRD/PMWR
D<7:0>
PIC24F
Address BusData BusControl Lines
PMA0R/WRS
E
LCD Controller
PMCS1
PM<7:0>
DS39881C-page 168 Preliminary © 2008 Microchip Technology Inc.
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18.0 REAL-TIME CLOCK AND CALENDAR (RTCC)
FIGURE 18-1: RTCC BLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 29. Real-Time Clock andCalendar (RTCC)� (DS39696).
RTCC Prescalers
RTCC Timer
Comparator
Compare Registers
Repeat Counter
YEAR
MTHDY
WKDYHR
MINSEC
ALMTHDY
ALWDHR
ALMINSECwith Masks
RTCC Interrupt Logic
RCFGCAL
ALCFGRPT
AlarmEvent
32.768 kHz Inputfrom SOSC Oscillator
0.5s
RTCC Clock Domain
Alarm Pulse
RTCC Interrupt
CPU Clock Domain
RTCVAL
ALRMVAL
RTCC Pin
RTCOE
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 169
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18.1 RTCC Module RegistersThe RTCC module registers are organized into threecategories:� RTCC Control Registers� RTCC Value Registers� Alarm Value Registers
18.1.1 REGISTER MAPPINGTo limit the register interface, the RTCC Timer andAlarm Time registers are accessed through corre-sponding register pointers. The RTCC Value registerwindow (RTCVALH and RTCVALL) uses the RTCPTRbits (RCFGCAL<9:8>) to select the desired Timerregister pair (see Table 18-1).
By writing the RTCVALH byte, the RTCC Pointer value,RTCPTR<1:0> bits, decrement by one until they reach�00�. Once they reach �00�, the MINUTES and SEC-ONDS value will be accessible through RTCVALH andRTCVALL until the pointer value is manually changed.
TABLE 18-1: RTCVAL REGISTER MAPPING
The Alarm Value register window (ALRMVALH andALRMVALL) uses the ALRMPTR bits(ALCFGRPT<9:8>) to select the desired Alarm registerpair (see Table 18-2).
By writing the ALRMVALH byte, the Alarm Pointervalue, ALRMPTR<1:0> bits, decrement by one untilthey reach �00�. Once they reach �00�, the ALRMMINand ALRMSEC value will be accessible throughALRMVALH and ALRMVALL until the pointer value ismanually changed.
TABLE 18-2: ALRMVAL REGISTER MAPPING
Considering that the 16-bit core does not distinguishbetween 8-bit and 16-bit read operations, the user mustbe aware that when reading either the ALRMVALH orALRMVALL bytes will decrement the ALRMPTR<1:0>value. The same applies to the RTCVALH or RTCVALLbytes with the RTCPTR<1:0> being decremented.
18.1.2 WRITE LOCKIn order to perform a write to any of the RTCC Timerregisters, the RTCWREN bit (RCFGCAL<13>) must beset (refer to Example 18-1).
EXAMPLE 18-1: SETTING THE RTCWREN BIT
RTCPTR<1:0>
RTCC Value Register Window
RTCVAL<15:8> RTCVAL<7:0>
00 MINUTES SECONDS01 WEEKDAY HOURS10 MONTH DAY11 � YEAR
ALRMPTR<1:0>
Alarm Value Register Window
ALRMVAL<15:8> ALRMVAL<7:0>
00 ALRMMIN ALRMSEC01 ALRMWD ALRMHR10 ALRMMNTH ALRMDAY11 � �
Note: This only applies to read operations andnot write operations.
Note: To avoid accidental writes to the timer, it isrecommended that the RTCWREN bit(RCFGCAL<13>) is kept clear at anyother time. For the RTCWREN bit to beset, there is only 1 instruction cycle timewindow allowed between the 55h/AAsequence and the setting of RTCWREN;therefore, it is recommended that codefollow the procedure in Example 18-1.
asm volatile("push w7");asm volatile("push w8");asm volatile("disi #5");asm volatile("mov #0x55, w7");asm volatile("mov w7, _NVMKEY");asm volatile("mov #0xAA, w8");asm volatile("mov w8, _NVMKEY");asm volatile("bset _RCFGCAL, #13"); //set the RTCWREN bitasm volatile("pop w8");asm volatile("pop w7");
DS39881C-page 170 Preliminary © 2008 Microchip Technology Inc.
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18.1.3 RTCC CONTROL REGISTERSREGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0RTCEN(2) � RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled0 = RTCC module is disabled
bit 14 Unimplemented: Read as �0�bit 13 RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the datacan be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripplebit 11 HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second0 = First half period of a second
bit 10 RTCOE: RTCC Output Enable bit1 = RTCC output enabled0 = RTCC output disabled
bit 9-8 RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bitsPoints to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL regis-ters; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches �00�.RTCVAL<15:8>:00 = MINUTES01 = WEEKDAY10 = MONTH11 = ReservedRTCVAL<7:0>:00 = SECONDS01 = HOURS10 = DAY11 = YEAR
Note 1: The RCFGCAL register is only affected by a POR.2: A write to the RTCEN bit is only allowed when RTCWREN = 1.3: This bit is read-only. It is cleared to �0� on a write to the lower half of the MINSEC register.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 171
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bit 7-0 CAL7:CAL0: RTC Drift Calibration bits01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute...01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute00000000 = No adjustment11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute...10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
Note 1: The RCFGCAL register is only affected by a POR.2: A write to the RTCEN bit is only allowed when RTCWREN = 1.3: This bit is read-only. It is cleared to �0� on a write to the lower half of the MINSEC register.
REGISTER 18-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0� � � � � � RTSECSEL(1) PMPTTL
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as �0�bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin0 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers0 = PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
DS39881C-page 172 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 18-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 ALRMEN: Alarm Enable bit1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10 AMASK3:AMASK0: Alarm Mask Configuration bits0000 = Every half second0001 = Every second0010 = Every 10 seconds0011 = Every minute0100 = Every 10 minutes0101 = Every hour0110 = Once a day0111 = Once a week1000 = Once a month1001 = Once a year (except when configured for February 29th, once every 4 years)101x = Reserved � do not use11xx = Reserved � do not use
bit 9-8 ALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bitsPoints to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches �00�.ALRMVAL<15:8>:00 = ALRMMIN01 = ALRMWD10 = ALRMMNTH11 = UnimplementedALRMVAL<7:0>:00 = ALRMSEC01 = ALRMHR10 = ALRMDAY11 = Unimplemented
bit 7-0 ARPT7:ARPT0: Alarm Repeat Counter Value bits11111111 = Alarm will repeat 255 more times...00000000 = Alarm will not repeatThe counter decrements on any alarm event. The counter is prevented from rolling over from 00h toFFh unless CHIME = 1.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 173
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18.1.4 RTCVAL REGISTER MAPPINGSREGISTER 18-4: YEAR: YEAR VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xYRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as �0�bit 7-4 YRTEN3:YRTEN0: Binary Coded Decimal Value of Year�s Tens Digit; Contains a value from 0 to 9bit 3-0 YRONE3:YRONE0: Binary Coded Decimal Value of Year�s Ones Digit; Contains a value from 0 to 9
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 18-5: MTHDY: MONTH AND DAY VALUE REGISTER(1)
U-0 U-0 U-0 R-x R-x R-x R-x R-x� � � MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� � DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0�bit 12 MTHTEN0: Binary Coded Decimal Value of Month�s Tens Digit; Contains a value of �0� or �1�bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month�s Ones Digit; Contains a value from 0 to 9bit 7-6 Unimplemented: Read as �0�bit 5-4 DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day�s Tens Digit; Contains a value from 0 to 3bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day�s Ones Digit; Contains a value from 0 to 9
Note 1: A write to this register is only allowed when RTCWREN = 1.
DS39881C-page 174 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 18-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x� � � � � WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� � HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as �0�bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6bit 7-6 Unimplemented: Read as �0�bit 5-4 HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour�s Tens Digit; Contains a value from 0 to 2bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour�s Ones Digit; Contains a value from 0 to 9
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 18-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute�s Tens Digit; Contains a value from 0 to 5bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute�s Ones Digit; Contains a value from 0 to 9bit 7 Unimplemented: Read as �0�bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second�s Tens Digit; Contains a value from 0 to 5bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second�s Ones Digit; Contains a value from 0 to 9
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 175
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18.1.5 ALRMVAL REGISTER MAPPINGSREGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x� � � MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� � DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as �0�bit 12 MTHTEN0: Binary Coded Decimal Value of Month�s Tens Digit; Contains a value of �0� or �1�bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month�s Ones Digit; Contains a value from 0 to 9bit 7-6 Unimplemented: Read as �0�bit 5-4 DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day�s Tens Digit; Contains a value from 0 to 3bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day�s Ones Digit; Contains a value from 0 to 9
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 18-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x� � � � � WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� � HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as �0�bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6bit 7-6 Unimplemented: Read as �0�bit 5-4 HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour�s Tens Digit; Contains a value from 0 to 2bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour�s Ones Digit; Contains a value from 0 to 9
Note 1: A write to this register is only allowed when RTCWREN = 1.
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18.2 CalibrationThe real-time crystal input can be calibrated using theperiodic auto-adjust feature. When properly calibrated,the RTCC can provide an error of less than 3 secondsper month. This is accomplished by finding the numberof error clock pulses and storing the value into thelower half of the RCFGCAL register. The 8-bit signedvalue loaded into the lower half of RCFGCAL is multi-plied by four and will be either added or subtracted fromthe RTCC timer, once every minute. Refer to the stepsbelow for RTCC calibration:
1. Using another timer resource on the device, theuser must find the error of the 32.768 kHzcrystal.
2. Once the error is known, it must be converted tothe number of error clock pulses per minute.
EQUATION 18-1:
3. a) If the oscillator is faster then ideal (negativeresult form step 2), the RCFGCAL register valueneeds to be negative. This causes the specifiednumber of clock pulses to be subtracted fromthe timer counter once every minute.
b) If the oscillator is slower then ideal (positiveresult from step 2) the RCFGCAL register valueneeds to be positive. This causes the specifiednumber of clock pulses to be subtracted fromthe timer counter once every minute.
4. Divide the number of error clocks per minute by4 to get the correct CAL value and load theRCFGCAL register with the correct value.
(Each 1-bit increment in CAL adds or subtracts4 pulses).
Writes to the lower half of the RCFGCAL registershould only occur when the timer is turned off, orimmediately after the rising edge of the seconds pulse.
REGISTER 18-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x� SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as �0�bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute�s Tens Digit; Contains a value from 0 to 5bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute�s Ones Digit; Contains a value from 0 to 9bit 7 Unimplemented: Read as �0�bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second�s Tens Digit; Contains a value from 0 to 5bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second�s Ones Digit; Contains a value from 0 to 9
(Ideal Frequency� � Measured Frequency) * 60 = Clocks per Minute
� Ideal frequency = 32,768 Hz
Note: It is up to the user to include in the errorvalue the initial error of the crystal, driftdue to temperature and drift due to crystalaging.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 177
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18.3 Alarm� Configurable from half second to one year� Enabled using the ALRMEN bit(ALCFGRPT<15>, Register 18-3)� One-time alarm and repeat alarm options
available
18.3.1 CONFIGURING THE ALARMThe alarm feature is enabled using the ALRMEN bit.This bit is cleared when an alarm is issued. Writes toALRMVAL should only take place when ALRMEN = 0.
As shown in Figure 18-2, the interval selection of thealarm is configured through the AMASK bits(ALCFGRPT<13:10>). These bits determine which andhow many digits of the alarm must match the clockvalue for the alarm to occur.
The alarm can also be configured to repeat based on apreconfigured interval. The amount of times this occursonce the alarm is enabled is stored in the ARPT bits,ARPT7:ARPT0 (ALCFGRPT<7:0>). When the value ofthe ARPT bits equals 00h and the CHIME bit(ALCFGRPT<14>) is cleared, the repeat function isdisabled and only a single alarm will occur. The alarmcan be repeated up to 255 times by loadingARPT7:ARPT0 with FFh.
After each alarm is issued, the value of the ARPT bitsis decremented by one. Once the value has reached00h, the alarm will be issued one last time, after whichthe ALRMEN bit will be cleared automatically and thealarm will turn off.
Indefinite repetition of the alarm can occur if the CHIMEbit = 1. Instead of the alarm being disabled when thevalue of the ARPT bits reaches 00h, it rolls over to FFhand continues counting indefinitely while CHIME is set.
18.3.2 ALARM INTERRUPTAt every alarm event, an interrupt is generated. In addi-tion, an alarm pulse output is provided that operates athalf the frequency of the alarm. This output iscompletely synchronous to the RTCC clock and can beused as a trigger clock to other peripherals.
FIGURE 18-2: ALARM MASK SETTINGS
Note: Changing any of the registers, other thenthe RCFGCAL and ALCFGRPT registersand the CHIME bit while the alarm isenabled (ALRMEN = 1), can result in afalse alarm event leading to a false alarminterrupt. To avoid a false alarm event, thetimer and alarm values should only bechanged while the alarm is disabled(ALRMEN = 0). It is recommended that theALCFGRPT register and CHIME bit bechanged when RTCSYNC = 0.
Note 1: Annually, except when configured for February 29.
s
s s
m s s
m m s s
h h m m s s
d h h m m s s
d d h h m m s s
m m d d h h m m s s
Day ofthe
Week Month Day Hours Minutes SecondsAlarm Mask Setting(AMASK3:AMASK0)
0000 � Every half second0001 � Every second
0010 � Every 10 seconds
0011 � Every minute
0100 � Every 10 minutes
0101 � Every hour
0110 � Every day
0111 � Every week
1000 � Every month
1001 � Every year(1)
DS39881C-page 178 Preliminary © 2008 Microchip Technology Inc.
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19.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR
The programmable CRC generator offers the followingfeatures:
� User-programmable polynomial CRC equation� Interrupt output� Data FIFO
The module implements a software configurable CRCgenerator. The terms of the polynomial and its lengthcan be programmed using the CRCXOR (X<15:1>) bitsand the CRCCON (PLEN3:PLEN0) bits, respectively.
Consider the CRC equation:
x16 + x12 + x5 + 1
To program this polynomial into the CRC generator,the CRC register bits should be set as shown inTable 19-1.
TABLE 19-1: EXAMPLE CRC SETUP
Note that for the value of X<15:1>, the 12th bit and the5th bit are set to �1�, as required by the equation. The 0bit required by the equation is always XORed. For a16-bit polynomial, the 16th bit is also always assumedto be XORed; therefore, the X<15:1> bits do not havethe 0 bit or the 16th bit.
The topology of a standard CRC generator is shown inFigure 19-2.
FIGURE 19-1: CRC SHIFTER DETAILS
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 30. Programmable CyclicRedundancy Check (CRC)� (DS39714).
Bit Name Bit Value
PLEN3:PLEN0 1111
X<15:1> 000100000010000
INOUT
BIT 0
0
1
p_clk
X1
INOUT
BIT 1
0
1
p_clk
X2
INOUT
BIT 2
0
1
p_clk
X3
INOUT
BIT 15
0
1
p_clk
X15
XOR
DOUT
0 1 2 15PLEN<3:0>
Hold Hold Hold Hold
CRC Read Bus
CRC Write Bus
CRC Shift Register
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 179
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FIGURE 19-2: CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 119.1 User Interface
19.1.1 DATA INTERFACETo start serial shifting, a �1� must be written to theCRCGO bit.
The module incorporates a FIFO that is 8 deep whenPLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. Thedata for which the CRC is to be calculated must first bewritten into the FIFO. The smallest data element thatcan be written into the FIFO is one byte. For example,if PLEN = 5, then the size of the data is PLEN + 1 = 6.The data must be written as follows:
data[5:0] = crc_input[5:0]
data[7:6] = �bxx
Once data is written into the CRCWDAT MSb (asdefined by PLEN), the value of the VWORD bits(CRCCON<12:8>) increments by one. The serialshifter starts shifting data into the CRC engine whenCRCGO = 1 and VWORD > 0. When the MSb isshifted out, VWORD decrements by one. The serialshifter continues shifting until the VWORD reaches 0.Therefore, for a given value of PLEN, it will take(PLEN + 1) * VWORD number of clock cycles tocomplete the CRC calculations.
When VWORD reaches 8 (or 16), the CRCFUL bit willbe set. When VWORD reaches 0, the CRCMPT bit willbe set.
To continually feed data into the CRC engine, the rec-ommended mode of operation is to initially �prime� theFIFO with a sufficient number of words so no interruptis generated before the next word can be written. Oncethat is done, start the CRC by setting the CRCGO bit to�1�. From that point onward, the VWORD bits should bepolled. If they read less than 8 or 16, another word canbe written into the FIFO.
To empty words already written into a FIFO, theCRCGO bit must be set to �1� and the CRC shifterallowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will benecessary to wait for the CRCMPT bit to go high beforereading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, theVWORD Pointer will roll over to 0. The hardware willthen behave as if the FIFO is empty. However, the con-dition to generate an interrupt will not be met; therefore,no interrupt will be generated (See Section 19.1.2�Interrupt Operation�).
At least one instruction cycle must pass after a write toCRCWDAT before a read of the VWORD bits is done.
19.1.2 INTERRUPT OPERATIONWhen the VWORD4:VWORD0 bits make a transitionfrom a value of �1� to �0�, an interrupt will be generated.
19.2 Operation in Power Save Modes
19.2.1 SLEEP MODEIf Sleep mode is entered while the module is operating,the module will be suspended in its current state untilclock execution resumes.
19.2.2 IDLE MODETo continue full module operation in Idle mode, theCSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way asit does in Sleep mode; pending interrupt events will bepassed on, even though the module clocks are notavailable.
D Q
BIT 0
p_clk
D Q
BIT 4
p_clk
D Q
BIT 5
p_clk
D Q
BIT 12
p_clk
XOR
SDOx
CRC Read Bus
CRC Write Bus
D Q
BIT 15
p_clk
DS39881C-page 180 Preliminary © 2008 Microchip Technology Inc.
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19.3 RegistersThere are four registers used to control programmableCRC operation:� CRCCON� CRCXOR� CRCDAT� CRCWDAT
REGISTER 19-1: CRCCON: CRC CONTROL REGISTER
U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0� � CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0
bit 15 bit 8
R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CRCFUL CRCMPT � CRCGO PLEN3 PLEN2 PLEN1 PLEN0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as �0�bit 13 CSIDL: CRC Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12-8 VWORD4:VWORD0: Pointer Value bitsIndicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 ≤ 7.
bit 7 CRCFUL: FIFO Full bit1 = FIFO is full 0 = FIFO is not full
bit 6 CRCMPT: FIFO Empty Bit1 = FIFO is empty 0 = FIFO is not empty
bit 5 Unimplemented: Read as �0�bit 4 CRCGO: Start CRC bit
1 = Start CRC serial shifter0 = CRC serial shifter turned off
bit 3-0 PLEN3:PLEN0: Polynomial Length bitsDenotes the length of the polynomial to be generated minus 1.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 181
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REGISTER 19-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0X15 X14 X13 X12 X11 X10 X9 X8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0X7 X6 X5 X4 X3 X2 X1 �
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-1 X15:X1: XOR of Polynomial Term Xn Enable bitsbit 0 Unimplemented: Read as �0�
DS39881C-page 182 Preliminary © 2008 Microchip Technology Inc.
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20.0 10-BIT HIGH-SPEED A/D CONVERTER
The 10-bit A/D Converter has the following keyfeatures:
� Successive Approximation (SAR) conversion� Conversion speeds of up to 500 ksps� Up to 13 analog input pins� External voltage reference input pins� Automatic Channel Scan mode� Selectable conversion trigger source� 16-word conversion result buffer� Selectable Buffer Fill modes� Four result alignment options � Operation during CPU Sleep and Idle modes
Depending on the particular device pinout, the 10-bitA/D Converter can have up to three analog input pins,designated AN0 through AN12. In addition, there aretwo analog input pins for external voltage referenceconnections. These voltage reference inputs may beshared with other analog input pins. The actual numberof analog input pins and external voltage referenceinput configuration will depend on the specific device.
A block diagram of the A/D Converter is shown inFigure 20-1.
To perform an A/D conversion:
1. Configure the A/D module:a) Select port pins as analog inputs
(AD1PCFG<15:0>).b) Select voltage reference source to match
expected range on analog inputs(AD1CON2<15:13>).
c) Select the analog conversion clock tomatch desired data rate with processorclock (AD1CON3<7:0>).
d) Select the appropriate sample/conversionsequence (AD1CON1<7:5> andAD1CON3<12:8>).
e) Select how conversion results arepresented in the buffer (AD1CON1<9:8>).
f) Select interrupt rate (AD1CON2<5:2>).g) Turn on A/D module (AD1CON1<15>).
2. Configure A/D interrupt (if required):a) Clear the AD1IF bit. b) Select A/D interrupt priority.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 17. 10-Bit A/D Converter�(DS39705).
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 183
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FIGURE 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAMComparator
10-Bit SAR Conversion Logic
VREF+
DAC
AN12
AN8(1)
AN9
AN10
AN11
AN4
AN5
AN6(1)
AN7(1)
AN0
AN1
AN2
AN3
VREF-
Sample Control
S/H
AVSS
AVDD
ADC1BUF0:ADC1BUFF
AD1CON1AD1CON2AD1CON3AD1CHS
AD1PCFGAD1CSSL
Control Logic
Data Formatting
Input MUX Control
Conversion Control
Pin Config. Control
Internal Data Bus
16
VR+VR-M
UX
AM
UX
B
VINH
VINL
VINH
VINH
VINL
VINL
VR+
VR-VR S
elec
t
Note 1: Analog channels AN6 through AN8 are available on 28-pin devices only.2: Band gap voltage reference (VBG) is internally connected to analog channel AN15, which does not appear on any pin.
VBG(2)
DS39881C-page 184 Preliminary © 2008 Microchip Technology Inc.
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REGISTER 20-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0 U-0 R/C-0 U-0 U-0 U-0 R/W-0 R/W-0ADON � ADSIDL � � � FORM1 FORM0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/W-0, HCSSSRC2 SSRC1 SSRC0 � � ASAM SAMP DONE
bit 7 bit 0
Legend: C = Clearable bit HCS = Hardware Clearable/Settable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 ADON: A/D Operating Mode bit1 = A/D Converter module is operating0 = A/D Converter is off
bit 14 Unimplemented: Read as �0�bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode
bit 12-10 Unimplemented: Read as �0�bit 9-8 FORM1:FORM0: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)10 = Fractional (dddd dddd dd00 0000)01 = Signed integer (ssss sssd dddd dddd)00 = Integer (0000 00dd dddd dddd)
bit 7-5 SSRC2:SSRC0: Conversion Trigger Source Select bits111 = Internal counter ends sampling and starts conversion (auto-convert)110 = Reserved10x = Reserved011 = Reserved010 = Timer3 compare ends sampling and starts conversion001 = Active transition on INT0 pin ends sampling and starts conversion000 = Clearing SAMP bit ends sampling and starts conversion
bit 4-3 Unimplemented: Read as �0�bit 2 ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set.0 = Sampling begins when SAMP bit is set
bit 1 SAMP: A/D Sample Enable bit1 = A/D sample/hold amplifier is sampling input0 = A/D sample/hold amplifier is holding
bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done0 = A/D conversion is NOT done
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 185
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REGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0VCFG2 VCFG1 VCFG0 � � CSCNA � �
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0BUFS � SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-13 VCFG2:VCFG0: Voltage Reference Configuration bits
bit 12-11 Unimplemented: Read as �0�bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs0 = Do not scan inputs
bit 9-8 Unimplemented: Read as �0�bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling buffer 08-0F, user should access data in 00-070 = A/D is currently filling buffer 00-07, user should access data in 08-0F
bit 6 Unimplemented: Read as �0�bit 5-2 SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence.....0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>)
bit 0 ALTS: Alternate Input Sample Mode Select bit1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and
MUX A input multiplexer settings for all subsequent samples0 = Always uses MUX A input multiplexer settings
VCFG2:VCFG0 VR+ VR-
000 AVDD* AVSS*001 External VREF+ pin AVSS*010 AVDD* External VREF- pin011 External VREF+ pin External VREF- pin1xx AVDD* AVSS*
* AVDD and AVSS inputs are tied to VDD and VSS on 28-pin devices.
DS39881C-page 186 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 20-3: AD1CON3: A/D CONTROL REGISTER 3R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADRC � � SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 ADRC: A/D Conversion Clock Source bit1 = A/D internal RC clock0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as �0�bit 12-8 SAMC4:SAMC0: Auto-Sample Time bits
11111 = 31 TAD·····00001 = 1 TAD00000 = 0 TAD (not recommended)
bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits11111111 = 256 � TCY······00000001 = 2 � TCY00000000 = TCY
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 187
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REGISTER 20-4: AD1CHS: A/D INPUT SELECT REGISTER
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0CH0NB � � � CH0SB3(1,2) CH0SB2(1,2) CH0SB1(1,2) CH0SB0(1,2)
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0CH0NA � � � CH0SA3(1,2) CH0SA2(1,2) CH0SA1(1,2) CH0SA0(1,2)
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit1 = Channel 0 negative input is AN10 = Channel 0 negative input is VR-
bit 14-12 Unimplemented: Read as �0�bit 11-8 CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1,2)
1111 = Channel 0 positive input is AN15 (band gap voltage reference)1100 = Channel 0 positive input is AN121011 = Channel 0 positive input is AN11·····0001 = Channel 0 positive input is AN10000 = Channel 0 positive input is AN0
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit1 = Channel 0 negative input is AN10 = Channel 0 negative input is VR-
bit 6-4 Unimplemented: Read as �0�bit 3-0 CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits(1,2)
1111 = Channel 0 positive input is AN15 (band gap voltage reference)1100 = Channel 0 positive input is AN121011 = Channel 0 positive input is AN11·····0001 = Channel 0 positive input is AN10000 = Channel 0 positive input is AN0
Note 1: Combinations �1101� and �1110� are unimplemented; do not use.2: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; do not use.
DS39881C-page 188 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 20-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PCFG15 � � PCFG12 PCFG11 PCFG10 PCFG9 PCFG8(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PCFG7(1) PCFG6(1) PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 PCFG15: Analog Input Pin Configuration Control bits1 = Band gap voltage reference is disabled0 = Band gap voltage reference enabled
bit 14-13 Unimplemented: Read as �0�bit 12-0 PCFG12:PCFG0: Analog Input Pin Configuration Control bits(1)
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage
Note 1: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits set.
REGISTER 20-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CSSL15 � � CSSL12 CSSL11 CSSL10 CSSL9 CSSL8(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CSSL7(1) CSSL6(1) CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 CSSL15: Band Gap Reference Input Pin Scan Selection bits1 = Band gap voltage reference channel selected for input scan0 = Band gap voltage reference channel omitted from input scan
bit 14-13 Unimplemented: Read as �0�bit 12-0 CSSL12:CSSL0: A/D Input Pin Scan Selection bits(1)
1 = Corresponding analog channel selected for input scan0 = Analog channel omitted from input scan
Note 1: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits cleared.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 189
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EQUATION 20-1: A/D CONVERSION CLOCK PERIOD(1)FIGURE 20-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
TAD = TCY � (ADCS +1)
ADCS =TADTCY
� 1
CPINVA
Rs ANxVT = 0.6V
VT = 0.6V ILEAKAGE
RIC ≤ 250Ω SamplingSwitch
RSS
CHOLD= DAC capacitance
VSS
VDD
= 4.4 pF (Typical)±500 nA
Legend: CPIN
VTILEAKAGE
RICRSS
CHOLD
= Input Capacitance= Threshold Voltage= Leakage Current at the pin due to
= Interconnect Resistance= Sampling Switch Resistance= Sample/Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
RSS ≤ 5 kΩ (Typical)
6-11 pF(Typical)
DS39881C-page 190 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
FIGURE 20-3: A/D TRANSFER FUNCTION10 0000 0001 (513)
10 0000 0010 (514)10 0000 0011 (515)
01 1111 1101 (509)
01 1111 1110 (510)01 1111 1111 (511)
11 1111 1110 (1022)11 1111 1111 (1023)
00 0000 0000 (0)00 0000 0001 (1)
Output Code
10 0000 0000 (512)
(VIN
H �
VIN
L)
VR-
VR+
� VR
-10
24
512*
(VR
+ �
VR-)
1024
VR+
V R- +
VR- +
1023
*(VR
+ �
VR-)
1024
VR- +
0
(Binary (Decimal))
Voltage Level
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 191
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NOTES:DS39881C-page 192 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
21.0 COMPARATOR MODULE
FIGURE 21-1: COMPARATOR I/O OPERATING MODES
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 16. Output Compare�(DS39706).
C2
C2IN-VIN-
VIN+
C2IN+
CVREFC2IN+
C2OUT(1)
CMCON<7>
C1
C1IN-VIN-
VIN+
C1IN+
CVREFC1IN+
C1OUT(1)
CMCON<6>C1NEG
C1POS
C2NEG
C2POS
C1INV
C2INV
C1OUTEN
C2OUTEN
C1EN
C2EN
Note 1: This peripheral�s outputs must be assigned to an available RPn pin before use. Please see Section 9.4 �Peripheral Pin Select� for more information.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 193
PIC24FJ64GA004 FAMILY
REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER
R/W-0 U-0 R/C-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0CMIDL � C2EVT C1EVT C2EN C1EN C2OUTEN(1) C1OUTEN(2)
bit 15 bit 8
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15 CMIDL: Stop in Idle Mode bit1 = When device enters Idle mode, module does not generate interrupts; module is still enabled0 = Continue normal module operation in Idle mode
bit 14 Unimplemented: Read as �0�bit 13 C2EVT: Comparator 2 Event
1 = Comparator output changed states0 = Comparator output did not change states
bit 12 C1EVT: Comparator 1 Event1 = Comparator output changed states0 = Comparator output did not change states
bit 11 C2EN: Comparator 2 Enable1 = Comparator is enabled0 = Comparator is disabled
bit 10 C1EN: Comparator 1 Enable1 = Comparator is enabled0 = Comparator is disabled
bit 9 C2OUTEN: Comparator 2 Output Enable(1)
1 = Comparator output is driven on the output pad0 = Comparator output is not driven on the output pad
bit 8 C1OUTEN: Comparator 1 Output Enable(2)
1 = Comparator output is driven on the output pad0 = Comparator output is not driven on the output pad
bit 7 C2OUT: Comparator 2 Output bitWhen C2INV = 0:1 = C2 VIN+ > C2 VIN-0 = C2 VIN+ < C2 VIN-When C2INV = 1:0 = C2 VIN+ > C2 VIN-1 = C2 VIN+ < C2 VIN-
bit 6 C1OUT: Comparator 1 Output bitWhen C1INV = 0:1 = C1 VIN+ > C1 VIN-0 = C1 VIN+ < C1 VIN-When C1INV = 1:0 = C1 VIN+ > C1 VIN-1 = C1 VIN+ < C1 VIN-
DS39881C-page 194 Preliminary © 2008 Microchip Technology Inc.
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bit 5 C2INV: Comparator 2 Output Inversion bit1 = C2 output inverted0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit1 = C1 output inverted0 = C1 output not inverted
bit 3 C2NEG: Comparator 2 Negative Input Configure bit1 = Input is connected to VIN+0 = Input is connected to VIN-See Figure 21-1 for the Comparator modes.
bit 2 C2POS: Comparator 2 Positive Input Configure bit1 = Input is connected to VIN+0 = Input is connected to CVREFSee Figure 21-1 for the Comparator modes.
bit 1 C1NEG: Comparator 1 Negative Input Configure bit1 = Input is connected to VIN+0 = Input is connected to VIN-See Figure 21-1 for the Comparator modes.
bit 0 C1POS: Comparator 1 Positive Input Configure bit1 = Input is connected to VIN+0 = Input is connected to CVREFSee Figure 21-1 for the Comparator modes.
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See Section 9.4 �Peripheral Pin Select� for more information.
REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 195
PIC24FJ64GA004 FAMILY
NOTES:DS39881C-page 196 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
22.0 COMPARATOR VOLTAGE REFERENCE
22.1 Configuring the Comparator Voltage Reference
The voltage reference module is controlled through theCVRCON register (Register 22-1). The comparatorvoltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to beused is selected by the CVRR bit (CVRCON<5>). Theprimary difference between the ranges is the size of thesteps selected by the CVREF Selection bits(CVR3:CVR0), with one range offering finer resolution.
The comparator reference supply voltage can comefrom either VDD and VSS, or the external VREF+ andVREF-. The voltage source is selected by the CVRSSbit (CVRCON<4>).
The settling time of the comparator voltage referencemust be considered when changing the CVREFoutput.
FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the�PIC24F Family Reference Manual�,�Section 20. Comparator VoltageReference Module� (DS39709).
16-to
-1 M
UX
CVR3:CVR08R
RCVREN
CVRSS = 0AVDD
VREF+CVRSS = 1
8R
CVRSS = 0
VREF-CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CVREF
AVSS
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 197
PIC24FJ64GA004 FAMILY
REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0� � � � � � � �
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as �0�-n = Value at POR �1� = Bit is set �0� = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as �0�bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit1 = CVREF voltage level is output on CVREF pin0 = CVREF voltage level is disconnected from CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size
bit 4 CVRSS: Comparator VREF Source Selection bit1 = Comparator reference source CVRSRC = VREF+ � VREF- 0 = Comparator reference source CVRSRC = AVDD � AVSS
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bitsWhen CVRR = 1:CVREF = (CVR<3:0>/ 24) • (CVRSRC)When CVRR = 0:CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)
DS39881C-page 198 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
23.0 SPECIAL FEATURES
PIC24FJ64GA004 family devices include severalfeatures intended to maximize application flexibility andreliability, and minimize cost through elimination ofexternal components. These are:� Flexible Configuration� Watchdog Timer (WDT)� Code Protection� JTAG Boundary Scan Interface� In-Circuit Serial Programming� In-Circuit Emulation
23.1 Configuration BitsThe Configuration bits can be programmed (read as �0�),or left unprogrammed (read as �1�), to select variousdevice configurations. These bits are mapped starting atprogram memory location F80000h. A complete list isshown in Table 23-1. A detailed explanation of the vari-ous bit functions is provided in Register 23-1 throughRegister 23-4.
Note that address F80000h is beyond the user programmemory space. In fact, it belongs to the configurationmemory space (800000h-FFFFFFh) which can only beaccessed using table reads and table writes.
23.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ64GA004 FAMILY DEVICES
In PIC24FJ64GA004 family devices, the configurationbytes are implemented as volatile memory. This meansthat configuration data must be programmed each timethe device is powered up. Configuration data is storedin the two words at the top of the on-chip programmemory space, known as the Flash ConfigurationWords. Their specific locations are shown inTable 23-1. These are packed representations of theactual device Configuration bits, whose actuallocations are distributed among five locations in config-uration space. The configuration data is automaticallyloaded from the Flash Configuration Words to theproper Configuration registers during device Resets.
TABLE 23-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GA004 FAMILY DEVICES
When creating applications for these devices, usersshould always specifically allocate the location of theFlash Configuration Word for configuration data. This isto make certain that program code is not stored in thisaddress when the code is compiled.
The Configuration bits are reloaded from the FlashConfiguration Word on any device Reset.
The upper byte of both Flash Configuration Words inprogram memory should always be �1111 1111�. Thismakes them appear to be NOP instructions in theremote event that their locations are ever executed byaccident. Since Configuration bits are not implementedin the corresponding locations, writing �1�s to theselocations has no effect on device operation.
Note: This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to thefollowing sections of the �PIC24F FamilyReference Manual�:
� Section 9. �Watchdog Timer (WDT)� (DS39697)
� Section 32. �High-Level Device Integration� (DS39719)
� Section 33. �Programming and Diagnostics� (DS39716)
Note: Configuration data is reloaded on all typesof device Resets.
DeviceConfiguration Word
Addresses
1 2
PIC24FJ16GA 002BFEh 002BFChPIC24FJ32GA 0057FEh 0057FChPIC24FJ48GA 0083FEh 0083FChPIC24FJ64GA 00ABFEh 00ABFCh
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 199
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REGISTER 23-1: CW1: FLASH CONFIGURATION WORD 1
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1� � � � � � � �
bit 23 bit 16
r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1
r JTAGEN GCP GWRP DEBUG r ICS1 ICS0bit 15 bit 8
R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1FWDTEN WINDIS � FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0
Legend: r = Reserved bitR = Readable bit PO = Program Once bit U = Unimplemented bit, read as �0�-n = Value when device is unprogrammed �1� = Bit is set �0� = Bit is cleared
bit 23-16 Unimplemented: Read as �1�bit 15 Reserved: The value is unknown; program as �0� bit 14 JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled0 = JTAG port is disabled
bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled0 = Code protection is enabled for the entire program memory space
bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed0 = Writes to program memory are disabled
bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode0 = Device resets into Debug mode
bit 10 Reserved: Always maintain as �1� bit 9-8 ICS1:ICS0: Emulator Pin Placement Select bits
11 = Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD110 = Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD201 = Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD300 = Reserved; do not use
bit 7 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled0 = Watchdog Timer is disabled
bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled0 = Windowed Watchdog Timer enabled; FWDTEN must be �1�
bit 5 Unimplemented: Read as �1�bit 4 FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:1280 = Prescaler ratio of 1:32
DS39881C-page 200 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
bit 3-0 WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits1111 = 1:32,7681110 = 1:16,3841101 = 1:8,1921100 = 1:4,0961011 = 1:2,0481010 = 1:1,0241001 = 1:5121000 = 1:2560111 = 1:1280110 = 1:640101 = 1:320100 = 1:160011 = 1:80010 = 1:40001 = 1:20000 = 1:1
REGISTER 23-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 201
PIC24FJ64GA004 FAMILY
REGISTER 23-2: CW2: FLASH CONFIGURATION WORD 2U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1� � � � � � � �
bit 23 bit 16
R/PO-1 U-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1IESO � � � � FNOSC2 FNOSC1 FNOSC0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1FCKSM1 FCKSM0 OSCIOFCN IOL1WAY � I2C1SEL POSCMD1 POSCMD0
bit 7 bit 0
Legend: r = Reserved bitR = Readable bit PO = Program Once bit U = Unimplemented bit, read as �0�-n = Value when device is unprogrammed �1� = Bit is set �0� = Bit is cleared
bit 23-16 Unimplemented: Read as �1�bit 15 IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) enabled0 = IESO mode (Two-Speed Start-up) disabled
bit 14-11 Unimplemented: Read as �1�bit 10-8 FNOSC2:FNOSC0: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)000 = Fast RC Oscillator (FRC)
bit 7-6 FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits1x = Clock switching and Fail-Safe Clock Monitor are disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 OSCIOFCN: OSCO Pin Configuration bitIf POSCMD1:POSCMD0 = 11 or 00:1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2)0 = OSCO/CLKO/RA3 functions as port I/O (RA3)If POSCMD1:POSCMD0 = 10 or 01:OSCIOFCN has no effect on OSCO/CLKO/RA3.
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit1 = The OSCCON<IOLOCK> bit can be set once, provided the unlock sequence has been completed.
Once set, the Peripheral Pin Select registers cannot be written to a second time.0 = The OSCCON<IOLOCK> bit can be set and cleared as needed, provided the unlock sequence has
been completedbit 3 Unimplemented: Read as �1�bit 2 I2C1SEL: I2C1 Pin Select bit
1 = Use default SCL1/SDA1 pins0 = Use alternate SCL1/SDA1 pins
bit 1-0 POSCMD1:POSCMD0: Primary Oscillator Configuration bits11 = Primary oscillator disabled10 = HS Oscillator mode selected01 = XT Oscillator mode selected00 = EC Oscillator mode selected
DS39881C-page 202 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 23-3: DEVID: DEVICE ID REGISTERU U U U U U U U� � � � � � � �
bit 23 bit 16
U U R R R R R R� � FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2
bit 15 bit 8
R R R R R R R RFAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-14 Unimplemented: Read as �1�bit 13-6 FAMID7:FAMID0: Device Family Identifier bits
00010001 = PIC24FJ64GA004 family bit 5-0 DEV5:DEV0: Individual Device Identifier bits
000100 = PIC24FJ16GA002000101 = PIC24FJ32GA002000110 = PIC24FJ48GA002000111 = PIC24FJ64GA002001100 = PIC24FJ16GA004001101 = PIC24FJ32GA004001110 = PIC24FJ48GA004001111 = PIC24FJ64GA004
REGISTER 23-4: DEVREV: DEVICE REVISION REGISTER
U U U U U U U U� � � � � � � �
bit 23 bit 16
U U U U U U U R� � � � � � � MAJRV2
bit 15 bit 8
R R U U U R R RMAJRV1 MAJRV0 � � � DOT2 DOT1 DOT0
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-9 Unimplemented: Read as �0�bit 8-6 MAJRV2:MAJRV0: Major Revision Identifier bitsbit 5-3 Unimplemented: Read as �0�bit 2-0 DOT2:DOT0: Minor Revision Identifier bits
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23.2 On-Chip Voltage RegulatorAll of the PIC24FJ64GA004 family of devices powertheir core digital logic at a nominal 2.5V. This maycreate an issue for designs that are required to operateat a higher typical voltage, such as 3.3V. To simplifysystem design, all devices in the PIC24FJ64GA004family incorporate an on-chip regulator that allows thedevice to run its core logic from VDD.The regulator is controlled by the DISVREG pin. TyingVSS to the pin enables the regulator, which in turn, pro-vides power to the core from the other VDD pins. Whenthe regulator is enabled, a low-ESR capacitor (such asceramic) must be connected to the VDDCORE/VCAP pin(Figure 23-1). This helps to maintain the stability of theregulator. The recommended value for the filter capacitoris provided in Section 26.1 �DC Characteristics�.
If DISVREG is tied to VDD, the regulator is disabled. Inthis case, separate power for the core logic at a nomi-nal 2.5V must be supplied to the device on theVDDCORE/VCAP pin to run the I/O pins at higher voltagelevels, typically 3.3V. Alternatively, the VDDCORE/VCAPand VDD pins can be tied together to operate at a lowernominal voltage. Refer to Figure 23-1 for possibleconfigurations.
23.2.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION
When it is enabled, the on-chip regulator provides aconstant voltage of 2.5V nominal to the digital corelogic.
The regulator can provide this level from a VDD of about2.5V, all the way up to the device�s VDDMAX. It does nothave the capability to boost VDD levels below 2.5V. Inorder to prevent �brown out� conditions when the volt-age drops too low for the regulator, the regulator entersTracking mode. In Tracking mode, the regulator outputfollows VDD, with a typical voltage drop of 100 mV.
When the device enters Tracking mode, it is no longerpossible to operate at full speed. To provide informationabout when the device enters Tracking mode, theon-chip regulator includes a simple, Low-VoltageDetect circuit. When VDD drops below full-speed oper-ating voltage, the circuit sets the Low-Voltage DetectInterrupt Flag, LVDIF (IFS4<8>). This can be used togenerate an interrupt and put the application into alow-power operational mode, or trigger an orderlyshutdown.
Low-Voltage Detection is only available when theregulator is enabled.
FIGURE 23-1: CONNECTIONS FOR THE ON-CHIP REGULATOR
23.2.2 ON-CHIP REGULATOR AND PORWhen the voltage regulator is enabled, it takes approxi-mately 20 μs for it to generate output. During this time,designated as TSTARTUP, code execution is disabled.TSTARTUP is applied every time the device resumesoperation after any power-down, including Sleep mode.
If the regulator is disabled, a separate Power-up Timer(PWRT) is automatically enabled. The PWRT adds afixed delay of 64 ms nominal delay at device start-up.
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJ64GA3.3V(1)2.5V(1)
Regulator Disabled (DISVREG tied to VDD):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJ64GA2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJ64GA
CEFC
3.3V
(10 μF typ)
Regulator Enabled (DISVREG tied to VSS):
Note 1: These are typical operating voltages. Refer to Section 26.1 �DC Characteristics� for the full operating ranges of VDD and VDDCORE.
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23.2.3 ON-CHIP REGULATOR AND BORWhen the on-chip regulator is enabled,PIC24FJ64GA004 family devices also have a simplebrown-out capability. If the voltage supplied to the reg-ulator is inadequate to maintain the tracking level, theregulator Reset circuitry will generate a Brown-outReset. This event is captured by the BOR flag bit(RCON<1>). The brown-out voltage levels are speci-fied in Section 26.1 �DC Characteristics�.23.2.4 POWER-UP REQUIREMENTSThe on-chip regulator is designed to meet the power-uprequirements for the device. If the application does notuse the regulator, then strict power-up conditions mustbe adhered to. While powering up, VDDCORE mustnever exceed VDD by 0.3 volts.
23.2.5 VOLTAGE REGULATOR STANDBY MODE
When enabled, the on-chip regulator always consumesa small incremental amount of current over IDD/IPD,including when the device is in Sleep mode, eventhough the core digital logic does not require power. Toprovide additional savings in applications where powerresources are critical, the regulator automaticallydisables itself whenever the device goes into Sleepmode. This feature is controlled by the VREGS bit(RCON<8>). By default, this bit is cleared, whichenables Standby mode. When waking up from Standbymode, the regulator will require around 190 μS towake-up. This extra time is needed to ensure that theregulator can source enough current to power theFlash memory.
For applications which require a faster wake-up time, itis possible to disable regulator Standby mode. TheVREGS bit (RCON<8>) can be set to turn off Standbymode so that the Flash stays powered when in Sleepmode and the device can wake-up in 10 μS. WhenVREGS is set, the power consumption while in Sleepmode, will be approximately 40 μA higher than powerconsumption when the regulator is allowed to enterStandby mode.
23.3 Watchdog Timer (WDT)For PIC24FJ64GA004 family devices, the WDT isdriven by the LPRC oscillator. When the WDT isenabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.This feeds a prescaler that can be configured for either5-bit (divide-by-32) or 7-bit (divide-by-128) operation.The prescaler is set by the FWPSA Configuration bit.With a 31 kHz input, the prescaler yields a nominalWDT time-out period (TWDT) of 1 ms in 5-bit mode, or4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaleroutput and allows for a wide range of time-out periods.The postscaler is controlled by the WDTPS3:WDTPS0Configuration bits (Flash Configuration Word 1<3:0>),which allow the selection of a total of 16 settings, from1:1 to 1:32,768. Using the prescaler and postscaler,time-out periods ranging from 1 ms to 131 seconds canbe achieved.
The WDT, prescaler and postscaler are reset:
� On any device Reset� On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor)
� When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)
� When the device exits Sleep or Idle mode to resume normal operation
� By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run duringSleep or Idle modes. When the WDT time-out occurs,the device will wake the device and code execution willcontinue from where the PWRSAV instruction was exe-cuted. The corresponding SLEEP or IDLE bits(RCON<3:2>) will need to be cleared in software afterthe device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-matically cleared following a WDT time-out. To detectsubsequent WDT events, the flag must be cleared insoftware.
Note: For more information, see Section 26.0�Electrical Characteristics�.
Note: The CLRWDT and PWRSAV instructionsclear the prescaler and postscaler countswhen executed.
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23.3.1 WINDOWED OPERATIONThe Watchdog Timer has an optional Fixed Windowmode of operation. In this Windowed mode, CLRWDTinstructions can only reset the WDT during the last 1/4of the programmed WDT period. A CLRWDT instructionexecuted before that window causes a WDT Reset,similar to a WDT time-out.Windowed WDT mode is enabled by programming theWINDIS Configuration bit (CW1<6>) to �0�.
23.3.2 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTENConfiguration bit. When the FWDTEN Configuration bitis set, the WDT is always enabled.
The WDT can be optionally controlled in software whenthe FWDTEN Configuration bit has been programmedto �0�. The WDT is enabled in software by setting theSWDTEN control bit (RCON<5>). The SWDTENcontrol bit is cleared on any device Reset. The softwareWDT option allows the user to enable the WDT forcritical code segments and disable the WDT duringnon-critical segments for maximum power savings.
FIGURE 23-2: WDT BLOCK DIAGRAM
23.4 JTAG InterfacePIC24FJ64GA004 family devices implement a JTAGinterface, which supports boundary scan device testingas well as in-circuit programming.
23.5 Program Verification and Code Protection
For all devices in the PIC24FJ64GA004 family ofdevices, the on-chip program memory space is treatedas a single block. Code protection for this block iscontrolled by one Configuration bit, GCP. This bitinhibits external reads and writes to the programmemory space. It has no direct effect in normalexecution mode.
Write protection is controlled by the GWRP bit in theConfiguration Word. When GWRP is programmed to�0�, internal write and erase operations to programmemory are blocked.
23.5.1 CONFIGURATION REGISTER PROTECTION
The Configuration registers are protected againstinadvertent or unwanted changes or reads in two ways.The primary protection method is the same as that ofthe RP registers � shadow registers contain a compli-mentary value which is constantly compared with theactual value.
To safeguard against unpredictable events, Configura-tion bit changes resulting from individual cell leveldisruptions (such as ESD events) will cause a parityerror and trigger a device Reset.
The data for the Configuration registers is derived fromthe Flash Configuration Words in program memory.When the GCP bit is set, the source data for deviceconfiguration is also protected as a consequence.
LPRC Input WDT Overflow
Wake from Sleep
31 kHz
Prescaler Postscaler
FWPSA
SWDTENFWDTEN
Reset
All Device Resets
Sleep or Idle Mode
LPRC Control
CLRWDT Instr.PWRSAV Instr.
(5-bit/7-bit) 1:1 to 1:32.768
WDTPS3:WDTPS0
1 ms/4 ms
Exit Sleep orIdle Mode
WDTCounter
Transition toNew Clock Source
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23.6 In-Circuit Serial ProgrammingPIC24FJ64GA004 family microcontrollers can be seri-ally programmed while in the end application circuit.This is simply done with two lines for clock (PGCx) anddata (PGDx) and three other lines for power, groundand the programming voltage. This allows customers tomanufacture boards with unprogrammed devices andthen program the microcontroller just before shippingthe product. This also allows the most recent firmwareor a custom firmware to be programmed.23.7 In-Circuit DebuggerWhen MPLAB® ICD 2 is selected as a debugger, thein-circuit debugging functionality is enabled. This func-tion allows simple debugging functions when used withMPLAB IDE. Debugging functionality is controlledthrough the EMUCx (Emulation/Debug Clock) andEMUDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,the design must implement ICSP connections toMCLR, VDD, VSS, PGCx, PGDx and theEMUDx/EMUCx pin pair. In addition, when the featureis enabled, some of the resources are not available forgeneral use. These resources include the first 80 bytesof data RAM and two I/O pins.
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NOTES:DS39881C-page 208 Preliminary © 2008 Microchip Technology Inc.
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24.0 DEVELOPMENT SUPPORTThe PIC® microcontrollers are supported with a fullrange of hardware and software development tools:
� Integrated Development Environment- MPLAB® IDE Software
� Assemblers/Compilers/Linkers- MPASMTM Assembler- MPLAB C18 and MPLAB C30 C Compilers- MPLINKTM Object Linker/
MPLIBTM Object Librarian- MPLAB ASM30 Assembler/Linker/Library
� Simulators- MPLAB SIM Software Simulator
� Emulators- MPLAB ICE 2000 In-Circuit Emulator- MPLAB REAL ICE� In-Circuit Emulator
� In-Circuit Debugger- MPLAB ICD 2
� Device Programmers- PICSTART® Plus Development Programmer- MPLAB PM3 Device Programmer- PICkit� 2 Development Programmer
� Low-Cost Demonstration and Development Boards and Evaluation Kits
24.1 MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16-bit micro-controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
� A single graphical interface to all debugging tools- Simulator- Programmer (sold separately)- Emulator (sold separately)- In-Circuit Debugger (sold separately)
� A full-featured editor with color-coded context� A multiple project manager� Customizable data windows with direct edit of
contents� High-level source code debugging� Visual device initializer for easy register
initialization� Mouse over variable inspection� Drag and drop variables from source to watch
windows� Extensive on-line help� Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR C Compilers
The MPLAB IDE allows you to:
� Edit your source files (either assembly or C)� One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (automatically updates all project information)
� Debug using:- Source files (assembly or C)- Mixed assembly and C- Machine code
MPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost-effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increased flexibilityand power.
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24.2 MPASM AssemblerThe MPASM Assembler is a full-featured, universalmacro assembler for all PIC MCUs.The MPASM Assembler generates relocatable objectfiles for the MPLINK Object Linker, Intel® standard HEXfiles, MAP files to detail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.
The MPASM Assembler features include:
� Integration into MPLAB IDE projects� User-defined macros to streamline
assembly code� Conditional assembly for multi-purpose
source files� Directives that allow complete control over the
assembly process
24.3 MPLAB C18 and MPLAB C30 C Compilers
The MPLAB C18 and MPLAB C30 Code DevelopmentSystems are complete ANSI C compilers forMicrochip�s PIC18 and PIC24 families of microcontrol-lers and the dsPIC30 and dsPIC33 family of digital sig-nal controllers. These compilers provide powerfulintegration capabilities, superior code optimization andease of use not found with other compilers.
For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.
24.4 MPLINK Object Linker/MPLIB Object Librarian
The MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and theMPLAB C18 C Compiler. It can link relocatable objectsfrom precompiled libraries, using directives from alinker script.
The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.
The object linker/library features include:
� Efficient linking of single libraries instead of many smaller files
� Enhanced code maintainability by grouping related modules together
� Flexible creation of libraries with easy module listing, replacement, deletion and extraction
24.5 MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatablemachine code from symbolic assembly language fordsPIC30F devices. MPLAB C30 C Compiler uses theassembler to produce its object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:
� Support for the entire dsPIC30F instruction set� Support for fixed-point and floating-point data� Command line interface� Rich directive set� Flexible macro language� MPLAB IDE compatibility
24.6 MPLAB SIM Software SimulatorThe MPLAB SIM Software Simulator allows codedevelopment in a PC-hosted environment by simulat-ing the PIC MCUs and dsPIC® DSCs on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The tracebuffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supportssymbolic debugging using the MPLAB C18 andMPLAB C30 C Compilers, and the MPASM andMPLAB ASM30 Assemblers. The software simulatoroffers the flexibility to develop and debug code outsideof the hardware laboratory environment, making it anexcellent, economical software development tool.
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24.7 MPLAB ICE 2000High-Performance In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intendedto provide the product development engineer with acomplete microcontroller design tool set for PICmicrocontrollers. Software control of the MPLAB ICE2000 In-Circuit Emulator is advanced by the MPLABIntegrated Development Environment, which allowsediting, building, downloading and source debuggingfrom a single environment.
The MPLAB ICE 2000 is a full-featured emulatorsystem with enhanced trace, trigger and data monitor-ing features. Interchangeable processor modules allowthe system to be easily reconfigured for emulation ofdifferent processors. The architecture of the MPLABICE 2000 In-Circuit Emulator allows expansion tosupport new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system hasbeen designed as a real-time emulation system withadvanced features that are typically found on moreexpensive development tools. The PC platform andMicrosoft® Windows® 32-bit operating system werechosen to best make these features available in asimple, unified application.
24.8 MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System isMicrochip�s next generation high-speed emulator forMicrochip Flash DSC and MCU devices. It debugs andprograms PIC® Flash MCUs and dsPIC® Flash DSCswith the easy-to-use, powerful graphical user interface ofthe MPLAB Integrated Development Environment (IDE),included with each kit.
The MPLAB REAL ICE probe is connected to the designengineer�s PC using a high-speed USB 2.0 interface andis connected to the target with either a connectorcompatible with the popular MPLAB ICD 2 system(RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection(CAT5).
MPLAB REAL ICE is field upgradeable through futurefirmware downloads in MPLAB IDE. In upcomingreleases of MPLAB IDE, new devices will be supported,and new features will be added, such as software break-points and assembly code trace. MPLAB REAL ICEoffers significant advantages over competitive emulatorsincluding low-cost, full-speed emulation, real-timevariable watches, trace analysis, complex breakpoints, aruggedized probe interface and long (up to three meters)interconnection cables.
24.9 MPLAB ICD 2 In-Circuit DebuggerMicrochip�s In-Circuit Debugger, MPLAB ICD 2, is apowerful, low-cost, run-time development tool,connecting to the host PC via an RS-232 or high-speedUSB interface. This tool is based on the Flash PICMCUs and can be used to develop for these and otherPIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizesthe in-circuit debugging capability built into the Flashdevices. This feature, along with Microchip�s In-CircuitSerial ProgrammingTM (ICSPTM) protocol, offers cost-effective, in-circuit Flash debugging from the graphicaluser interface of the MPLAB Integrated DevelopmentEnvironment. This enables a designer to develop anddebug source code by setting breakpoints, single step-ping and watching variables, and CPU status andperipheral registers. Running at full speed enablestesting hardware and applications in real time. MPLABICD 2 also serves as a development programmer forselected PIC devices.
24.10 MPLAB PM3 Device ProgrammerThe MPLAB PM3 Device Programmer is a universal,CE compliant device programmer with programmablevoltage verification at VDDMIN and VDDMAX formaximum reliability. It features a large LCD display(128 x 64) for menus and error messages and a modu-lar, detachable socket assembly to support variouspackage types. The ICSP� cable assembly is includedas a standard item. In Stand-Alone mode, the MPLABPM3 Device Programmer can read, verify and programPIC devices without a PC connection. It can also setcode protection in this mode. The MPLAB PM3connects to the host PC via an RS-232 or USB cable.The MPLAB PM3 has high-speed communications andoptimized algorithms for quick programming of largememory devices and incorporates an SD/MMC card forfile storage and secure data applications.
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24.11 PICSTART Plus DevelopmentProgrammerThe PICSTART Plus Development Programmer is aneasy-to-use, low-cost, prototype programmer. Itconnects to the PC via a COM (RS-232) port. MPLABIntegrated Development Environment software makesusing the programmer simple and efficient. ThePICSTART Plus Development Programmer supportsmost PIC devices in DIP packages up to 40 pins.Larger pin count devices, such as the PIC16C92X andPIC17C76X, may be supported with an adapter socket.The PICSTART Plus Development Programmer is CEcompliant.
24.12 PICkit 2 Development ProgrammerThe PICkit� 2 Development Programmer is a low-costprogrammer and selected Flash device debugger withan easy-to-use interface for programming many ofMicrochip�s baseline, mid-range and PIC18F families ofFlash memory microcontrollers. The PICkit 2 Starter Kitincludes a prototyping development board, twelvesequential lessons, software and HI-TECH�s PICC�Lite C compiler, and is designed to help get up to speedquickly using PIC® microcontrollers. The kit provideseverything needed to program, evaluate and developapplications using Microchip�s powerful, mid-rangeFlash memory family of microcontrollers.
24.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development andevaluation boards for various PIC MCUs and dsPICDSCs allows quick application development on fully func-tional systems. Most boards include prototyping areas foradding custom circuitry and provide application firmwareand source code for examination and modification.
The boards support a variety of features, including LEDs,temperature sensors, switches, speakers, RS-232interfaces, LCD displays, potentiometers and additionalEEPROM memory.
The demonstration and development boards can beused in teaching environments, for prototyping customcircuits and for learning about various microcontrollerapplications.
In addition to the PICDEM� and dsPICDEM� demon-stration/development board series of circuits, Microchiphas a line of evaluation kits and demonstration softwarefor analog filter design, KEELOQ® security ICs, CAN,IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.
Check the Microchip web page (www.microchip.com)for the complete list of demonstration, developmentand evaluation kits.
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25.0 INSTRUCTION SET SUMMARY
The PIC24F instruction set adds many enhancementsto the previous PIC® MCU instruction sets, while main-taining an easy migration from previous PIC MCUinstruction sets. Most instructions are a single programmemory word. Only three instructions require twoprogram memory locations.
Each single-word instruction is a 24-bit word dividedinto an 8-bit opcode, which specifies the instructiontype and one or more operands, which further specifythe operation of the instruction. The instruction set ishighly orthogonal and is grouped into four basiccategories:
� Word or byte-oriented operations� Bit-oriented operations� Literal operations� Control operations
Table 25-1 shows the general symbols used indescribing the instructions. The PIC24F instruction setsummary in Table 25-2 lists all the instructions, alongwith the status flags affected by each instruction.
Most word or byte-oriented W register instructions(including barrel shift instructions) have threeoperands:
� The first source operand which is typically a register �Wb� without any address modifier
� The second source operand which is typically a register �Ws� with or without an address modifier
� The destination of the result which is typically a register �Wd� with or without an address modifier
However, word or byte-oriented file register instructionshave two operands:
� The file register specified by the value �f�� The destination, which could either be the file
register �f� or the W0 register, which is denoted as �WREG�
Most bit-oriented instructions (including simplerotate/shift instructions) have two operands:
� The W register (with or without an address modifier) or file register (specified by the value of �Ws� or �f�)
� The bit in the W register or file register (specified by a literal value or indirectly by the contents of register �Wb�)
The literal instructions that involve data movement mayuse some of the following operands:
� A literal value to be loaded into a W register or file register (specified by the value of �k�)
� The W register or file register where the literal value is to be loaded (specified by �Wb� or �f�)
However, literal instructions that involve arithmetic orlogical operations use some of the following operands:
� The first source operand which is a register �Wb� without any address modifier
� The second source operand which is a literal value
� The destination of the result (only if not the same as the first source operand) which is typically a register �Wd� with or without an address modifier
The control instructions may use some of the followingoperands:
� A program memory address � The mode of the table read and table write
instructions
All instructions are a single word, except for certaindouble-word instructions, which were made dou-ble-word instructions so that all the required informa-tion is available in these 48 bits. In the second word, the8 MSbs are �0�s. If this second word is executed as aninstruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a singleinstruction cycle, unless a conditional test is true or theprogram counter is changed as a result of the instruc-tion. In these cases, the execution takes two instructioncycles, with the additional instruction cycle(s) executedas a NOP. Notable exceptions are the BRA (uncondi-tional/computed branch), indirect CALL/GOTO, all tablereads and writes, and RETURN/RETFIE instructions,which are single-word instructions but take two or threecycles.
Certain instructions that involve skipping over the sub-sequent instruction require either two or three cycles ifthe skip is performed, depending on whether theinstruction being skipped is a single-word or two-wordinstruction. Moreover, double-word moves require twocycles. The double-word instructions execute in twoinstruction cycles.
Note: This chapter is a brief summary of thePIC24F instruction set architecture, and isnot intended to be a comprehensivereference source.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 213
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TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONSField Description
#text Means literal defined by �text�(text) Means �content of text�[text] Means �the location addressed by text�{ } Optional field or operation<n:m> Register bit field.b Byte mode selection.d Double-Word mode selection.S Shadow register select.w Word mode selection (default)bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky ZeroExpr Absolute address, label or expression (resolved by the linker)f File register address ∈ {0000h...1FFFh}lit1 1-bit unsigned literal ∈ {0,1}lit4 4-bit unsigned literal ∈ {0...15}lit5 5-bit unsigned literal ∈ {0...31}lit8 8-bit unsigned literal ∈ {0...255}lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word modelit14 14-bit unsigned literal ∈ {0...16384}lit16 16-bit unsigned literal ∈ {0...65535}lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be �0�None Field does not require an entry, may be blankPC Program CounterSlit10 10-bit signed literal ∈ {-512...511}Slit16 16-bit signed literal ∈ {-32768...32767}Slit6 6-bit signed literal ∈ {-16...16}Wb Base W register ∈ {W0..W15}Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }Wdo Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing)Wn One of 16 working registers ∈ {W0..W15}Wnd One of 16 destination working registers ∈ {W0..W15}Wns One of 16 source working registers ∈ {W0..W15}WREG W0 (working register used in file register instructions)Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }Wso Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
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TABLE 25-2: INSTRUCTION SET OVERVIEW AssemblyMnemonic Assembly Syntax Description # of
Words# of
CyclesStatus Flags
Affected
ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z
ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z
ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z
AND AND f f = f .AND. WREG 1 1 N, Z
AND f,WREG WREG = f .AND. WREG 1 1 N, Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z
ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z
BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None
BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None
BRA GT,Expr Branch if Greater than 1 1 (2) None
BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None
BRA LE,Expr Branch if Less than or Equal 1 1 (2) None
BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None
BRA LT,Expr Branch if Less than 1 1 (2) None
BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3)
None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3)
None
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 215
PIC24FJ64GA004 FAMILY
BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3)
None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3)
None
BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call Indirect Subroutine 1 2 None
CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep
COM COM f f = f 1 1 N, Z
COM f,WREG WREG = f 1 1 N, Z
COM Ws,Wd Wd = Ws 1 1 N, Z
CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z
CP Wb,Ws Compare Wb with Ws (Wb � Ws) 1 1 C, DC, N, OV, Z
CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z
CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z
CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb � Ws � C)
1 1 C, DC, N, OV, Z
CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 (2 or 3)
None
CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 (2 or 3)
None
CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 (2 or 3)
None
CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if ≠ 1 1 (2 or 3)
None
DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C
DEC DEC f f = f �1 1 1 C, DC, N, OV, Z
DEC f,WREG WREG = f �1 1 1 C, DC, N, OV, Z
DEC Ws,Wd Wd = Ws � 1 1 1 C, DC, N, OV, Z
DEC2 DEC2 f f = f � 2 1 1 C, DC, N, OV, Z
DEC2 f,WREG WREG = f � 2 1 1 C, DC, N, OV, Z
DEC2 Ws,Wd Wd = Ws � 2 1 1 C, DC, N, OV, Z
DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV
EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) AssemblyMnemonic Assembly Syntax Description # of
Words# of
CyclesStatus Flags
Affected
DS39881C-page 216 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
GOTO GOTO Expr Go to Address 2 2 None
GOTO Wn Go to Indirect 1 2 None
INC INC f f = f + 1 1 1 C, DC, N, OV, Z
INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z
INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z
IOR IOR f f = f .IOR. WREG 1 1 N, Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z
LNK LNK #lit14 Link Frame Pointer 1 1 None
LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z
MOV MOV f,Wn Move f to Wn 1 1 None
MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None
MOV f Move f to f 1 1 N, Z
MOV f,WREG Move f to WREG 1 1 N, Z
MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N, Z
MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None
MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None
NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z
NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None
POP.S Pop Shadow Registers 1 1 All
PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) AssemblyMnemonic Assembly Syntax Description # of
Words# of
CyclesStatus Flags
Affected
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 217
PIC24FJ64GA004 FAMILY
PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep
RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
RESET RESET Software Device Reset 1 1 None
RETFIE RETFIE Return from Interrupt 1 3 (2) None
RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None
RETURN RETURN Return from Subroutine 1 3 (2) None
RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z
RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z
RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z
RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z
SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z
SETM SETM f f = FFFFh 1 1 None
SETM WREG WREG = FFFFh 1 1 None
SETM Ws Ws = FFFFh 1 1 None
SL SL f f = Left Shift f 1 1 C, N, OV, Z
SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z
SUB SUB f f = f � WREG 1 1 C, DC, N, OV, Z
SUB f,WREG WREG = f � WREG 1 1 C, DC, N, OV, Z
SUB #lit10,Wn Wn = Wn � lit10 1 1 C, DC, N, OV, Z
SUB Wb,Ws,Wd Wd = Wb � Ws 1 1 C, DC, N, OV, Z
SUB Wb,#lit5,Wd Wd = Wb � lit5 1 1 C, DC, N, OV, Z
SUBB SUBB f f = f � WREG � (C) 1 1 C, DC, N, OV, Z
SUBB f,WREG WREG = f � WREG � (C) 1 1 C, DC, N, OV, Z
SUBB #lit10,Wn Wn = Wn � lit10 � (C) 1 1 C, DC, N, OV, Z
SUBB Wb,Ws,Wd Wd = Wb � Ws � (C) 1 1 C, DC, N, OV, Z
SUBB Wb,#lit5,Wd Wd = Wb � lit5 � (C) 1 1 C, DC, N, OV, Z
SUBR SUBR f f = WREG � f 1 1 C, DC, N, OV, Z
SUBR f,WREG WREG = WREG � f 1 1 C, DC, N, OV, Z
SUBR Wb,Ws,Wd Wd = Ws � Wb 1 1 C, DC, N, OV, Z
SUBR Wb,#lit5,Wd Wd = lit5 � Wb 1 1 C, DC, N, OV, Z
SUBBR SUBBR f f = WREG � f � (C) 1 1 C, DC, N, OV, Z
SUBBR f,WREG WREG = WREG � f � (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,Ws,Wd Wd = Ws � Wb � (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,#lit5,Wd Wd = lit5 � Wb � (C) 1 1 C, DC, N, OV, Z
SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None
TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) AssemblyMnemonic Assembly Syntax Description # of
Words# of
CyclesStatus Flags
Affected
DS39881C-page 218 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
ULNK ULNK Unlink Frame Pointer 1 1 None
XOR XOR f f = f .XOR. WREG 1 1 N, Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z
ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) AssemblyMnemonic Assembly Syntax Description # of
Words# of
CyclesStatus Flags
Affected
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 219
PIC24FJ64GA004 FAMILY
NOTES:DS39881C-page 220 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
26.0 ELECTRICAL CHARACTERISTICSThis section provides an overview of the PIC24FJ64GA004 family electrical characteristics. Additional information willbe provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ64GA004 family are listed below. Exposure to these maximum ratingconditions for extended periods may affect device reliability. Functional operation of the device at these, or any otherconditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(�) Ambient temperature under bias............................................................................................................ .-40°C to +135°CStorage temperature .............................................................................................................................. -65°C to +150°CVoltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0VVoltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0VVoltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0VMaximum current out of VSS pin ...........................................................................................................................300 mAMaximum current into VDD pin (Note 1)................................................................................................................250 mAMaximum output current sunk by any I/O pin..........................................................................................................25 mAMaximum output current sourced by any I/O pin ....................................................................................................25 mAMaximum current sunk by all ports .......................................................................................................................200 mAMaximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-1).
�NOTICE: Stresses above those listed under �Absolute Maximum Ratings� may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions forextended periods may affect device reliability.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 221
PIC24FJ64GA004 FAMILY
26.1 DC CharacteristicsFIGURE 26-1: PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
FIGURE 26-2: PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE)
Frequency
Volta
ge (V
DD
CO
RE)
(1)
3.00V
2.00V
32 MHz
2.75V
2.50V
2.25V
2.75V
16 MHz
2.35V
For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE � 2V) + 16 MHz.
Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V.
PIC24FJ64GA004/32GA004/64GA002/32GA002
Frequency
Volta
ge (V
DD
CO
RE)
(1)
3.00V
2.00V
24 MHz
2.75V
2.50V
2.25V
2.75V
2.35V
For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE � 2V) + 16 MHz.
Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V.
PIC24FJ64GA004/32GA004/64GA002/32GA002
16 MHz
DS39881C-page 222 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 26-1: THERMAL OPERATING CONDITIONSRating Symbol Min Typ Max Unit
PIC24FJ64GA004 Family: Operating Junction Temperature Range TJ -40 � +140 °C Operating Ambient Temperature Range TA -40 � +125 °CPower Dissipation: Internal Chip Power Dissipation:
PINT = VDD x (IDD � Σ IOH) PD PINT + PI/O W I/O Pin Power Dissipation:
PI/O = Σ ({VDD � VOH} x IOH) + Σ (VOL x IOL)Maximum Allowed Power Dissipation PDMAX (TJ � TA)/θJA W
TABLE 26-2: THERMAL PACKAGING CHARACTERISTICSCharacteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 300 mil SOIC θJA 49 � °C/W (Note 1)Package Thermal Resistance, 6x6x0.9 mm QFN θJA 33.7 � °C/W (Note 1)Package Thermal Resistance, 8x8x1 mm QFN θJA 28 � °C/W (Note 1)Package Thermal Resistance, 10x10x1 mm TQFP θJA 39.3 � °C/W (Note 1)Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 223
PIC24FJ64GA004 FAMILY
TABLE 26-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param No. Symbol Characteristic Min Typ(1) Max Units Conditions
Operating VoltageDC10 Supply Voltage
VDD 2.2 � 3.6 V Regulator enabledVDD VDDCORE � 3.6 V Regulator disabledVDDCORE 2.0 � 2.75 V Regulator disabled
DC12 VDR RAM Data Retention Voltage(2)
1.5 � � V
DC16 VPOR VDD Start Voltageto ensure internalPower-on Reset signal
� VSS � V
DC17 SVDD VDD Rise Rateto ensure internalPower-on Reset signal
0.05 � � V/ms 0-3.3V in 0.1s0-2.5V in 60 ms
Note 1: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.
DS39881C-page 224 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 26-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter No. Typical(1) Max Units Conditions
Operating Current (IDD): PMD Bits are Set(2)
DC20 0.650 0.850 mA -40°C
2.0V(3)
1 MIPS
DC20a 0.650 0.850 mA +25°CDC20b 0.650 0.850 mA +85°CDC20c 0.650 0.850 mA +125°CDC20d 1.2 1.6 mA -40°C
3.3V(4)DC20e 1.2 1.6 mA +25°CDC20f 1.2 1.6 mA +85°CDC20g 1.2 1.6 mA +125°CDC23 2.6 3.4 mA -40°C
2.0V(3)
4 MIPS
DC23a 2.6 3.4 mA +25°CDC23b 2.6 3.4 mA +85°CDC23c 2.6 3.4 mA +125°CDC23d 4.1 5.4 mA -40°C
3.3V(4)DC23e 4.1 5.4 mA +25°CDC23f 4.1 5.4 mA +85°CDC23g 4.1 5.4 mA +125°CDC24 13.5 17.6 mA -40°C
2.5V(3)
16 MIPS
DC24a 13.5 17.6 mA +25°CDC24b 13.5 17.6 mA +85°CDC24c 13.5 17.6 mA +125°CDC24d 15 20 mA -40°C
3.3V(4)DC24e 15 20 mA +25°CDC24f 15 20 mA +85°CDC24g 15 20 mA +125°CDC31 13 17 μA -40°C
2.0V(3)
LPRC (31 kHz)
DC31a 13 17 μA +25°CDC31b 20 26 μA +85°CDC31c 40 50 μA +125°CDC31d 54 70 μA -40°C
3.3V(4)DC31e 54 70 μA +25°CDC31f 95 124 μA +85°CDC31g 120 260 μA +125°CNote 1: Data in �Typical� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
3: On-chip voltage regulator disabled (DISVREG tied to VDD).4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 225
PIC24FJ64GA004 FAMILY
TABLE 26-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter No. Typical(1) Max Units Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2)
DC40 150 200 μA -40°C
2.0V(3)
1 MIPS
DC40a 150 200 μA +25°CDC40b 150 200 μA +85°CDC40c 165 220 μA +125°CDC40d 250 325 μA -40°C
3.3V(4)DC40e 250 325 μA +25°CDC40f 250 325 μA +85°CDC40g 275 360 μA +125°CDC43 0.55 0.72 mA -40°C
2.0V(3)
4 MIPS
DC43a 0.55 0.72 mA +25°CDC43b 0.55 0.72 mA +85°CDC43c 0.60 0.8 mA +125°CDC43d 0.82 1.1 mA -40°C
3.3V(4)DC43e 0.82 1.1 mA +25°CDC43f 0.82 1.1 mA +85°CDC43g 0.91 1.2 mA +125°CDC47 3 4 mA -40°C
2.5V(3)
16 MIPS
DC47a 3 4 mA +25°CDC47b 3 4 mA +85°CDC47c 3.3 4.4 mA +125°CDC47d 3.5 4.6 mA -40°C
3.3V(4)DC47e 3.5 4.6 mA +25°CDC47f 3.5 4.6 mA +85°CDC47g 3.9 5.1 mA +125°CDC50 0.85 1.1 mA -40°C
2.0V(3)
FRC (4 MIPS)
DC50a 0.85 1.1 mA +25°CDC50b 0.85 1.1 mA +85°CDC50c 0.94 1.2 mA +125°CDC50d 1.2 1.6 mA -40°C
3.3V(4)DC50e 1.2 1.6 mA +25°CDC50f 1.2 1.6 mA +85°CDC50g 1.3 1.8 mA +125°CNote 1: Data in �Typical� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.2: The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from rail to
rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
3: On-chip voltage regulator disabled (DISVREG tied to VDD).4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.
DS39881C-page 226 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
DC51 4 6 μA -40°C
2.0V(3)
LPRC (31 kHz)
DC51a 4 6 μA +25°CDC51b 7 9 μA +85°CDC51c 14 18 μA +125°CDC51d 42 55 μA -40°C
3.3V(4)DC51e 42 55 μA +25°CDC51f 70 91 μA +85°CDC51g 100 180 μA +125°C
TABLE 26-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter No. Typical(1) Max Units Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2)
Note 1: Data in �Typical� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
3: On-chip voltage regulator disabled (DISVREG tied to VDD).4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 227
PIC24FJ64GA004 FAMILY
TABLE 26-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter No. Typical(1) Max Units Conditions
Power-Down Current (IPD): PMD Bits are Set, VREGS Bit is �0�(2)
DC60 0.1 1 μA -40°C
2.0V(3)
Base Power-Down Current(5)
DC60a 0.15 1 μA +25°CDC60b 3.7 12 μA +85°CDC60j 15 50 μA +125°CDC60c 0.2 1 μA -40°C
2.5V(3)DC60d 0.25 1 μA +25°CDC60e 4.2 25 μA +85°CDC60k 16 100 μA +125°CDC60f 3.3 9 μA -40°C
3.3V(4)DC60g 3.5 10 μA +25°CDC60h 9 30 μA +85°CDC60l 36 120 μA +125°CDC61 1.75 3 μA -40°C
2.0V(3)
Watchdog Timer Current: ΔIWDT(5)
DC61a 1.75 3 μA +25°CDC61b 1.75 3 μA +85°CDC61j 3.5 6 μA +125°CDC61c 2.4 4 μA -40°C
2.5V(3)DC61d 2.4 4 μA +25°CDC61e 2.4 4 μA +85°CDC61k 4.8 8 μA +125°CDC61f 2.8 5 μA -40°C
3.3V(4)DC61g 2.8 5 μA +25°CDC61h 2.8 5 μA +85°CDC61l 5.6 10 μA +125°CNote 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled
high. WDT, etc., are all switched off.3: On-chip voltage regulator disabled (DISVREG tied to VDD).4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.5: The Δ current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
DS39881C-page 228 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
DC62 8 16 μA -40°C
2.0V(3)
RTCC + Timer1 w/32 kHz Crystal: ΔRTCC ΔITI32(5)
DC62a 12 16 μA +25°CDC62b 12 16 μA +85°CDC62j 18 23 μA +125°CDC62c 9 16 μA -40°C
2.5V(3)DC62d 12 16 μA +25°CDC62e 12.5 16 μA +85°CDC62k 20 25 μA +125°CDC62f 10.3 18 μA -40°C
3.3V(4)DC62g 13.4 18 μA +25°CDC62h 14.2 18 μA +85°CDC62l 23 28 μA +125°C
TABLE 26-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter No. Typical(1) Max Units Conditions
Power-Down Current (IPD): PMD Bits are Set, VREGS Bit is �0�(2)
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off.
3: On-chip voltage regulator disabled (DISVREG tied to VDD).4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.5: The Δ current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 229
PIC24FJ64GA004 FAMILY
TABLE 26-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param No. Sym Characteristic Min Typ(1) Max Units Conditions
VIL Input Low Voltage(4)
DI10 I/O Pins VSS � 0.2 VDD VDI11 PMP Pins VSS � 0.15 VDD V PMPTTL = 1
DI15 MCLR VSS � 0.2 VDD VDI16 OSCI (XT mode) VSS � 0.2 VDD VDI17 OSCI (HS mode) VSS � 0.2 VDD VDI18 I/O Pins with I2C� Buffer VSS � 0.3 VDD V SMBus disabledDI19 I/O Pins with SMBus
BufferVSS � 0.8 V SMBus enabled
VIH Input High Voltage(4)
DI20 I/O Pins: with Analog Functions Digital Only
0.8 VDD0.8 VDD
��
VDD5.5
VV
DI21 PMP Pins: with Analog Functions Digital Only
0.25 VDD + 0.80.25 VDD + 0.8
��
VDD5.5
VV
PMPTTL = 1
DI25 MCLR 0.8 VDD � VDD VDI26 OSCI (XT mode) 0.7 VDD � VDD VDI27 OSCI (HS mode) 0.7 VDD � VDD VDI28 I/O Pins with I2C Buffer:
with Analog Functions Digital Only
0.7 VDD0.7 VDD
��
VDD5.5
VV
DI29 I/O Pins with SMBus Buffer: with Analog Functions Digital Only
2.12.1
��
VDD5.5
Vv 2.5V ≤ VPIN ≤ VDD
DI30 ICNPU CNxx Pull-up Current 50 250 400 μA VDD = 3.3V, VPIN = VSS
IIL Input Leakage Current(2,3)
DI50 I/O Ports � � +1 μA VSS ≤ VPIN ≤ VDD,Pin at high-impedance
DI51 Analog Input Pins � � +1 μA VSS ≤ VPIN ≤ VDD,Pin at high-impedance
DI55 MCLR � � +1 μA VSS ≤ VPIN ≤ VDD
DI56 OSCI � � +1 μA VSS ≤ VPIN ≤ VDD, XT and HS modes
Note 1: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.4: Refer to Table 1-2 for I/O pin buffer types.
DS39881C-page 230 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 26-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
TABLE 26-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param No. Sym Characteristic Min Typ(1) Max Units Conditions
VOL Output Low VoltageDO10 All I/O pins � � 0.4 V IOL = 8.5 mA, VDD = 3.6V
� � 0.4 V IOL = 5.0 mA, VDD = 2.0VDO16 All I/O pins � � 0.4 V IOL = 8.0 mA, VDD = 3.6V, 125°C
� � 0.4 V IOL = 4.5 mA, VDD = 2.0V, 125°C VOH Output High Voltage
DO20 All I/O pins 3 � � V IOH = -3.0 mA, VDD = 3.6V1.8 � � V IOH = -1.5 mA, VDD = 2.0V
DO26 All I/O pins 3 � � V IOH = -2.5 mA, VDD = 3.6V, 125°C 1.8 � � V IOH = -1.0 mA, VDD = 2.0V, 125°C
Note 1: Data in �Typ� column is at 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-9: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
ParamNo. Sym Characteristic Min Typ(1) Max Units Conditions
Program Flash MemoryD130 EP Cell Endurance 10000 � � E/W -40°C to +125°CD131 VPR VDD for Read VMIN � 3.6 V VMIN = Minimum operating voltageD132B VPEW VDDCORE for Self-Timed
Write2.25 � 2.75 V
D133A TIW Self-Timed Write Cycle Time
� 3 � ms
D134 TRETD Characteristic Retention 20 � � Year Provided no other specifications are violated
D135 IDDP Supply Current during Programming
� 7 � mA
Note 1: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated.
Operating Conditions: -40°C < TA < +125°C (unless otherwise stated)
ParamNo. Symbol Characteristics Min Typ Max Units Comments
VRGOUT Regulator Output Voltage � 2.5 � VCEFC External Filter Capacitor Value 4.7 10 � μF Series resistance < 3 Ohm
recommended; < 5 Ohm required.
TVREG � 10 � μs DISVREG = VSS TPWRT � 64 � ms DISVREG = VDD
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 231
PIC24FJ64GA004 FAMILY
26.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ64GA004 family AC characteristics and timingparameters.TABLE 26-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS � AC
FIGURE 26-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 26-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for ExtendedOperating voltage VDD range as described in Section 26.1 �DC Characteristics�.
Param No. Symbol Characteristic Min Typ(1) Max Units Conditions
DO50 COSC2 OSCO/CLKO pin � � 15 pF In XT and HS modes when external clock is used to drive OSCI.
DO56 CIO All I/O Pins and OSCO � � 50 pF EC mode. DO58 CB SCLx, SDAx � � 400 pF In I2C� mode.Note 1: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL = 464ΩCL = 50 pF for all pins except OSCO
15 pF for OSCO output
Load Condition 1 � for all pins except OSCO Load Condition 2 � for OSCO
DS39881C-page 232 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
FIGURE 26-4: EXTERNAL CLOCK TIMING
OSCI
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
OS20
OS25OS30 OS30
OS40 OS41
OS31OS31
Q1 Q2 Q3 Q4 Q2 Q3
TABLE 26-13: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICSStandard Operating Conditions: 2.0 to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
ParamNo. Sym Characteristic Min Typ(1) Max Units Conditions
OS10 FOSC External CLKI Frequency(External clocks allowed only in EC mode)
DC4
DC4
����
328246
MHzMHzMHzMHz
EC, -40°C ≤ TA ≤ +85°CECPLL, -40°C ≤ TA ≤ +85°CEC, -40°C ≤ TA ≤ +125°CECPLL, -40°C ≤ TA ≤ +125°C
Oscillator Frequency 331031310
������
1083233624
MHzMHzMHzkHzMHzMHz
XTXTPLL, -40°C ≤ TA ≤ +85°CHS, -40°C ≤ TA ≤ +85°CSOSCXTPLL, -40°C ≤ TA ≤ +125°CHS, -40°C ≤ TA ≤ +125°C
OS20 TOSC TOSC = 1/FOSC � � � � See parameter OS10for FOSC value
OS25 TCY Instruction Cycle Time(2) 62.5 � DC nsOS30 TosL,
TosHExternal Clock in (OSCI)High or Low Time
0.45 x TOSC � � ns EC
OS31 TosR,TosF
External Clock in (OSCI)Rise or Fall Time
� � 20 ns EC
OS40 TckR CLKO Rise Time(3) � 6 10 nsOS41 TckF CLKO Fall Time(3) � 6 10 nsNote 1: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at �Min.� values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the �Max.� cycle time limit is �DC� (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 233
PIC24FJ64GA004 FAMILY
TABLE 26-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
ParamNo. Sym Characteristic(1) Min Typ(2) Max Units Conditions
OS50 FPLLI PLL Input Frequency Range
3
3
�
�
8
6
MHz
MHz
ECPLL, HSPLL, XTPLL modes, -40°C ≤ TA ≤ +85°CECPLL, HSPLL, XTPLL modes, -40°C ≤ TA ≤ +125°C
OS51 FSYS PLL Output Frequency Range
88
��
3224
MHzMHz
-40°C ≤ TA ≤ +85°C-40°C ≤ TA ≤ +125°C
OS52 TLOCK PLL Start-up Time (Lock Time)
� � 2 ms
OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over 100 ms periodNote 1: These parameters are characterized but not tested in manufacturing.
2: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param No. Characteristic Min Typ Max Units Conditions
Internal FRC Accuracy @ 8 MHz(1)
F20 FRC -2 � 2 % 25°C3.0V ≤ VDD ≤ 3.6V
-5 � 5 % -40°C ≤ TA ≤ +125°CNote 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
TABLE 26-16: INTERNAL RC ACCURACY
AC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
ParamNo. Characteristic Min Typ Max Units Conditions
LPRC @ 31 kHz(1)
F21 -15 � 15 % 25°C3.0V ≤ VDD ≤ 3.6V-15 � 15 % -40°C ≤ TA ≤ +85°C
-20 � 20 % 125°CNote 1: Change of LPRC frequency as VDD changes.
DS39881C-page 234 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
FIGURE 26-5: CLKO AND I/O TIMING CHARACTERISTICSNote: Refer to Figure 26-3 for load conditions.
I/O Pin(Input)
I/O Pin(Output)
DI35
Old Value New Value
DI40
DO31DO32
TABLE 26-17: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
ParamNo. Sym Characteristic Min Typ(1) Max Units Conditions
DO31 TIOR Port Output Rise Time � 10 25 nsDO32 TIOF Port Output Fall Time � 10 25 nsDI35 TINP INTx pin High or Low
Time (output)20 � � ns
DI40 TRBP CNx High or Low Time (input)
2 � � TCY
Note 1: Data in �Typ� column is at 3.3V, 25°C unless otherwise stated.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 235
PIC24FJ64GA004 FAMILY
TABLE 26-18: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V(unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param No. Symbol Characteristic Min. Typ Max. Units Conditions
Device SupplyAD01 AVDD Module VDD Supply Greater of
VDD � 0.3or 2.0
� Lesser ofVDD + 0.3
or 3.6
V
AD02 AVSS Module VSS Supply VSS � 0.3 � VSS + 0.3 VReference Inputs
AD05 VREFH Reference Voltage High AVSS + 1.7 � AVDD VAD06 VREFL Reference Voltage Low AVSS � AVDD � 1.7 VAD07 VREF Absolute Reference
Voltage AVSS � 0.3 � AVDD + 0.3 V
Analog InputAD10 VINH-VINL Full-Scale Input Span VREFL � VREFH V (Note 2)AD11 VIN Absolute Input Voltage AVSS � 0.3 � AVDD + 0.3 V �AD12 VINL Absolute VINL Input
Voltage AVSS � 0.3 AVDD/2 V
AD17 RIN Recommended Impedance of Analog Voltage Source
� � 2.5K Ω 10-bit
ADC AccuracyAD20b Nr Resolution � 10 � bitsAD21b INL Integral Nonlinearity � ±1 <±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3VAD22b DNL Differential Nonlinearity � ±1 <±1.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3VAD23b GERR Gain Error � ±1 ±3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3VAD24b EOFF Offset Error � ±1 ±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3VAD25b � Monotonicity(1) � � � � GuaranteedNote 1: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.
DS39881C-page 236 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 26-19: ADC CONVERSION TIMING REQUIREMENTS(1)AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V(unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param No. Symbol Characteristic Min. Typ Max. Units Conditions
Clock ParametersAD50 TAD ADC Clock Period 75 � � ns TCY = 75 ns, AD1CON3
in default stateAD51 tRC ADC Internal RC Oscillator
Period� 250 � ns
Conversion RateAD55 tCONV Conversion Time � 12 � TAD
AD56 FCNV Throughput Rate � � 500 ksps AVDD ≥ 2.7VAD57 tSAMP Sample Time � 1 � TAD
Clock ParametersAD61 tPSS Sample Start Delay from setting
Sample bit (SAMP)2 � 3 TAD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 237
PIC24FJ64GA004 FAMILY
NOTES:DS39881C-page 238 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
27.0 PACKAGING INFORMATION27.1 Package Marking InformationLegend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week �01�)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.
3e
28-Lead SOIC (.300�)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC24FJ16GA002/SO0810017
28-Lead QFN
XXXXXXXXXXXXXXXXYYWWNNN
Example
24FJ48GA002/ML0810017
3e
3e
28-Lead SPDIP
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
-I/SPPIC24FJ16GA002
08100173e
28-Lead SSOP
XXXXXXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
24FJ16GA002/SS
08100173e
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 239
PIC24FJ64GA004 FAMILY
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
24FJ32GA
Example
004-I/ML0810017
44-Lead TQFP
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
24FJ32GA004-I/PT
0810017
3e
3e
DS39881C-page 240 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
27.2 Package Details The following sections give the technical details of the packages.��������� ������������� ��� ��������������������
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© 2008 Microchip Technology Inc. Preliminary DS39881C-page 241
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NOTES:DS39881C-page 250 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (March 2007)Original data sheet for the PIC24FJ64GA004 family ofdevices.
Revision B (March 2007)Changes to Table 26-8; packaging diagrams updated.
Revision C (January 2008)� Update of electrical specifications to include DC
characteristics for Extended Temperature devices.
� Update for A/D converter chapter to include information on internal band gap voltage reference.
� Added �Appendix B: �Additional Guidance for PIC24FJ64GA004 Family Applications�.
� General revisions to incorporate corrections included in document errata to date (DS80333).
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 251
PIC24FJ64GA004 FAMILY
APPENDIX B: ADDITIONAL GUIDANCE FOR PIC24FJ64GA004 FAMILY APPLICATIONS
B.1 Additional Methods for Power Reduction
Devices in the PIC24FJ64GA004 family include a num-ber of core features to significantly reduce the applica-tion�s power requirements. For truly power-sensitiveapplications, it is possible to further reduce theapplication�s power demands by taking advantage ofthe device�s regulator architecture. These methodshelp decrease power in two ways: by disabling theinternal voltage regulator to eliminate its power con-sumption, and by reducing the voltage on VDDCORE tolower the device�s dynamic current requirements.Using these methods, it is possible to reduce Sleepcurrents (IPD) from 3.5 μA to 250 nA (typical values,refer to specifications DC60d and DC60g inTable 26-6). For dynamic power consumption, thereduction in VDDCORE from 2.5V, provided by theregulator, to 2.0V can provide a power reduction ofabout 30%.
When using a regulated power source or a battery witha constant output voltage, it is possible to decreasepower consumption by disabling the regulator. In thiscase (Figure B-1), a simple diode can be used toreduce the voltage from 3V or greater to the 2V-2.5Vrequired for VDDCORE. This method is only advised onpower supplies, such as Lithium Coin cells, whichmaintain a constant voltage over the life of the battery.
FIGURE B-1: POWER REDUCTION EXAMPLE FOR CONSTANT VOLTAGE SUPPLIES
A similar method can be used for non-regulatedsources (Figure B-2). In this case, it can be beneficialto use a low quiescent current external voltage regula-tor. Devices such as the MCP1700 consume only 1 μAto regulate to 2V or 2.5V, which is lower than thecurrent required to power the internal voltage regulator.
FIGURE B-2: POWER REDUCTION EXAMPLE FOR NON-REGULATED SUPPLIES
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DS39881C-page 252 Preliminary © 2008 Microchip Technology Inc.
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INDEXAA/D Converter
Analog Input Model ................................................... 190Transfer Function...................................................... 191
Additional Guidance for Family Applications..................... 252Assembler
MPASM Assembler................................................... 210
BBlock Diagrams
10-Bit High-Speed A/D Converter............................. 184Accessing Program Memory with Table Instructions .. 39Addressable PMP Example ...................................... 166CALL Stack Frame...................................................... 37Comparator Operating Modes .................................. 193Comparator Voltage Reference ................................ 197CPU Programmer�s Model .......................................... 19CRC Reconfigured for Polynomial ............................ 180CRC Shifter Details................................................... 179Data Access From Program Space
Address Generation............................................ 38I2C Module ................................................................ 144Input Capture ............................................................ 125Legacy PMP Example............................................... 166On-Chip Regulator Connections ............................... 204Output Compare ....................................................... 130PIC24F CPU Core ...................................................... 18PIC24FJ64GA004 Family (General) ........................... 10PMP
Master Port Examples .............................. 166�168PMP Module Overview ............................................. 159PSV Operation ............................................................ 40Reset System.............................................................. 47RTCC ........................................................................ 169Shared I/O Port Structure ........................................... 97Simplified UART........................................................ 151SPI Master/Frame Master Connection...................... 141SPI Master/Frame Slave Connection........................ 141SPI Master/Slave Connection
(Enhanced Buffer Mode)................................... 140SPI Master/Slave Connection
(Standard Mode)............................................... 140SPI Slave/Frame Master Connection........................ 141SPI Slave/Frame Slave Connection.......................... 141SPIx Module (Enhanced Mode) ................................ 135SPIx Module (Standard Mode).................................. 134System Clock Diagram ............................................... 87Timer1....................................................................... 117Timer2 and Timer4 (16-Bit Modes) ........................... 121Timer2/3 and Timer4/5 (32-Bit Mode)....................... 120Timer3 and Timer5 (16-Bit Modes) ........................... 121Watchdog Timer (WDT) ............................................ 206
CC Compilers
MPLAB C18 .............................................................. 210MPLAB C30 .............................................................. 210
Code ExamplesBasic Clock Switching Example ................................. 93Configuring UART 1 Input and Output
Functions (PPS) ............................................... 102Erasing a Program Memory Block.............................. 44I/O Port Read/Write .................................................... 98Initiating a Programming Sequence ........................... 45Loading the Write Buffers ........................................... 45Single-Word Flash Programming ............................... 46
Code Protection................................................................ 206Configuration Bits ............................................................. 199Core Features....................................................................... 7CPU
ALU............................................................................. 21Control Registers........................................................ 20Core Registers............................................................ 19Programmer�s Model .................................................. 17
CRCCRCXOR Register.................................................... 182Operation in Power Save Modes.............................. 180User Interface ........................................................... 180
Customer Change Notification Service............................. 256Customer Notification Service .......................................... 256Customer Support............................................................. 256
DData Memory
Address Space ........................................................... 25Memory Map............................................................... 25Near Data Space ........................................................ 26Organization ............................................................... 26SFR Space ................................................................. 26Software Stack ........................................................... 37
Development Support ....................................................... 209Device Features (Summary)................................................. 9DISVREG Pin ................................................................... 204Doze Mode ......................................................................... 96
EElectrical Characteristics
A/D Specifications .................................................... 236Absolute Maximum Ratings...................................... 221Current Specifications ...................................... 225�229I/O Pin Specifications ....................................... 230�231Internal Clock Specifications .................................... 234Load Conditions and Requirements for
AC Characteristics............................................ 232Program Memory Specifications............................... 231Thermal Operating Conditions.................................. 223V/F Graphs ............................................................... 222Voltage Ratings ........................................................ 224Voltage Regulator Specifications.............................. 231
EquationsA/D Clock Conversion Period ................................... 190Baud Rate Reload Calculation ................................. 145Calculating the PWM Period..................................... 128Calculation for Maximum PWM Resolution .............. 128Device and SPI Clock Speed Relationship............... 142UART Baud Rate with BRGH = 0............................. 152UART Baud Rate with BRGH = 1............................. 152
Errata .................................................................................... 6
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 253
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FFlash Configuration Words.................................. 24, 199�202Flash Program Memoryand Table Instructions................................................. 41Enhanced ICSP Operation.......................................... 42JTAG Operation .......................................................... 42Programming Algorithm .............................................. 44RTSP Operation.......................................................... 42Single-Word Programming.......................................... 46
II/O Ports
Analog Port Configuration........................................... 98Input Change Notification............................................ 98Open-Drain Configuration ........................................... 98Parallel (PIO) .............................................................. 97Peripheral Pin Select .................................................. 99Pull-ups ....................................................................... 98
I2CClock Rates............................................................... 145Peripheral Remapping Options ................................. 143Reserved Addresses................................................. 145Slave Address Masking ............................................ 145
Idle Mode ............................................................................ 96Instruction Set
Overview ................................................................... 215Summary................................................................... 213
Instruction-Based Power-Saving Modes ............................. 95Inter-Integrated Circuit. See I2C........................................ 143Internet Address................................................................ 256Interrupts
Alternate Interrupt Vector Table (AIVT) ...................... 53and Reset Sequence .................................................. 53Implemented Vectors .................................................. 55Interrupt Vector Table (IVT) ........................................ 53Registers............................................................... 56�84Setup and Service Procedures ................................... 85Trap Vectors ............................................................... 54Vector Table................................................................ 54
JJTAG Interface .................................................................. 206
MMicrochip Internet Web Site .............................................. 256MPLAB ASM30 Assembler, Linker, Librarian ................... 210MPLAB ICD 2 In-Circuit Debugger.................................... 211MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator .................................... 211MPLAB Integrated Development
Environment Software............................................... 209MPLAB PM3 Device Programmer..................................... 211MPLAB REAL ICE In-Circuit Emulator System................. 211MPLINK Object Linker/MPLIB Object Librarian ................ 210
NNear Data Space................................................................. 26
OOscillator Configuration
Clock Switching........................................................... 92Sequence............................................................ 93
Initial Configuration on POR ....................................... 88Oscillator Modes ......................................................... 88
Output ComparePWM Mode............................................................... 128
Period and Duty Cycle Calculation ................... 129Single Output Pulse Generation ............................... 127
PPackaging
Details....................................................................... 241Marking..................................................................... 239
Parallel Master Port. See PMP. ........................................ 159Peripheral Enable Bits ........................................................ 96Peripheral Module Disable (PMD) bits................................ 96Peripheral Pin Select (PPS)................................................ 99
Available Peripherals and Pins ................................... 99Configuration Control................................................ 101Considerations for Use ............................................. 102Input Mapping ............................................................. 99Mapping Exceptions ................................................. 101Output Mapping ........................................................ 100Peripheral Priority ....................................................... 99Registers .......................................................... 103�116
PICSTART Plus Development Programmer..................... 212Pinout Descriptions....................................................... 11�16PMP
Master Port Examples ...................................... 166�168Power-Saving Features ...................................................... 95Power-up Requirements ................................................... 205Product Identification System ........................................... 258Program Memory
Access Using Table Instructions................................. 39Address Construction ................................................. 37Address Space ........................................................... 23Flash Configuration Words ......................................... 24Memory Map............................................................... 23Organization ............................................................... 24Program Space Visibility............................................. 40
Pulse-Width Modulation. See PWM.................................. 128
RReader Response............................................................. 257Register Maps
A/D Converter (ADC) .................................................. 33Clock Control .............................................................. 36CPU ............................................................................ 27CRC............................................................................ 34Dual Comparator ........................................................ 34I2C .............................................................................. 30ICN ............................................................................. 27Input Capture.............................................................. 29Interrupt Controller...................................................... 28NVM............................................................................ 36Output Compare ......................................................... 30Pad Configuration ....................................................... 32Parallel Master/Slave Port .......................................... 33Peripheral Pin Select .................................................. 35PMD............................................................................ 36PORTA ....................................................................... 32PORTB ....................................................................... 32PORTC ....................................................................... 32Real-Time Clock and Calendar (RTCC) ..................... 34SPI .............................................................................. 31Timers......................................................................... 29UART.......................................................................... 31
DS39881C-page 254 Preliminary © 2008 Microchip Technology Inc.
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RegistersAD1CHS (A/D Input Select) ...................................... 188AD1CON1 (A/D Control 1) ........................................ 185AD1CON2 (A/D Control 2) ........................................ 186AD1CON3 (A/D Control 3) ........................................ 187AD1CSSL (A/D Input Scan Select) ........................... 189AD1PCFG (A/D Port Configuration).......................... 189ALCFGRPT (Alarm Configuration)............................ 173ALMINSEC (Alarm Minutes and
Seconds Value) ................................................ 177ALMTHDY (Alarm Month and Day Value) ................ 176ALWDHR (Alarm Weekday and Hours Value).......... 176CLKDIV (Clock Divider) .............................................. 91CMCON (Comparator Control) ................................. 194CORCON (Core Control) ............................................ 57CORCON (CPU Control) ............................................ 21CRCCON (CRC Control) .......................................... 181CRCXOR (CRC XOR Polynomial)............................ 182CVRCON (Comparator Voltage
Reference Control) ........................................... 198CW1 (Flash Configuration Word 1)........................... 200CW2 (Flash Configuration Word 2)........................... 202DEVID (Device ID) .................................................... 203DEVREV (Device Revision) ...................................... 203I2CxCON (I2Cx Control) ........................................... 146I2CxMSK (I2Cx Slave Mode Address Mask) ............ 150I2CxSTAT (I2Cx Status) ........................................... 148ICxCON (Input Capture x Control) ............................ 126IECn (Interrupt Enable Control 0-4) ...................... 65�69IFSn (Interrupt Flag Status 0-4) ............................ 60�64INTCON1 (Interrupt Control 1).................................... 58INTCON2 (Interrupt Control 2).................................... 59IPCn (Interrupt Priority Control 0-18) .................... 70�84MINSEC (RTCC Minutes and Seconds Value)......... 175MTHDY (RTCC Month and Day Value) .................... 174NVMCON (Flash Memory Control) ............................. 43OCxCON (Output Compare x Control) ..................... 131OSCCON (Oscillator Control) ..................................... 89OSCTUN (FRC Oscillator Tune)................................. 92PADCFG1 (Pad Configuration Control) ............ 165, 172PMADDR (PMP Address) ......................................... 163PMAEN (PMP Enable).............................................. 163PMCON (PMP Control)............................................. 160PMMODE (PMP Mode)............................................. 162PMPSTAT (PMP Status)........................................... 164RCFGCAL (RTCC Calibration and
Configuration) ................................................... 171RCON (Reset Control) ................................................ 48RPINRn (PPS Input Mapping 0-23) .................. 103�109RPORn (PPS Output Mapping 0-12) ................ 110�116SPIxCON1 (SPIx Control 1)...................................... 138SPIxCON2 (SPIx Control 2)...................................... 139SPIxSTAT (SPIx Status and Control) ....................... 136SR (ALU STATUS) ............................................... 20, 57T1CON (Timer1 Control)........................................... 118TxCON (Timer2 and Timer4 Control)........................ 122TyCON (Timer3 and Timer5 Control)........................ 123UxMODE (UARTx Mode).......................................... 154UxRXREG (UARTx Receive).................................... 158UxSTA (UARTx Status and Control)......................... 156UxTXREG (UARTx Transmit) ................................... 158WKDYHR (RTCC Weekday and
Hours Value) ..................................................... 175YEAR (RTCC Year Value) ........................................ 174
ResetsClock Source Selection .............................................. 49Delay Times................................................................ 50RCON Flags Operation .............................................. 49SFR States ................................................................. 51
Revision History................................................................ 251RTCC
Alarm Configuration.................................................. 178Calibration ................................................................ 177Register Mapping ..................................................... 170
SSerial Peripheral Interface. See SPI. ................................ 133SFR Space ......................................................................... 26Selective Peripheral Power Control .................................... 96Sleep Mode ........................................................................ 95Software Simulator (MPLAB SIM) .................................... 210Software Stack ................................................................... 37
TTimer1 .............................................................................. 117Timer2/3 and Timer4/5 ..................................................... 119Timing Diagrams
CLKO and I/O Timing ............................................... 235External Clock Timing............................................... 233
UUART
Baud Rate Generator (BRG) .................................... 152Break and Sync Sequence ....................................... 153IrDA Support ............................................................. 153Operation of UxCTS and UxRTS
Control Pins ...................................................... 153Receiving.................................................................. 153Transmitting.............................................................. 153
VVDDCORE/VCAP pin............................................................ 204Voltage Regulator (On-Chip) ............................................ 204
and BOR................................................................... 205and POR................................................................... 204Standby Mode .......................................................... 205Tracking Mode.......................................................... 204
WWatchdog Timer (WDT).................................................... 205
Windowed Operation ................................................ 206WWW Address ................................................................. 256WWW, On-Line Support ....................................................... 6
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 255
PIC24FJ64GA004 FAMILY
NOTES:DS39881C-page 256 Preliminary © 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
THE MICROCHIP WEB SITEMicrochip provides online support via our WWW site atwww.microchip.com. This web site is used as a meansto make files and information easily available tocustomers. Accessible by using your favorite Internetbrowser, the web site contains the followinginformation:
� Product Support � Data sheets and errata, application notes and sample programs, design resources, user�s guides and hardware support documents, latest software releases and archived software
� General Technical Support � Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
� Business of Microchip � Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICEMicrochip�s customer notification service helps keepcustomers current on Microchip products. Subscriberswill receive e-mail notification whenever there arechanges, updates, revisions or errata related to aspecified product family or development tool of interest.
To register, access the Microchip web site atwww.microchip.com, click on Customer ChangeNotification and follow the registration instructions.
CUSTOMER SUPPORTUsers of Microchip products can receive assistancethrough several channels:
� Distributor or Representative� Local Sales Office� Field Application Engineer (FAE)� Technical Support� Development Systems Information Line
Customers should contact their distributor,representative or field application engineer (FAE) forsupport. Local sales offices are also available to helpcustomers. A listing of sales offices and locations isincluded in the back of this document.
Technical support is available through the web siteat: http://support.microchip.com
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 257
PIC24FJ64GA004 FAMILY
READER RESPONSEIt is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentationcan better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader ResponseTotal Pages Sent ________
From: Name
CompanyAddressCity / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS39881CPIC24FJ64GA004 Family
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39881C-page 258 Preliminary © 2008 Microchip Technology Inc.
© 2008 Microchip Technology Inc. Preliminary DS39881C-page 259
PIC24FJ64GA004 FAMILY
PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Architecture 24 = 16-bit modified Harvard without DSP
Flash Memory Family FJ = Flash program memory
Product Group GA0 = General purpose microcontrollers
Pin Count 02 = 28-pin04 = 44-pin
Temperature Range E = -40°C to +125°C (Extended)I = -40°C to +85°C (Industrial)
Package SP = SPDIPSO = SOICSS = SSOPML = QFNPT = TQFP
Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)ES = Engineering Sample
Examples:a) PIC24FJ32GA002-I/ML:
General purpose PIC24F, 32-Kbyte program memory, 28-pin, Industrial temp.,QFN package.
b) PIC24FJ64GA004-E/PT:General purpose PIC24F, 64-Kbyte program memory, 44-pin, Extended temp.,TQFP package.
Microchip TrademarkArchitectureFlash Memory FamilyProgram Memory Size (KB)Product GroupPin Count
Temperature RangePackagePattern
PIC 24 FJ 64 GA0 04 T - I / PT - XXX
Tape and Reel Flag (if applicable)
DS39881C-page 260 Preliminary © 2008 Microchip Technology Inc.
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