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FPGAS
C. Sisterna DSDA 1
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Celda de Configuración del FPGA
Elemento básico no-lógico
2 DSDA
Determina la configuración de los
elementos de ruteo e interconexiones
Determina la configuración de cada
elemento lógico
C. Sisterna
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Celdas de Configuración del FPGA
Tipos de Celdas
SRAM
Anti-Fuse
Flash
Flash y SRAM
3 DSDA C. Sisterna
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Celda de Configuración SRAM
4 DSDA
La configuración de los elementos lógicos y los de
ruteo e interconexión son almacenados en celdas
SRAMs
Ventajas:
Rápida y fácil actualización
Infinitamente reprogramable
Programable en circuito (In System Programable)
Proceso de fabricación estándar
Costos muy bajos
Proceso súper-comprobado
Alto rendimiento
C. Sisterna
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Celda de Configuración SRAM
5 DSDA
Desventajas:
Necesidad de una memoria de configuración externa
Retardos en ruteo largos debido al retardo de la celda
SRAM
Celda volátil
Simple glitch en Vcc desconfigura el FPGA
Tiempo de configuración lento ~500ms
Inseguridad debido a la conexión FPGA-Memoria de
configuración que puede ser ‘leída’
C. Sisterna
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Celda de Configuración Anti-Fuse
6 DSDA
La configuración de los elementos lógicos y los de
ruteo e interconexión son almacenados en celdas
Anti-Fuse (ACTEL)
C. Sisterna
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Celda de Configuración Anti-Fuse
7 DSDA
Ventajas:
Retardos de conexiones de ruteo son pequeños
No es volátil
No sensibles a bombardeo de partículas iónicas
Muy usados en sistemas espaciales
C. Sisterna
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Celda de Configuración Anti-Fuse
8 DSDA
Desventajas:
One-Time-Programmable (OTP)
Proceso de verificacion muy largo y riguroso
Proceso muy caro
Proceso de fabricación específico
Costos elevados
No sensibles a bombardeo de partículas iónicas
Muy usados en sistemas espaciales
C. Sisterna
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Celda de Configuración Flash
9 DSDA
La configuración de los elementos lógicos y los de
ruteo e interconexión son almacenados en celdas
Flash
C. Sisterna
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Celda de Configuración Flash
10 DSDA
Ventajas:
Retardos de conexiones de ruteo son pequeños
No es volátil
Sensibilidad baja a bombardeo de partículas iónicas
Usados en sistemas espaciales
C. Sisterna
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Celda de Configuración Flash
11 DSDA
Desventajas:
FPGA es bastante caro
Proceso se esta haciendo mas común últimamente
Proceso de reconfiguración bastante largo (~3-5 seg)
C. Sisterna
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Celda de Configuración Flash-SRAM
12 DSDA
Ventajas:
Tiempo de configuración es bastante bajo (~<1ms)
Prácticamente ‘no es volátil’
Se pueden configurar solo las celdas SRAM
Durante el proceso de debug o prototipo
No se necesita una memoria de configuración externa
Menos espacio en el PCB
Sistema no vulnerable – Sistema seguro
C. Sisterna
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Celda de Configuración Flash-SRAM
13 DSDA
Desventajas:
FPGA es caro
Proceso se esta haciendo mas común últimamente
C. Sisterna
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Celda de Configuración Flash-SRAM
14 DSDA
Las celdas Flash se usan para guardar los datos de
configuración del FPGA
Las celdas SRAM para la configuración de los
elementos lógicos y los de ruteo e interconexión
Cuando de alimenta el FPGA, las celdas SRAM se
configuran en forma casi instantanea desde las
celdas Flash.
C. Sisterna
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Comparación Tipos de Celdas
DSDA 15 C. Sisterna
SRAM Anti_fuse Flash
Tecnología Ultima
Una o más
generación
atrás
Una o más
generación atrás
Velocidad Más lenta Mejor Más lenta
Volátil Si No No
Potencia Varía/Peor Baja Media Baja
Densidad Mejor Segunda Mejor Media
Tolerancia a la
Radiación Peor Mejor Media
Config. Externa Si No No
Tamaño celda ruteo 1 1/10 1/7
Memoria Externa Si No No
Reprogramable Si No Si
Instant-On No Si Si
Seguridad
Encriptado->
Buena, Sino
MALA
Muy buena Muy Buena
Tamano Celda
Config.
Grande
(6 Transistores) Muy pequeña
Media-Baja
(2 transistores)
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CYCLONE IV FPGA
C. Sisterna 16 DSDA
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Cyclone IV – General View
C. Sisterna DSDA 17
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Cyclone FPGA Familiy
Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs
Built on an optimized low-power process, the Cyclone IV
device family offers the following two variants:
Cyclone IV E—lowest power, high functionality with the lowest cost
Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125 Gbps transceivers
C. Sisterna 18 DSDA
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Cyclone IV E Family
C. Sisterna 19 DSDA
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Cyclone IV GX Family
C. Sisterna 20 DSDA
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Cyclone Core Fabric
Logic Elements: 4-input look up tables
M9K Memory Blocks: 9Kbits of
embedded SRAM
Embedded Multiplier: 18x18 or two 9x9
multipliers in a single block
C. Sisterna 21 DSDA
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Cyclone I/O Features
Cyclone device I/O supports:
◦ Programmable bus hold
◦ Programmable pull-up resistors
◦ Programmable delay
◦ Programmable drive strength
◦ Programmable slew rate control
◦ Hot socketing
◦ Calibrated on-chip series termination or dirves
impedance matching
◦ Cyclone GX offers high-speed transceiver I/Os
C. Sisterna 22 DSDA
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Cyclone Clock Management
Include up to 30 global clock network (GCLK)
Include up to 8 PLLs, with five outputs per PLL
Cyclone IV GX support:
◦ Multipurpose PLL: for clocking the transceiver blocks (they can be used as general-purpose clock)
◦ General purpose PLL: fo general applications in the fabric and periphery
C. Sisterna 23 DSDA
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External Memory Interface
Cyclone IV supports SDR, DDR, DDR2
SDRAM and QDRII SRAM interfaces
Support the use of error correction
coding (ECC) bits on DDR and DDR2
SDRAM interfaces
C. Sisterna 24 DSDA
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Packaging Ordering Information
C. Sisterna 25 DSDA
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LOGIC ELEMENT
C. Sisterna DSDA 26
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Logic Elements (LE)
Each LE has the following features:
A four-input look-up table (LUT), which can implement any function of
four variables
A programmable register
A carry chain connection
A register chain connection
The ability to drive the following interconnects:
◦ Local
◦ Row
◦ Column
◦ Register chain
◦ Direct link
Register packing support
Register feedback support
C. Sisterna 27 DSDA
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Logic Element
C. Sisterna 28 DSDA
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Logic Array Block
Logic array blocks (LABs) contain groups of LEs
Each LAB consists of the following features:
◦ 16 LEs
◦ LAB control signals
◦ LE carry chains
◦ Register chains
◦ Local interconnect
C. Sisterna 29 DSDA
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LAB Structure
C. Sisterna 30 DSDA
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ROUTING
C. Sisterna DSDA 31
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Interconnect - Routing
DSDA 32 C. Sisterna
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Interconnect - Routing
DSDA 33
Transistor de Paso
M
Y 0
Y
PIP
C. Sisterna
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Interconnect - Routing
DSDA 34 C. Sisterna
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Interconnect - Routing
35 DSDA C. Sisterna
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Interconnect - Routing
DSDA 36 C. Sisterna
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Interconnect - Routing
DSDA 37 C. Sisterna
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EMBEDDED MEMORY
C. Sisterna DSDA 38
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Embedded Memory
M9K blocks support the following features: 8,192 memory bits per block (9,216 bits per block including parity)
Independent read-enable (rden) and write-enable (wren) signals for each port
Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs
Variable port configurations
Single-port and simple dual-port modes support for all port widths
True dual-port (one read and one write, two reads, or two writes) operation
Byte enables for data input masking during writes
Two clock-enable control signals for each port (port A and port B)
Initialization file to pre-load memory content in RAM and ROM modes
C. Sisterna DSDA 39
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Embedded Memory Modes
Cyclone IV devices M9K memory blocks allow to implement fully-synchronous SRAM memory in multiple modes of operation.
M9K memory blocks support the following modes:
◦ Single-port
◦ Simple dual-port
◦ True dual-port
◦ Shift-register
◦ ROM
◦ FIFO
C. Sisterna DSDA 40
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Single Port Mode
C. Sisterna DSDA 41
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Simple Dual Port
C. Sisterna DSDA 42
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True Dual Port
C. Sisterna DSDA 43
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Embedded Multitplier
Each embedded multiplier consists of the
following elements:
◦ Multiplier stage
◦ Input and output registers
◦ Input and output interfaces
C. Sisterna DSDA 44
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Embedded Multiplier
C. Sisterna DSDA 45
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INPUT/OUTPUT FEATURES
C. Sisterna DSDA 46
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Cyclone IV I/O Elements
C. Sisterna DSDA 47
SDR Mode
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I/O Element Features
Programmable Current Strength
Slew Rate Control
Open-Drain Output
Bus Hold
Programmable Pull-Up Resistor
Programmable Delay
On Chip Termination (resistor)
C. Sisterna DSDA 48
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I/O Standards
C. Sisterna DSDA 49
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I/O Standards
C. Sisterna DSDA 50
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I/O Banks
C. Sisterna DSDA 51
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I/O LVDS Implementation
C. Sisterna DSDA 52
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DDR Input Registers
C. Sisterna DSDA 53
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DDR Output Registers
C. Sisterna DSDA 54
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FPGA CONFIGURATION
C. Sisterna DSDA 55
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Active Serial Configuration
C. Sisterna DSDA 56
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Configuring Multiple Devices
C. Sisterna DSDA 57
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Pasive Serial Configuration
C. Sisterna DSDA 58
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PS Configuration with a Micro
C. Sisterna DSDA 59
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JTAG Configuration
C. Sisterna DSDA 60
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Active Parallel Configuration
C. Sisterna DSDA 61