February 2013Revision: EB81_01.1
CSI2 to Parallel Bridge Board
User’s Guide
2
CSI2 to Parallel Bridge Board User’s Guide
IntroductionThe CSI2 to Parallel Bridge Board comprises a compact, low cost, MIPI CSI2 (Camera Serial Interface) image sen-sor, lens and lens housing with adjustable focus, that can bolt directly onto the Lattice HDR-60 Base Board or the MachXO2™ Dual Sensor Interface Board. Both the CSI2 to Parallel Bridge Board and the MachXO2 Dual Sensor Interface Board are designed to work together. These boards plug into the HDR-60 Base Board to allow for a dem-onstration. The CSI2 to Parallel Bridge Board is designed to use the Sony IMX169 CMOS Digital Image Sensors which feature:
• Up to 13 megapixels
• HD video (1080p30 mode configurable)
• Selectable video or single frame modes
• MIPI CSI2 output, either two or four data lanes
Read more about the image sensor specifications in the Sony IMX169 data sheet.
FeaturesKey features of the CSI2 to Parallel Bridge Board include:
• Sony IMX169 CMOS Digital Image Sensor
• Lens: F/1.59, <7% distortion, with minimized flare, halo, and ghosting
• Lens holder with adjustable focus
• CSI2 or parallel signal connections to the MachXO2 Dual Sensor Interface Board or HDR-60 Base Board
• Selectable on-board 27.000 MHz MEMs oscillator, or HDR-60 Base Board oscillator
• Power status LEDs with one user-defined LED
General DescriptionThe CSI2 to Parallel Bridge Board has been designed for use on the MachXO2 Dual Interface Sensor Board and the HDR-60 Base Board. The CSI2 to Parallel Bridge Board contains the camera sensor portion, while the MachXO2 Dual Sensor Interface Board performs the CSI2 to parallel conversion. The HDR-60 Base Board allows the user to see an image on a HDMI monitor. See RD1146, MIPI CSI2 to CMOS Parallel Sensor Bridge, for more information concerning a related demo.
Initial Setup and HandlingThe following is recommended reading prior to removing the CSI2 to Parallel Bridge Board from the static shielding bag and may or may not apply to your particular use of the board.
CAUTION: The devices on the boards can be damaged by improper handling.
The devices on the evaluation boards contain fairly robust ESD (Electro Static Discharge) protection structures within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example of ESD characterization requirements). Even so, the devices are static-sensitive to conditions that exceed their designed-in protection. For example: higher static voltages, as well as lower voltages with lower series resistance or larger capacitance than the respective ESD specifications require can potentially damage or degrade the devices on the evaluation board.
As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while han-dling the evaluation boards when they are removed from the static shielding bag. If you will not be using the boards for a while, it is best to put them back in the static shielding bag. Please save the static shielding bag and packing box for future storage of the boards when they are not in use.
3
CSI2 to Parallel Bridge Board User’s Guide
When reaching for the boards, it is recommended that you first touch the outside shield portion of the J11 BNC connector on the HDR-60 Base Board. If the CSI2 to Parallel Bridge Board is not installed on the HDR-60 Base Board, then when reaching for the CSI2 to Parallel Bridge Board, it is recommended that you first touch the outside edge of the mounting holes on the CSI2 to Parallel Bridge Board. This will neutralize any static voltage difference between your body and the board prior to any contact with signal I/O.
CAUTION: To minimize the possibility of ESD damage, the first and last electrical connection to the board, should be from test equipment chassis ground to the J11 BNC shield GND on the HDR-60 Base Board.
Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment to the J11 BNC shield GND on the HDR-60 Base Board. Connecting the board ground to test equipment chassis ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged should be the chassis GND connection to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation board.
If you are holding or carrying the board while it is not in a static shielding bag, please keep one finger on the J11 BNC shield GND on the HDR-60 Base Board. If carrying the CSI2 to Parallel Bridge Board alone, keep one finger one of the mounting holes. This will keep the board at the same voltage potential as your body until you can pick up the static shielding bag and put the board back in it.
Electrical, Mechanical, and Environmental SpecificationsThe nominal board dimensions are 42mm x 42mm (1.654” x 1.654”). Additional mechanical board dimension infor-mation is included on the mechanical drawing shown in Appendix A, Figure . On the physical board itself, connec-tors include pin 1 indictors as either an arrow, or triangle point near pin 1 on the outer layer silk screen. The environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: <95% without condensation
4
CSI2 to Parallel Bridge Board User’s Guide
Functional DescriptionFigure 1. CSI2 to Parallel Bridge Board Revision B
Voltage RegulatorsThe CSI2 to Parallel Bridge Board power is supplied by the 5V DC power applied at connectors J7 and J8, pins 1, 2, 39 and 40. The on-board linear voltage regulators then provide the necessary supply voltages to power the sen-sor: 2.7V, VDDIO, 1.2V, 1.8V, 2.5V and 3.3V. The regulator in location U10 can be configured as shown in Table 1.
Table 1. CSI2 to Parallel Bridge Board Regulator Voltages
Supply Voltage Regulator Resistor Ratio Comment
V1P8_V3P3 On HDR-60 Base BoardR45/R50 1.8VR58/R50 2.5VR59/R50 3.3V
Jumper J253 short:1.8V: 1 and 22.5V: 3 and 4 (default configuration)3.3V: 5 and 6
Each of the LT3025 regulators are the linear low dropout voltage type that incorporate an external resistor divider voltage feedback to divide down the regulator output voltage and compare it against an internal reference voltage. The regulator then adjusts the output voltage higher or lower such that the resistor divided voltage matches the internal reference. By doing this, each regulator output voltage remains at a constant voltage value independent of the load it drives. Each regulator output voltage follows this equation:
VOUT = (1 + resistor ratio) x (regulator internal reference voltage)
See the LT3025 device data sheet for additional details about this device.
The default configuration for J253 is for 2.5V via shorting pins 3 and 4 as shown in Figure 2.
5
CSI2 to Parallel Bridge Board User’s Guide
Figure 2. CSI2 to Parallel Bridge Board with Sony IMX169 CSI2 Sensor
J253: • Short Pins 3 to 4
MEMS Oscillator (Y2)As shown in Figure 2, J5 is set such that the IMX169 sensor will receive a clock input signal from the internal 27.000 MHz MEMS oscillator (Y2). The alternate position of J5 will select the HDR-60 Base Board oscillator for the sensor clock input.
High-Speed CSI2 Connector (J8)The Sony IMX169 (U12) will produce high-speed CSI2 differential signals after proper configuration via SCLK and SADDR pins. There is a CSI2 differential clock and up to four CSI2 differential data lanes. The J8 connector can plug into the MachXO2 Dual Sensor Interface Board or into the HDR-60 Base Board. The signals are identified in Table 2.
Table 2. CSI2 to Parallel Bridge Board (J8)
J8 Pin IMX169 I/O Pin Signal Polarity Description
13 K4 CSI2 data0 P Differential CSI2 data
11 J4 CSI2 data0 N Differential CSI2 data
29 K6 CSI2 data1 P Differential CSI2 data
27 J6 CSI2 data1 N Differential CSI2 data
21 K3 CSI2 data2 P Differential CSI2 data
19 J3 CSI2 data2 N Differential CSI2 data
26 K7 CSI2 data3 P Differential CSI2 data
24 J7 CSI2 data3 N Differential CSI2 data
18 K5 CSI2 clock P Differential CSI2 clock
16 J5 CSI2 clock N Differential CSI2 clock
12 J4 CSI2 low speed data bit 0 — Single-ended CSI2 data 0 N side
6
CSI2 to Parallel Bridge Board User’s Guide
Parallel Connector (J7)Connector J7 is primarily reserved for future use. When used with the MachXO2 Dual Sensor Interface Board, only a few pins are used as shown in Table 3.
Table 3. CSI2 to Parallel Bridge Board (J7)
J7 Pins IMX169 I/O Pin Signal Polarity Description30 K4 CSI2 low speed data bit 0 — Single-ended CSI2 data 0 P side
28 C5 I2C SCLK — Serial clock to program IMX169
26 B5 I2C SADDR — Serial address to program IMX169
9-25, 27, 29, 31 — Reserved for future use via iCE40
References• RD1146, MIPI CSI2 to CMOS Parallel Sensor Bridge
• HDR-60 Video Camera Development Kit web page
• DS1021, LatticeECP3 Family Data Sheet
• HB1009, LatticeECP3 Family Handbook
• EB59, HDR-60 Base Board User’s Guide
• EB69, MachXO2 Dual Sensor Interface Board User’s Guide
• QS010, LatticeECP3 Video Camera Development Kit QuickSTART Guide
Ordering InformationThe CSI2 to Parallel Bridge Board is designed solely for use with the MachXO2 Dual Sensor Interface Board and/or the HDR-60 Video Camera Development Kit.
Description Ordering Part Number China RoHS Environment Friendly
CSI2 to Parallel Bridge Board LF-C2P-EVN
MachXO2 Dual Sensor Interface Board LCMXO2-4000HE-DSIB-EVN
HDR-60 Video Camera Development Kit(Contains: HDR-60 Base Board with LatticeECP3 FPGA pre-loaded with Image Signal Processing (ISP)Demo, two USB cables, HDMI cable with HDMI-to-DVI adapter, 12V AC adapter power supply, QuickSTART Guide)
LFE3-70EAHDR60-DKN
Technical Support AssistanceHotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)e-mail: [email protected]: www.latticesemi.com
7
CSI2 to Parallel Bridge Board User’s Guide
Revision HistoryDate Version Change Summary
December 2012 01.0 Initial release.
February 2013 01.1 Clarify that CSI-2 is for use with MachXO2.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
CSI2 to Parallel Bridge Board User’s Guide
Appendix A. SchematicIndex
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MIP
I IM
X N
AN
OV
ESTA
REV
2
1.
IND
EX
2.
BLO
CK
DIA
GR
AM
3.
BO
TTO
M C
ON
N C
ON
NEC
TIO
N
4.
I2C
BY
PA
SS
CO
NN
ECTI
ON
5.
BA
NK
2 &
BA
NK
3
6.
BA
NK
0 &
BA
NK
1
7.
REG
ULA
TOR
CO
NN
ECTI
ON
8.
LEV
EL T
RA
NS
LATO
R C
ON
NEC
TIO
N
9.
PO
WER
AN
D D
ECA
PS
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
19
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
19
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
19
Thur
sday
, Oct
ober
25,
201
2
9
CSI2 to Parallel Bridge Board User’s Guide
Block Diagram
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
iCE4
0
BA
NK
0
BA
NK
1
BA
NK
2
BA
NK
3
(She
et 6
)
(She
et 6
)
(She
et 5
)
(She
et 5
)
BLO
CK
DIA
GR
AM
BO
TTO
M P
AR
ALL
EL C
ON
NEC
TOR
(She
et 3
)
BO
TTO
M H
IGH
SP
I C
ON
NEC
TOR
(She
et 3
)
SONY SENSOR
MIPI
(Sheet 4)
REG
ULA
TOR
S(S
heet
7)
OSCILLATOR(Sheet 8)
TI CONNECTOR(Sheet 4)
LVD
S(0
,1,2
,3,C
LK)
(She
et 4
)S
PI
FLA
SH
(M
25
P8
0)
(She
et 4
)
2 3
4
1
123
CM
81
LEV
EL T
RA
NS
LATO
R(S
heet
8)
DN
I
SA
DD
R/
SC
LK
SA
DD
R/
SC
LK
DP
HY
(0)
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
29
Sun
day,
Oct
ober
28,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
29
Sun
day,
Oct
ober
28,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
29
Sun
day,
Oct
ober
28,
201
2
NOTNOT40
40 11
USEDUSEDiCE
iCE
CM
CM
10
CSI2 to Parallel Bridge Board User’s Guide
Bottom Conn Connections
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Fitting & Boss have no electrical function, can be used as vias
BO
TTO
M -
HIG
H S
PI
to E
CP
3B
OTT
OM
CO
NN
CO
NN
ECTI
ON
S
BO
TTO
M -
PA
RA
LLEL
to
ECP
3
Fitting & Boss have no electrical function, can be used as vias
SLV
S_0
N_C
SI_
0N_H
ISP
IS
LVS
_0P
_CS
I_0P
_HIS
PI
SLV
S_2
N_C
SI_
2N_H
ISP
IS
LVS
_2P
_CS
I_2P
_HIS
PI
SLV
S_1
N_C
SI_
1N_H
ISP
IS
LVS
_1P
_CS
I_1P
_HIS
PI
SLV
S_C
LKN
_CS
I_C
KN
_HIS
PI
SLV
S_C
LKP
_CS
I_C
KP
_HIS
PI
SLV
S_3
N_C
SI_
3N_H
ISP
IS
LVS
_3P
_CS
I_3P
_HIS
PI
LED
_CM
OS
_CS
I0N
_HIS
PI
SLV
S_0
N_C
SI_
0N_H
ISP
I
LED
_CM
OS
_CS
I0N
_HIS
PI
SLV
S_0
P_C
SI_
0P_H
ISP
I
ICE
40_S
S_C
SI_
0_C
MO
S_L
T
SLV
S_0
N_H
ISP
I
SLV
S_0
P_H
ISP
I
EC
P3_
PR
L_S
CLK
PIX
CLK
FRA
ME
_VA
LID
LIN
E_V
ALI
DD
06D
02D
07D
03D
10D
11
D04
D00
D05
D01
D08
D09
EX
TCLK
ICE
40_S
O_C
SI_
0_C
MO
S_L
T
ICE
40_S
I_C
SI_
0_C
MO
S_L
T
XC
LR_B
OTT
OM
ICE
40_S
CK
_CS
I_0_
CM
OS
_LT
ICE
40_S
S_C
SI_
0_C
MO
S_L
T
EC
P3_
PR
L_S
AD
DR
GN
DG
ND
GN
DG
ND
V1P
8
V5P
0_O
R
V5P
0_TI
V5P
0
V5P
0_O
RV
5P0_
OR
V5P
0_O
RV
5P0_
OR
SLV
S_2
N_C
SI_
2N_H
ISP
I[5
]S
LVS
_2P
_CS
I_2P
_HIS
PI
[5]
SLV
S_1
N_C
SI_
1N_H
ISP
I[5
]S
LVS
_1P
_CS
I_1P
_HIS
PI
[5]
SLV
S_C
LKN
_CS
I_C
KN
_HIS
PI[5
]S
LVS
_CLK
P_C
SI_
CK
P_H
ISP
I[5
]
SLV
S_3
N_C
SI_
3N_H
ISP
I[5
]S
LVS
_3P
_CS
I_3P
_HIS
PI
[5]
SLV
S_0
N_H
ISP
I[5
] SLV
S_0
P_H
ISP
I[5
]
PIX
CLK
[4,6
]FR
AM
E_V
ALI
D[4
,6]
D04
[4,6
]D
00[4
,6]
D05
[4,6
]D
01[4
,6]
D08
[4,6
]D
09[4
,6]
LIN
E_V
ALI
D[4
,6]
D06
[4,6
]D
02[4
,6]
D07
[4,6
]D
03[4
,6]
D10
[4,6
]D
11[4
,6]
EX
TCLK
[8]
ICE
40_S
O_C
SI_
0_C
MO
S_L
T[4
]
ICE
40_S
I_C
SI_
0_C
MO
S_L
T[4
]
XC
LR_B
OTT
OM
[5]
ICE
40_S
CK
_CS
I_0_
CM
OS
_LT
[4]
ICE
40_S
S_C
SI_
0_C
MO
S_L
T[4
]
EC
P3_
PR
L_S
AD
DR
[4,8
]E
CP
3_P
RL_
SC
LK[4
,8]
Title
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N tnemuco
Dezi
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I_IM
X_N
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ES
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_RE
V_2
B
39
Sun
day,
Oct
ober
28,
201
2
Title
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rebmu
N tnemuco
Dezi
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2>co
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X_N
AN
OV
ES
TRA
_RE
V_2
B
39
Sun
day,
Oct
ober
28,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
39
Sun
day,
Oct
ober
28,
201
2
R10
10
TP5
Hirose DF12 Series
J8 DF1
2(4.
0)-4
0DP
-0.5
V_H
EA
DE
R
PA
RT_
NU
MB
ER
= D
F12(
4.0)
-40D
P-0
.5V
Man
ufac
ture
r = H
IRO
SE
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
FITT
ING
1FI
TTIN
G1
FITT
ING
2FI
TTIN
G2
BO
SS
1B
OS
S1
BO
SS
2B
OS
S2
J251
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
J274
SM
D_1
210_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
J252
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
TP1
R11
10.0
K1%
Hirose DF12 Series
J7 DF1
2_40
DS
-0.5
V_R
EC
EP
TAC
LE
PA
RT_
NU
MB
ER
= D
F12(
4.0)
-40D
S-0
.5V
Man
ufac
ture
r = H
IRO
SE
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
FITT
ING
1FI
TTIN
G1
FITT
ING
2FI
TTIN
G2
BO
SS
1B
OS
S1
BO
SS
2B
OS
S2
11
CSI2 to Parallel Bridge Board User’s Guide
12C Bypass Connection
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
I2C
BY
PA
SS
CO
NN
ECTI
ON
DEF
AU
LT 1
&2
DEF
AU
LT 1
&2
LIN
E_V
ALI
DFR
AM
E_V
ALI
D
PIX
CLK
D05
D04
D03
D02
D00
D01
D06
D07
D08
D09
D10
D11
RE
SE
T_B
AR
EC
P3_
PR
L_S
CLK
EC
P3_
PR
L_S
AD
DR
ICE
40_S
I_C
SI_
0_C
MO
S
ICE
40_S
CK
_CS
I_0_
CM
OS
ICE
40_S
O_C
SI_
0_C
MO
S
ICE
40_S
S_C
SI_
0_C
MO
S
ICE
40_S
O_C
SI_
0_C
MO
S
ICE
40_S
I_C
SI_
0_C
MO
S
ICE
40_S
CK
_CS
I_0_
CM
OS
ICE
40_S
S_C
SI_
0_C
MO
S
ICE
40_S
CK
_CS
I_0_
CM
OS
ICE
40_S
O_C
SI_
0_C
MO
S
ICE
40_S
S_C
SI_
0_C
MO
S
ICE
40_S
I_C
SI_
0_C
MO
S
GN
D
V3P
3V
3P3
V3P
3
GN
D
V3P
3
GN
D
V3P
3
GN
D
V1P
8_3_
3V
GN
D
V1P
8_3_
3V
GN
D
V3P
3V
1P8_
3_3V
GN
D
V5P
0
V3P
3
GN
D
V3P
3
V5P
0_TI
FRA
ME
_VA
LID
[3,6
]LI
NE
_VA
LID
[3,6
]
PIX
CLK
[3,6
]
D11
[3,6
]D
10[3
,6]
D09
[3,6
]D
08[3
,6]
D07
[3,6
]D
06[3
,6]
D05
[3,6
]D
04[3
,6]
D03
[3,6
]D
02[3
,6]
D01
[3,6
]D
00[3
,6]
RE
SE
T_B
AR
[6]
EC
P3_
PR
L_S
CLK
[3,8
]E
CP
3_P
RL_
SA
DD
R[3
,8]
ICE
40_S
O_C
SI_
0_C
MO
S_L
T[3
,4]
ICE
40_S
I_C
SI_
0_C
MO
S_L
T[3
,4]
ICE
40_S
CK
_CS
I_0_
CM
OS
_LT
[3,4
]
ICE
40_S
S_C
SI_
0_C
MO
S_L
T[3
,4]
ICE
40_S
S_C
SI_
0_C
MO
S_L
T[3
,4] IC
E40
_SC
K_C
SI_
0_C
MO
S_L
T[3
,4]
ICE
40_S
O_C
SI_
0_C
MO
S_L
T[3
,4]
ICE
40_S
I_C
SI_
0_C
MO
S_L
T[3
,4]
SA
DD
R_B
OTT
OM
[8]
SC
LK_B
OTT
OM
[8]
SA
DD
R[5
,6]
SC
LK[5
,6]
SF8
K_S
AD
DR
1[6
]S
F8K
_SC
LK[6
]
Title
v eR
rebmu
N tnemuco
Dez i
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
49
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
49
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
49
Thur
sday
, Oct
ober
25,
201
2
U14
M25
P80
-VM
W6T
GM
anuf
actu
rer =
MIC
RO
NP
AR
T_N
UM
BE
R =
M25
P80
-VM
W6T
G
S_L
1
Q2
W_L
3
VS
S4
D5
C6
HO
LD_L
7V
CC
8
J9 0541
0436
31
PA
RT_
NU
MB
ER
= 0
5410
4363
1M
anuf
actu
rer =
MO
LEX
VC
C3.
3_1
1
VC
C3.
3_2
2
VC
C3.
3_3
3
VC
C5.
5_1
4
VC
C5.
5_2
5
GN
D1
6
EX
T_C
LK7
GN
D2
8
AFE
_CLK
9
GN
D3
10
AFE
_VD
11
AFE
_HD
12
AFE
_D13
13
AFE
_D12
14
AFE
_D11
15
AFE
_D10
16
AFE
_D9
17
AFE
_D8
18
AFE
_D7
19
AFE
_D6
20
AFE
_D5
21
AFE
_D4
22
AFE
_D3
23
AFE
_D2
24
GN
D4
25
GN
D5
26
AFE
_D1
27
AFE
_D0
28
I2C
_SC
LK29
I2C
_SD
ATA
30
SP
I_S
DO
31
SP
I_S
CLK
32
AFE
_RE
SE
T33
SP
I_E
N34
AFE
_D14
35
AFE
_D15
36
ME
CH
137
ME
CH
238
SEC
6/6
SPI
iCE4
0U
16F
iCE
40_C
M81
Man
ufac
ture
r = L
ATT
ICE
PA
RT_
NU
MB
ER
= iC
E40
PIO
S_S
PI_
SO
G6
PIO
S_S
PI_
SI
H7
PIO
S_S
PI_
SC
KG
7
PIO
S_S
PI_
SS
_BF7
SP
I_V
CC
H8
J277
3PIN
_SM
D_0
603
DE
FAU
LT_O
PTI
ON
= In
stal
l 0/0
603
Res
itor
1
2
3
R24
10.0
K1%
TXB0104DR
U15
LT_T
XB
0104
DR
Man
ufac
ture
r = T
IP
AR
T_N
UM
BE
R =
TX
B01
04D
R
VC
CA
1
A1
2
A2
3
A3
4
A4
5
NC
16
GN
D7
OE
8
NC
29
B4
10B
311
B2
12B
113
VC
CB
14
R12
10.0
K1%
C27
100n
F16
V
R10
20
R31
DN
L
R15
310
K1%
J273
HD
R_2
X3
MIS
O1
NC
_+5V
2S
CLK
3M
OS
I4
SS
5G
ND
6
C28
100n
F16
V
C92
80.
1uF
16V
J276
3PIN
_SM
D_0
603
DE
FAU
LT_O
PTI
ON
= In
stal
l 0/0
603
Res
itor
1
2
3
C92
70.
1uF
16V
NOT66 OS
_SP
I_S
OS
_SP
I_S
OS
_SP
I_S
OS
_SP
I_
S_S
PI_
SC
S_S
PI_
SC
SP
IS
SS
SP
I_V
CS
PI
VC
USEDSEC
SEC SEDSP
ISP
I
iCiC
Bank2 and Bank3
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
BA
NK
2 A
ND
BA
NK
3
PLACE
resi
stor
s R10
3, R
114,
R11
5, R
116,
CLO
SE
TO T
HE
SO
NY
SEN
SO
R P
INS
NO
TE:
PLACE
clos
e to
the
dev
ice
U16
SLV
S_0
P_C
SI_
0PS
LVS
_0P
_LV
DS
SLV
S_0
P_D
PH
Y
SLV
S_0
N_C
SI_
0NS
LVS
_0N
_LV
DS
SLV
S_0
N_D
PH
Y
SA
DD
R
SC
LKS
LVS
_0N
_CS
I_0N
SLV
S_0
P_C
SI_
0P
SLV
S_2
P_C
SI_
2P
SLV
S_2
N_C
SI_
2N
SLV
S_1
P_C
SI_
1P
SLV
S_1
N_C
SI_
1N
SLV
S_3
P_C
SI_
3P
SLV
S_3
N_C
SI_
3N
SLV
S_C
LKP
_CS
I_C
KP
SLV
S_C
LKN
_CS
I_C
KN
SLV
S_3
N_L
VD
S
SLV
S_3
P_L
VD
S
SLV
S_2
N_C
SI_
2N
SLV
S_2
N_L
VD
S
SLV
S_2
P_C
SI_
2P
SLV
S_2
P_L
VD
S
SLV
S_3
P_C
SI_
3P
SLV
S_3
N_C
SI_
3N
SO
NY
_IN
CK
SLV
S_1
P_L
VD
S
SLV
S_1
P_C
SI_
1PS
LVS
_1N
_CS
I_1N
SLV
S_1
N_L
VD
S
SLV
S_C
LKP
_CS
I_C
KP
SLV
S_C
LKP
_LV
DS
SLV
S_C
LKN
_LV
DS
SLV
S_C
LKN
_CS
I_C
KN
SLV
S_0
P_L
VD
SS
LVS
_1P
_LV
DS
SLV
S_1
N_L
VD
SS
LVS
_0N
_LV
DS
SLV
S_0
P_L
VD
S_1
SLV
S_0
N_L
VD
S_1
SLV
S_1
P_L
VD
S_1
SLV
S_1
N_L
VD
S_1S
LVS
_0N
_LV
DS
_1S
LVS
_0P
_LV
DS
_1
SLV
S_1
P_L
VD
S_1
SLV
S_1
N_L
VD
S_1
SLV
S_2
N_L
VD
S_1
SLV
S_2
P_L
VD
S_1
SLV
S_3
N_L
VD
S_1
SLV
S_3
P_L
VD
S_1
SLV
S_C
LKN
_LV
DS
_1S
LVS
_CLK
P_L
VD
S_1
V1P
8
AG
ND
AG
ND
V1P
8
V2P
5
GN
D
GN
D
V2P
5
V2P
5V
1P8
V1P
8V
1P8
V1P
8G
ND
V1P
8G
ND
GN
D
SLV
S_0
P_H
ISP
I[3
]S
LVS
_0N
_HIS
PI
[3]
SO
NY
_IN
CK
[6,8
]
XC
LR_S
ON
Y[5
]
SLV
S_2
P_C
SI_
2P_H
ISP
I[3
]S
LVS
_2N
_CS
I_2N
_HIS
PI
[3]
SLV
S_3
P_C
SI_
3P_H
ISP
I[3
]
SLV
S_3
N_C
SI_
3N_H
ISP
I[3
]
SLV
S_0
N_D
PH
Y[6
]S
LVS
_0P
_DP
HY
[6]
SLV
S_1
P_C
SI_
1P_H
ISP
I[3
]S
LVS
_1N
_CS
I_1N
_HIS
PI
[3]
SLV
S_C
LKP
_CS
I_C
KP
_HIS
PI
[3]
SLV
S_C
LKN
_CS
I_C
KN
_HIS
PI
[3]
XC
LR_i
CE
[6]
XC
LR_B
OTT
OM
[3]
XC
LR_S
ON
Y[5
]
SLV
S_C
LKP
_LV
DS
[6]
SLV
S_C
LKN
_LV
DS
[6]
SLV
S_3
P_L
VD
S[6
]
SLV
S_3
N_L
VD
S[6
]
SLV
S_2
P_L
VD
S[6
]S
LVS
_2N
_LV
DS
[6]
SC
LK[4
,6]
SA
DD
R[4
,6]
SLV
S_2
N_L
VD
S_1
[6]
SLV
S_2
P_L
VD
S_1
[6]
SLV
S_3
N_L
VD
S_1
[6]
SLV
S_3
P_L
VD
S_1
[6]
SLV
S_C
LKN
_LV
DS
_1[6
]S
LVS
_CLK
P_L
VD
S_1
[6]
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
59
Mon
day,
Oct
ober
29,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
59
Mon
day,
Oct
ober
29,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
59
Mon
day,
Oct
ober
29,
201
2
C89
80.
22U
F6.
3V
R11
11K 1%
C89
90.
22U
F6.
3V
1 2 3
DP
R35
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
1 2 3
DP
R33
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
R11
01K 1%
J272
21
R42
2
120
J278
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
SEC
4/6
BANK 3
iCE4
0U
16D
iCE
40_C
M81
Man
ufac
ture
r = L
ATT
ICE
PA
RT_
NU
MB
ER
= iC
E40PIO
3_D
P00
AC
2
PIO
3_D
P00
BB
2
PIO
3_D
P01
BC
1P
IO3_
DP
01A
B1
PIO
3_D
P02
BC
3P
IO3_
DP
02A
D2
PIO
3_D
P03
AD
1
PIO
3_D
P06
BE
4
PIO
3_D
P03
BE
1
PIO
3_D
P05
AE
2P
IO3_
DP
04B
F3P
IO3_
DP
04A
F1
PIO
3_D
P08
BG
1P
IO3_
DP
08A
G3
GB
IN6_
PIO
3_D
P06
AE
3G
BIN
7_P
IO3_
DP
05B
D3
VC
CIO
_3_H
3H
3
PIO
3_D
P07
BH
2P
IO3_
DP
07A
G2
R42
1
120
J275
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
R42
04
70
1%R
104
0
R42
930
0
R42
822
0
R43
0
120
1 2 3
DP
R32
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
R43
122
0
LED15PART_NUMBER = SML-512MWT86Green
1 2
R43
222
0
R44
8D
NL
R419 2401%
R44
9D
NL
CON
FIG
SEC
3/6
BANK 2
iCE4
0U
16C
iCE
40_C
M81
Man
ufac
ture
r = L
ATT
ICE
PA
RT_
NU
MB
ER
= iC
E40
VC
CIO
_2_J
5J5
GB
IN4_
PIO
2H
4
PIO
2_3
H1
PIO
2_4
J2
PIO
2_5
J1
PIO
2_6
J3
PIO
2_7
J4
GB
IN5_
PIO
2G
4
PIO
2_C
BS
EL0
G5
PIO
2_C
BS
EL1
H5
CD
ON
EE
6
CR
ES
ET_
BH
6
J279
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
1 2 3
4
DP
R26
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2
31
4
1 2 3
4
DP
R25
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2
31
4
R11
510 1%
R10
310 1%
R42
722
0
1 2 3
DP
R31
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
1 2 3
DP
R38
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
1 2 3
DP
R37
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
R15
10.0
K1%
R11
410 1%
LED
14P
AR
T_N
UM
BE
R =
SM
L-51
2MW
T86
Gre
en
12
R42
6
120
TP3
SEC
2/3
SONY SENSOR
U12
B
IMX
169C
QK
CM
anuf
actu
rer =
SO
NY
PA
RT_
NU
MB
ER
= IM
X16
9CQ
K-C
DM
O3N
J7D
MO
3PK
7
DM
O1N
J6D
MO
1PK
6
DC
KN
J5D
CK
PK
5
DM
O2N
J3D
MO
2PK
3
DM
O0N
J4D
MO
0PK
4
VC
AP
1H
1
VC
AP
2E
1
INC
KA
7
SC
LC
5
SD
AB
5
XC
EB
6
XC
LRC
6
SD
OA
5
XV
SA
6
TES
T1A
8
TES
T2B
8
TES
T3E
2
TES
T4J2
TES
T5K
2
1 2 3
DP
R36
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
R11
610 1%
R43
330
0
TP2
1 2 3
DP
R34
0 DE
FAU
LT_O
PTI
ON
= 2
&3
2 31
NOTPIO
3_D
P0
PIO
3_D
P0
PIO
3_D
P0
PIO
3_D
P0
PIO
3_D
P0
IO3_
DP
PIO
3_D
P0
O3_
DP
PIO
3D
P0
P0
PIO
3_D
P0
PIO
3_D
P0
PIO
3_D
P0
O3_
DP
0P
IO3_
DP
0P
IO3_
DP
0P
IO3_
DP
0P
IO3_
DP
0
PIO
3_D
P0
PIO
3_D
P0
PIO
3_D
P0
PIO
3_D
P0
USEDGB
GB
GB
GB
NOTGB
IN4_
PG
BIN
4_P
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
GB
IN5_
PG
BIN
5_P
PIO
2_C
BS
IO2_
CB
SP
IO2_
CB
SIO
2_C
BS
USEDO_2
_J5
O_2
_J5
Bank0 and Bank1
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
BA
NK
0 A
ND
BA
NK
1
DEC
AP
S F
OR
BA
NK
0D
ECA
PS
FO
R B
AN
K1
DEC
AP
S F
OR
BA
NK
2D
ECA
PS
FO
R B
AN
K3
NO
TE:
PLACE
clos
e to
the
dev
ice
U16
SF8
K_S
CLK
D00
D05
D01
D08
D09
PIX
CLK
D04
FRA
ME
_VA
LID
LIN
E_V
ALI
DD
06
D07
D03
D10
D11
D02
RE
SE
T_B
AR
XC
LR_i
CE
SLV
S_0
P_D
PH
YS
LVS
_0N
_DP
HY
SLV
S_3
P_L
VD
S
SLV
S_3
N_L
VD
S
SLV
S_C
LKP
_LV
DS
SLV
S_C
LKN
_LV
DS
SLV
S_3
P_L
VD
S_1
SLV
S_3
N_L
VD
S_1
SLV
S_C
LKP
_LV
DS
_1
SLV
S_C
LKN
_LV
DS
_1
SLV
S_2
P_L
VD
S
SLV
S_2
N_L
VD
SS
LVS
_2N
_LV
DS
_1
SLV
S_2
P_L
VD
S_1
SO
NY
_IN
CK
SF8
K_S
AD
DR
1
V1P
8_3_
3VV
1P8
V2P
5V
1P8
V1P
8
GN
DG
ND
GN
DG
ND
V1P
8_3_
3V
V1P
8V
1P8
V1P
8V
1P8
GN
DG
ND
V1P
8 V1P
8G
ND
D00
[3,4
]D
05[3
,4]
D08
[3,4
]D
09[3
,4]
D01
[3,4
]
PIX
CLK
[3,4
]FR
AM
E_V
ALI
D[3
,4]
D04
[3,4
]
LIN
E_V
ALI
D[3
,4]
D06
[3,4
]D
02[3
,4]
D07
[3,4
]D
03[3
,4]
D10
[3,4
]D
11[3
,4]
RE
SE
T_B
AR
[4]
XC
LR_i
CE
[5]
SLV
S_0
N_D
PH
Y[5
]S
LVS
_0P
_DP
HY
[5]
SLV
S_3
P_L
VD
S[5
]
SLV
S_3
N_L
VD
S[5
]
SLV
S_C
LKP
_LV
DS
[5]
SLV
S_C
LKN
_LV
DS
[5]
SLV
S_3
P_L
VD
S_1
[5]
SLV
S_3
N_L
VD
S_1
[5]
SLV
S_C
LKP
_LV
DS
_1[5
]
SLV
S_C
LKN
_LV
DS
_1[5
]
SLV
S_2
P_L
VD
S[5
]
SLV
S_2
N_L
VD
S[5
]
SLV
S_2
P_L
VD
S_1
[5]
SLV
S_2
N_L
VD
S_1
[5]
SA
DD
R[4
,5]
SC
LK[4
,5]
SF8
K_S
CLK
[4]
SO
NY
_IN
CK
[5,8
]
SF8
K_S
AD
DR
1[4
]
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
69
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
69
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
69
Thur
sday
, Oct
ober
25,
201
2
R76
330.
5%
C91
0.1u
F16
V
R87
330.
5%
R44
422
0
R43
4
120
R43
8
120
C95
0.1u
F16
V
R75
330.
5%
R81
330.
5%
C57
0.1u
F16
V
R84
330.
5%
R44
530
0
C97
0.1u
F16
V
R43
522
0
R45
0D
NL
C59
0.1u
F16
V
R72
330.
5%
R44
022
0
R44
6D
NI
R43
622
0
C60
0.1u
F16
V
J282
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
R42
4
120
R45
1D
NL
R77
330.
5%
C93
0.1u
F16
V
R86
330.
5%
R83
330.
5%
R44
122
0
SEC
2/6
BANK 1
iCE4
0U
16B
iCE
40_C
M81
Man
ufac
ture
r = L
ATT
ICE
PA
RT_
NU
MB
ER
= iC
E40
GB
IN2_
PIO
1_1
D8
GB
IN3_
PIO
1_2
E8
PIO
1_3
F8
PIO
1_4
G8
PIO
1_5
D6
PIO
1_6
E7
PIO
1_7
D7
PIO
1_8
D9
PIO
1_9
B9
PIO
1_10
C9
PIO
1_11
A9
PIO
1_12
H9
PIO
1_13
J8
PIO
1_14
G9
PIO
1_15
J9
VC
CIO
_1_C
6C
6
J281
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
R42
5
120
R71
330.
5%
R74
330.
5%
R43
730
0
C58
0.1u
F16
V
R88
330.
5%
R44
7D
NI
SEC
1/
6
BANK 0
iCE4
0U
16A
iCE
40_C
M81
Man
ufac
ture
r = L
ATT
ICE
PA
RT_
NU
MB
ER
= iC
E40
PIO
0_4
B7
PIO
0_5
A8
PIO
0_6
B6
PIO
0_7
A7
PIO
0_8
A6
PIO
0_9
B5
PIO
0_10
A4
PIO
0_11
E5
PIO
0_12
A3
PIO
0_13
B4
PIO
0_14
A2
PIO
0_15
D5
PIO
0_16
B3
PIO
0_17
A1
VC
CIO
_0_A
5A
5G
BIN
0_P
IO0_
1C
4
GB
IN1_
PIO
0_2
C5
PIO
0_3
B8
J280
SM
D_0
402_
JPR
DE
FAU
LT_O
PTI
ON
= 1
&2
1
2
3
R44
230
0R
439
120
R82
330.
5%
R73
330.
5%
R85
330.
5%
R44
322
0R
423
120
R45
2D
NL
NOT
GB
IN3_
PIO
BIN
3_P
IOP
IOP P
IOP
IOP
IOP
IOP
IOP
IOP
IOP
IOP
IOP
IOP
IOP
IO1
PIO
PIO
1P
IOP
IO1
O
USEDSEC
SEC
BBAANNKK11IO_1
_C6
IO_
NOTPIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
0P
IOP
IO0
O0
PIO
0P
IO0
PIO
0O
0
PIO
PIO
USEDBANK0O_0
_A5
O_0
_A5
Regulator Connections
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
V1P2
1.2v
300m
A
1ms
RC
V1P8
1.8v
300m
A
V2P7
2.7v
300m
A
V2P5
2.5v
300m
A
REG
ULA
TOR
CO
NN
ECTI
ON
S
V1P2
_VD
D1.
2v30
0mA
1ms
RC
V1P8
_3_3
V1.
8V o
r 2.5
V or
3.3
V 30
0mA
V3P3
3.3v
300m
A
1 &
2
3
4.8
K
V
1P
83
& 4
52
.3K
V2
P5
5 &
6
7
3.2
K
3
_3
V
SH
UN
TV
ALU
EV
OLT
AG
E
GN
D
GN
D
GN
DG
ND
GN
D
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
V5P
0
V2P
7
V5P
0
V1P
8
V5P
0
V1P
2
V1P
2
V5P
0
V5P
0
V2P
5
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
V5P
0
V1P
2_V
DD
GN
D
V1P
8G
ND
GN
D
V1P
8_3_
3V
GN
D
GN
DG
ND
GN
D
V5P
0
GN
DG
ND
V3P
3
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
79
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
79
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
79
Thur
sday
, Oct
ober
25,
201
2
R42
DN
I-060
3SM
T
C81
0.1u
F16
V
R40
DN
I-060
3SM
T
C84
0.1u
F16
V
J253
2x3_
HE
AD
ER
_100
mil
12
34
56
C21
10uF
/6V
36.
3V
R41
DN
I-060
3SM
T
LTC3
025
U11
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
C6
10uF
/6V
36.
3VR52
1R 5%
R10
70
R43
57.6
KR
0402
1%R
57
100K
-040
2SM
T
5%
C11
10uF
/6V
36.
3V
R53
10.0
KR
0402
1%
C19
10uF
/6V
36.
3V
R19
DN
I-060
3SM
T
R17
DN
I-060
3SM
T
R32
1R 5%
LTC3
025
U10
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
LTC3
025
U4
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
C16
10uF
/6V
36.
3V
R11
70
C7
10uF
/6V
36.
3V
R20
10.0
KR
0402
1%
C33
0.01
uF25
V
C79
0.1u
F16
V
R59
73.2
KR
0402
1%
C13
10uF
/6V
36.
3V
R10
90
R49
1R 5%
C78
0.1u
F16
V
R44
34.8
KR
0402
1%
R45
34.8
KR
0402
1%
R13
10.0
K1%
C5
10uF
/6V
36.
3V
R33
1R 5%
LTC3
025
U9
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
LTC3
025
U8
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
R16
20K
R04
021%
C77
0.1u
F16
V
C32
0.01
uF25
V
R14
DN
I-060
3SM
T
R10
60
C4
10uF
/6V
36.
3V
R22
10.0
KR
0402
1%
R21
10.0
KR
0402
1%
R54
52.3
KR
0402
1%
C9
10uF
/6V
36.
3V
C12
10uF
/6V
36.
3V
R34
1R 5%
LTC3
025
U5
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
R58
52.3
KR
0402
1%
C20
10uF
/6V
36.
3V
R55
DN
I-060
3SM
T
R48
1R 5%
R46
10.0
KR
0402
1%
R18
20K
R04
021%
R56
1R 5%
C22
10uF
/6V
36.
3V
R23
73.2
KR
0402
1%
LTC3
025
U6
LTC
3025
ED
C#P
BF
BIAS1
EN
6
IN3
GND2
PWP7
AD
J5
OU
T4
C23
10uF
/6V
36.
3V
C76
0.1u
F16
V
R10
80
C80
0.1u
F16
V
R47
100K
-040
2SM
T
5%
R50
10.0
KR
0402
1%
Level Translator Connections
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
LEV
EL T
RA
NS
LATO
R C
ON
NEC
TIO
NS
OS
CIL
LATO
R
Pla
ce R
28 n
ear Y
2
DEF
AU
LT 1
&2
EX
TCLK
_OS
C
EX
TCLK
SO
NY
_IN
CK
V1P
8
GN
D
V1P
8_3_
3V
GN
DV
1P8_
3_3V
V1P
8
V1P
8
GN
D
GN
DG
ND
GN
D
V1P
8V
1P8_
3_3V
EX
TCLK
[3]
SO
NY
_IN
CK
[5,6
]
EC
P3_
PR
L_S
AD
DR
[3,4
]
EC
P3_
PR
L_S
CLK
[3,4
]
SA
DD
R_B
OTT
OM
[4]
SC
LK_B
OTT
OM
[4]
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
89
Sun
day,
Oct
ober
28,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
89
Sun
day,
Oct
ober
28,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
89
Sun
day,
Oct
ober
28,
201
2
R15
04_
7K1%
R11
21K 1%
C26
100n
F16
V
R11
31K 1%
R28
27 1%C
101u
F6.
3V
J5
SM
D_0
603_
JPR
1 2 3
TXS0
102D
C
U13
TXS
0102
DC
Man
ufac
ture
r = T
IP
AR
T_N
UM
BE
R =
TX
S01
02D
CU
R
VC
CA
3
A1
5
A2
4
GN
D2
OE
6
B2
1B
18
VC
CB
7
R15
210
K1%
C22
50.
1uF
16V
1 2C
2510
0nF
16V
FB1
BLM
21A
G60
1SN
1DY
2
27 M
HZ
DI
Par
t Num
ber =
DS
C10
01A
E2-
27.0
000
Man
ufac
ture
r = D
ISC
ER
A
VC
C4
OU
T3
GN
D2
EN
1
Sensor Power and Decaps
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DEC
AP
S F
OR
VIP
2D
ECA
PS
FO
R V
2P
7
SEN
SO
R P
OW
ER A
ND
DEC
AP
S
DEC
AP
S F
OR
VIP
8
DEC
AP
S F
OR
V1
P2
_V
DD
DEC
AP
S F
OR
V2
P5
V1P
8_V
DD
M
V2P
7_V
DD
H
V1P
2_V
DD
L
V2P
7_V
DD
H
V1P
8_V
DD
M
V1P
2_V
DD
L
PLL
VC
C_G
2
PLL
GN
D_H
2
PLL
VC
C_G
2
PLL
GN
D_H
2
AG
ND
GN
D
AG
ND
V1P
2_V
DD
GN
D
GN
D
V2P
5
GN
D
V2P
7
V1P
8
V1P
2
AG
ND
GN
D
AG
ND
GN
D
V1P
2_V
DD
GN
DA
GN
D
V2P
5
V1P
2_V
DD
GN
D
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
99
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
99
Thur
sday
, Oct
ober
25,
201
2
Title
veR
rebmu
N tnemuco
Dezi
S
teehS
:etaD
of
2>co
D<MIP
I_IM
X_N
AN
OV
ES
TRA
_RE
V_2
B
99
Thur
sday
, Oct
ober
25,
201
2
C70
0.1u
F16
V
L41
4.7U
HP
AR
T_N
UM
BE
R =
744
3732
4047
12
C90
40.
1uF
16V
L43
4.7U
H1
2
C90
20.
1uF
16V
C12
61u
F16
V
C71
0.1u
F16
V
C91
510
UF
10V
C12
51u
F16
V
C89
72.
2UF
16V
C90
30.
1uF
16V
C91
90.
1uF
16V
TP4
C12
71u
F16
VC
923
10U
F10
V
R11
910
01%
C91
610
UF
10V
SEC
5/6
iCE4
0U
16E
iCE
40_C
M81
Man
ufac
ture
r = L
ATT
ICE
PA
RT_
NU
MB
ER
= iC
E40
VC
C_1
D4
VC
C_2
F2
VC
C_3
E9
VP
P_2
V5
C8
VP
P_F
AS
TC
7
GN
D_1
F5
GN
D_2
F4
GN
D_3
F9
GN
D_4
F6
PLL
GN
DJ6
PLL
VC
CJ7
C90
61u
F16
V
C12
41u
F16
V
C75
0.1u
F16
V
C92
410
UF
10V
C54
0.1u
F16
V
L42
4.7U
HP
AR
T_N
UM
BE
R =
744
3732
4047
12
C89
0.1u
F16
V
C90
71u
F16
V
C53
0.1u
F16
V
C92
610
UF
10V
C12
31u
F16
V
C91
30.
1uF
16V
R12
00
C91
710
UF
10V
C90
81u
F16
V
C73
0.1u
F16
V
C13
61u
F16
V
C90
90.
1uF
16V
C91
81u
F16
V
C90
00.
1uF
16V
C91
10.
1uF
16V
C87
0.1u
F16
V
SEC
1/3
SONY SENSOR
U12
A
IMX
169C
QK
CM
anuf
actu
rer =
SO
NY
PA
RT_
NU
MB
ER
= IM
X16
9CQ
K-C
VD
DH
1A
4
VD
DH
2C
1
VD
DH
3C
9
VD
DH
4D
1
VD
DH
5G
1
VD
DH
6H
3
VD
DH
7H
9
VD
DL1
C7
VD
DL2
E3
VD
DL3
F1
VD
DL4
H5
VD
DL5
H6
VD
DM
C8
VS
SH
1B
4
VS
SH
2C
2
VS
SH
3D
2
VS
SH
4G
2
VS
SH
5G
3
VS
SH
6H
2
VS
SH
7H
8
VS
SL1
B7
VS
SL2
C4
VS
SL3
D7
VS
SL4
F2
VS
SL5
F3
VS
SL6
G7
VS
SL7
H4
VS
SL8
H7
VC
PA
3
VR
LB
3
C91
40.
1uF
16V
R10
50
C90
50.
1uF
16V
C92
11u
F16
V
C92
210
UF
10V
C74
0.1u
F16
V
C13
71u
F16
V
C13
81u
F16
V
C91
00.
1uF
16V
C90
10.
1uF
16V
C91
20.
1uF
16V
C92
00.
1uF
16V
NOTGN
D_
GN
D_
GN
D_
GN
GN
D_
GN
DG
ND
_G
ND
PLL
GN
GN
USEDSESE
CC
_1C
C_1
CC
_2C
C_2
CC
_3C
C_3
PP
_2V
5P
P_2
V5
PP
_FA
ST
PP
_FA
ST
LLV
CC
LVC
C
Mouser Electronics
Authorized Distributor
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LF-C2P-EVN