Download - CS/EE 6710
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CS/EE 6710
CMOS Processing
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N-type Transistor
+
-
i electronsVds
+Vgs S
G
D
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N-type from the top
Top view shows patterns that make up the transistor
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Diffusion Mask
Mask for just the diffused regions
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Polysilicon Mask
Mask for just the polysilicon areas
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Combine the two masks
You get an N-type transistorThere are other steps in the process…
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A Cutaway ViewCMOS structure with both transistor types
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Look at Inverter Layout Again
How many layers?How many processing steps?
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Photolithography Oxidation LayerPhotoresist (PR)
CoatingStepper ExposurePR development and
bakeAcid EtchingSpin, Rinse, DryProcessing stepPR removal (ashing)
UV Light
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Photolithographic Process
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Photolithographic Process
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Photolithographic Process
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Photolithographic Process
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Photolithographic Process
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Photolithographic Process
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Photolithographic Process
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Growing the Silicon Crystal
Need single crystal structure Single crystal vs. Polycrystalline silicon (Poly)
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Czochralski Method
Need single-crystal silicon to accept impurities correctlyDonor elements provide electronsAcceptor elements provide holes
Pull a single crystal of silicon from a puddle of molten polycrystalline silicon
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Slice Crystal into Wafers
Slice into thin wafers (.25mm - 1.0mm), and polish to remove all scratches
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Lapping and Polishing
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Oxidation, Growing SiO2
Essential property of silicon is a nice, easily grown, insulating layer of SiO2Use for insulating gates (“thin oxide”)Also for “field oxide” to isolate devices
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Making the Mask
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Adding Photoresist
Photoresist can be positive or negativeDoes the exposed part turn hard, or the unexposed
part?
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“Steppers” Expose the Mask
Use very short wavelength UV lightSingle frequency, 436 - 248 nm
Expensive! ~$5,000,000/machine…
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Develop and Bake Photoresist
Developed photoresist is soft, unexposed is hardened So you can etch away the soft (exposed) part
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Now Etch the SiO2
Etch the SiO2 to expose the wafer for processing
Then Spin Rinse, and Dry
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Add a Processing StepNow that we’ve got a pattern etched to the
right level, we can process the siliconCould be:
Ion Implantation (I.e. diffusion)Chemical Vapor Deposition (silicide, Poly,
insulating layers, etc.)Metal deposition (evaporation or sputtering)Copper deposition (very tricky)
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Ion Implantation
Implant ions into the siliconDonor or Acceptor
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Chemical Vapor Deposition
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Metal Deposition
Typically aluminum, gold, tungsten, or alloys
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Advanced Metalization
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Copper is Tricky
40% less resistance than Aluminum 15% system speed increase
But, copper diffuses into Silicon and changes the electrical properties
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Ashing - Removing Photoresist
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Final Layer: Passivation
Basically a final insulating layer (SiO2 or Si3N4) to protect the circuit
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CMOS FabricationStart from single-crystal silicon waferUse photolithography to pattern device layers
Essentially one mask/photolithographic sequence per layer
Built (roughly) from the bottom up6 - Metal 35 - Metal 24 - Metal 12 - Polysilicon3 - Diffusions1 Tub (N-well)
Exc
eptio
n
Contact
ViaVia
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Self-Aligned GatesThinox in active
regions, thick elsewhere
Deposit Polysilicon
Etch thinox from active region (Poly serves as mask for etch/diffusion)
Implant dopant
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CMOS Inverter
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N-well Mask
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Active Mask
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Poly Mask
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N+ Select Mask
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P+ Select Mask
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Contact Mask
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Metal Mask
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Other Cutaway Views
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Another View of FabTaken from slides by Jan Rabaey
From his text “Digital Integrated Circuits”
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Circuit Under Design
This two-inverter circuit (of Figure 3.25 in Rabaey’s text )will be manufactured in a twin-well process.
VDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
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Circuit Layout
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Start Material
Starting wafer: n-type withdoping level = 10 13/cm3
* Cross-sections will be shown along vertical line A-A’
A
A’
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N-well Construction
(1) Oxidize wafer(2) Deposit silicon nitride(3) Deposit photoresist
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N-well Construction
(4) Expose resist using n-wellmask
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N-well Construction
(5) Develop resist(6) Etch nitride and(7) Grow thick oxide
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N-well Construction
(8) Implant n-dopants (phosphorus)(up to 1.5 m deep)
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P-well Construction
Repeat previous steps
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Grow Gate Oxide
0.055 m thin
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Grow Thick Field Oxide
Uses Active Area mask
Is followed by threshold-adjusting implants
0.9 m thick
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Polysilicon layer
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Source-Drain Implants
n+ source-drain implant(using n+ select mask)
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Source-Drain Implants
p+ source-drain implant(using p+ select mask)
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Contact-Hole Definition
(1) Deposit inter-level dielectric (SiO2) — 0.75 m
(2) Define contact opening using contact mask
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Aluminum-1 Layer
Aluminum evaporated (0.8 m thick)
followed by other metal layers and glass