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Continuous-time DS Modulators with
Improved Linearity
and Reduced Clock Jitter Sensitivity
using the SCRZ DAC
Shanthi Pavan
Indian Institute of Technology, Madras
Chennai 600 036
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Work of my M.S students
– Timir Nandi, now at TI, India
– Karthikeya Boominathan
Part of this presented at
– CICC 2012
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Outline
Introduction
Limitations of conventional DAC pulses
Switched-C Return-to-Zero Principle
Modulator Architecture
Circuit Design
Measurement Results
Conclusion
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Motivation
Continuous-time DSMs
– Resistive input impedance
– Relaxed opamp gain requirements
Most high performance CTDSMs
– Multibit loops
Focus of this research
– Can we do better with single-bit loops ?
Case study
– 14 bit ENOB, 2 MHz Bandwidth, 0.18mm CMOS
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Multibit versus Single-bit
Modulators
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Design Targets
Dynamic Range 86dB (14 ENOB)
Bandwidth 2 MHz
Order 4
Quantizer 1 bit 4 bit
Out of Band Gain
OSR Needed
Sampling Rate
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Design Targets
Dynamic Range 86dB (14 ENOB)
Bandwidth 2 MHz
Order 4
Quantizer 1 bit 4 bit
Out of Band Gain 1.5
OSR Needed 64
Sampling Rate 256 MHz
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Design Targets
Dynamic Range 86dB (14 ENOB)
Bandwidth 2 MHz
Order 4
Quantizer 1 bit 4 bit
Out of Band Gain 1.5 2.5
OSR Needed 64 20
Sampling Rate 256 MHz 80 MHz
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ADC : 1 bit versus 4 bit
4 bit ADC
- 15x more comparators @ 1/3rd speed
- 5x more ADC power, 15x more area
- 15x loop filter & clock path loading
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DAC : 1 bit versus 4 bit
4 bit DAC
–Needs Dynamic Element Matching
–DEM adds excess delay & power
–Not very effective @ low OSR
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DAC : 1 bit versus 4 bit
Calibration
– Complex logic
A single bit quantizer consumes
lesser power
though it operates at 3x the speed
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Modeling Clock Jitter
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Clock Jitter Comparison
A 4-bit modulator can tolerate 15 times more
RMS white jitter compared
to a single bit design
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Loop Filter Linearity
1bit
4 bit Higher demands on
loop filter linearity
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Choice of Quantizer
Single bit quantizer
– Lower power ADC
– No DEM needed
– Sensitive to clock jitter
– Loop filter needs to be extremely linear
Try to fix this
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DAC Pulse Shapes : NRZ
Inherently nonlinear (rise-fall asymmetry)
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DAC Pulse Shapes : NRZ
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DAC Pulse Shapes : NRZ
Opamp virtual short
Modulator output
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DAC Pulse Shapes : RZ
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Digression : Weak Nonlinearities in
CTDSMs
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RZ DAC : Linearity
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RZ DAC : Jitter
Opamp virtual short
Modulator output
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DAC Pulse Shapes : RZ
Excellent linearity
Terrible for jitter !
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SC DAC
Capacitors are charged to ±Vref during Φ1
They are discharged into the loopfilter during Φ2
Charge transferred = ±CVref
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SC DAC
Capacitors are charged to ±Vref during Φ1
They are discharged into the loopfilter during Φ2
Charge transferred = ±CVref
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SC DAC with Jitter
Transfers most of the charge in a short period
Error due to clock jitter is smaller
Charge transferred = ±CVref
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SC DAC
DAC output peak current is higher
Higher demands on the linearity of the loop filter
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DAC Pulse Shapes : SC
Terrible linearity !
Excellent for jitter
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Introducing the SCRZ DAC
RZ DAC
– Excellent linearity
– High jitter sensitivity
SC DAC
– Low jitter sensitivity
– Poor linearity
SCRZ DAC
2Io
2Io
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Introducing the SCRZ DAC
Opamp inputs
DAC currents 2Io
2Io
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SCRZ DAC operation (Φ1)
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SCRZ DAC operation (Φ1)
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SCRZ DAC operation (Φ2)
2Io
2Io
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SCRZ DAC operation (Φ2 = 0.5Ts)
2Io
2Io
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SCRZ DAC operation (Φ3)
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SCRZ DAC operation (Φ3)
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Summary : Ideal Waveforms
With an ideal clock
With ideal current 2Io = CVref/(0.5Ts)
– Idac has an RZ pulse shape
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Effect of jitter
Ideal – f2 half clock cycle wide
Jittered - 0.5Ts + t
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Effect of jitter
Idac lasts longer than
0.5Ts
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Waveforms (Φ3)
Vxy = 0 at the end of f3
Idac is negative in f3
Φ3
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Total DAC Charge
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Total DAC Charge
Irrespective of
Jitter !
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Role of current source
Shapes the capacitor discharge pulse
Smaller peak current
Relaxed requirement - linearity of the loop filter
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Non ideality - Deviation of 2Io
2Io(0.5Ts) = CVref
Io,d = 2CVref/Ts
Capacitors completely discharged at the end of Φ2
Idac = 0 during Φ3
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If 2Io < Io,d
Capacitors are incompletely discharged
The residual charge is discharged during Φ3
Idac is positive during Φ3
Net charge supplied by the DAC remains ±CVref
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If 2Io > Io,d
Capacitors are over discharged
The capacitors are charged during Φ3
Idac is negative during Φ3
Net charge supplied by the DAC remains ±CVref
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Tune 2Io
• 2Io= Io,d, Vxy= 0
• Vxy < 0, 2Io > Io,d
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Tune 2Io
Comparator- sign of Vxy at the end of Φ2
Control Io to 6-bit accuracy
2Io
2Io
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Compare : SC versus SCRZ DAC
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Related Work : The SCSR DAC
Anderson et. al. : IEEE JSSC 2009
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Related Work : The SCSR DAC
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Target Modulator Specifications
Signal Bandwidth = 2 MHz
Sampling frequency = 256 MHz
Quantizer range = 3.6 Vpp,d
Target resolution = 14 Bits
0.18 μm CMOS process
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Noise Transfer Function
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Modulator Architecture
4th Order Cascade of Integrators
with Feed Forward (CIFF)
Active-RC Integrators
Capacitive Summation
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[1] S. Pavan and P. Sankar, “Power reduction in continuous-time delta sigma modulators using the assisted
opamp technique,” IEEE Journal of Solid-State Circuits., vol. 45, no. 7, pp 1365-1379, July 2010
Assisted Opamp Technique
0
No swing here
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Opamp Design
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Two Stage Feedforward Compensation
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Chip layout and test board
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Test Setup
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SN(D)R vs Input Amplitude
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PSD of modulator
Clock jitter
~ 1 ps rms
18 dB
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Controlled jitter experiment
FM modulated sampling clock
60 MHz Chosen so that RMS jitter is 50 ps
Agilent 33250A
Signal
Generator Clock source Modulator
FM Modulation Test Board
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PSD of modulator (jittery clock)
28 dB
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Effect of opamp assistance
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Performance Summary
Signal Bandwidth / Clock Rate 2 MHz / 256 MHz
Full Scale 3.6 Vpp,diff
Input Swing for peak SNR -2.75 dBFS
Dynamic Range/ SNR/ SNDR 87.1 dB/ 84.5 dB/ 82.3 dB
Active area 0.38 mm2
Process / Supply Voltage 180 nm CMOS / 1.8 V
Power (including references) 16.5 mW
FoM (SNR) 300 fJ/lvl
FoM (SNDR) 387 fJ/lvl
FoM (DR) 168 dB
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Comparison with other works
Reference This
Work
Anderson
JSSC09
Veldho
JSSC03
Gealow
VLSI11
Kim
VLSI11
BW (MHz) 2 1.92 1.23 1.92 1.95
DR (dB) 87 70 83 83 79
SNR (dB) 84.5 66.4 83 - 74.3
SNDR (dB) 82.3 62.4 - 78 73.3
Power (mW) 16.5 5.0 4.1 2.8 8.55
FoMDR (dB) 168 156 168 171 163
FoMSNR(fJ/lvl) 300 768 145 - 517
FoMSNDR(fJ/lvl) 387 1218 - 110 580
Tech. (nm) 180 90 180 40 65
Supply (V) 1.8 1.2 1.8 2.4/1.4 2.5
Sampling (MHz) 256 312 76.8 245.76 124.8
Feedback DAC SCRZ SCSR SCR CT-SI CT-SC
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Conclusions
Conventional feedback DACs have problems
– NRZ DAC : Rise-fall asymmetry
– RZ DAC : Jitter sensitivity
– SC DAC : Poor linearity
The SC-RZ DAC
– Good marriage of the SC and RZ DACs
A high performance CTDSM incorporating an
SC-RZ DAC
– 87 dB DR in a 2MHz bandwidth
– 16.6mW in a 180nm CMOS process