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Evening Panel
International Symposium on FPGAs, 2009
CMOS vs. NANO
Monterey, CaliforniaFebruary 23, 2009
Comrades or Rivals?
Co-chairs
Deming Chen
Russell Tessier
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Technology trend
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How low can we go?Future devices could theoretically scale down to – 1.5 nm – with 0.04 ps switching speeds – and 0.017 electron volts in terms of power
consumption.
J. Hutchby, G. Bourianoff, et al., Proc. of IEEE, 2003
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Can CMOS get there?
C. Hu, et al., IEDM, 2000
• Power challenges:
D. Barlage, et al., MRS, 2006
• Reliability challenges:
• Others: random doping variations, short channel effects, surface scattering …
• Process challenges: manufacturing solutions beyond 22nm are not known
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Alternativesnanowirescarbon nanotubesgrapheneIII-V-based chips spintronicsphase change logic devices interference devices optical switches…
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Case Study 1: nanowire (NW)
High-density logic
A. DeHon, et al., FPGA, 2004
The pitch of the NWs can be much smaller than lithographic patterning, using a bottom-up self-assembly process
High-density routing
G. Snider et al., Nanotechnology, 2007
High-density nanowirecrossbar memory
Y. Chen, et al. Nanotechnology, 2003
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Case Study 2: carbon nanotube (CNT)CNT device on delay and energy×delay product.
CNT bundle interconnect on delay and thermal conductance.
N. Srivastava, K. Banerjee, IEDM, 2005
R. Chau, et al., Trans. Nano., 2005
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Carbon nanotube (cont’)CNT-based nanoFPGA offers high density and high performance
BLE 1
BLE 2 BLE 4
BLE 3
FF
MUX
FF
MUX
FF
MUX
Input to BLE
Output from BLE
FF
MUX
VDD
VDDVDD
VDD
C. Dong, et al., FPGA, 2009
LUT design CLB design
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But, unsolved issues for NANO remain
High defect rate– In the HP crossbar memory, only 85% of the switches can
switch, where 50% of these ‘good’ switches can only switch once.
Variation beyond photolithography– Mixture of metallic and semiconducting CNTs– Distribution of CNT diameters
Fabrication challenges– Difficulty of fine-grained positioning of the CNTs– Problematic interface between CNT and contact
“It can be done on a lab scale, but we don't know how to put millions of them on a wafer.”
– Mike Mayberry, VP, technology manufacturing group, Intel.
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So, what will be the future of CMOS and NANO?
Are they
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A. Comrades?B. Rivals?C. Strangers?D. Too early to say?
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Best Picture from OSCAR 2009: "Slumdog Millionaire"
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Experts in the panelProf. Kaustav Banerjee– University of California, Santa Barbara
Dr. Mojy C. Chian – Technology Development, Altera
Prof. André DeHon– University of Pennsylvania
Dr. Shinobu Fujita– Corporate R&D Center, Toshiba
Dr. James Hutchby– Semiconductor Research Corporation (SRC)
Dr. Steve Trimberger– Xilinx Research Labs, Xilinx
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Detailed discussion itemsDoes NANO offer new capabilities that are sufficiently compelling for investment and learning?What impact, if any, will bottom-up fabrication have?What are the pros and cons of the CMOS/Nano hybrid solution?How will FPGAs fare in this disruption (if any) compared to others? Will it upset the balance of power?Do nanoscale issues force architectural changes and paradigm shifts? What are the trends? Who will be impacted?Will FPGA vendors take the lead in this new paradigm and opportunity?
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Kaustav BanerjeeKaustav BanerjeeUniversity of California, Santa BarbaraUniversity of California, Santa Barbara
FPGA’09, February 22–24, 2009, Monterey, CA
Panel: CMOS vs. Nano: Comrades or Rivals?
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
Major Challenges in CMOS/FPGAMajor Challenges in CMOS/FPGA
Interconnection
Powerconsumption
Processvariation
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
Power Consumption in Power Consumption in FPGAsFPGAs
Xilinx Virtex II Dynamic power breakdown
Shang, et al. FPGA. 2002
Interconnect
Logic
ClockingIOBs
16% 60%14%
10%
Interconnect
Configuration SRAM Cells
LUTsOther
38%
34%12%
16%
Xilinx Spartan-3 Leakage power breakdown
Tuan et al., CICC. 2003
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
So, What Can Be Done?So, What Can Be Done?
Nanotechnologies offer potential solutionsNanotechnologies offer potential solutions……
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
Carbon Based Interconnect MaterialsCarbon Based Interconnect Materials
Carbon Nanotubes Mono-layer GrapheneNano-Ribbon
Roll-up Pattern
Graphene
Stack andPattern
Multi-layer GrapheneNano-Ribbon
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
CNT vs. Cu InterconnectsCNT vs. Cu InterconnectsD
elay
Rat
io w
.r.t C
u
PerformanceLi et al., TED 2009 (in press)
Thermal/ReliabilitySrivastava et al., IEDM 2005
Power DissipationSrivastava et al., TNT 2009 (in press)
tota
l buf
fer w
idth
(ti
mes
min
imum
)
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
CNT Interconnect FabricationCNT Interconnect Fabrication……
[Nihei et. al., (Fujitsu) IITC, 2007]
[Sato et. al., (Fujitsu) IITC, 2006][Kreupl et. al., (Infineon) IEDM, 2004]
[Choi et. al., (Samsung) Nano Conf., 2006]
[Awano et al., (Fujitsu) 2006]
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
Integration with Cu/LowIntegration with Cu/Low--k Dielectrick Dielectric
CNT Single Kelvin via CNT Single Kelvin via grown at 400 grown at 400 00CC
CNT via is robust under current highCNT via is robust under current high--density density stress over long timestress over long time……....
A. Kawabata et. al., IITC, 2008
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
Leakage Increases with ScalingLeakage Increases with Scaling
Device Scaling
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
SubSub--threshold Slope Engineeringthreshold Slope Engineering
[ ] 10ln1log1
qkT
CC
dVIdS
ox
dm
g
d⎟⎟⎠
⎞⎜⎜⎝
⎛+=⎟
⎟⎠
⎞⎜⎜⎝
⎛=
−
NEMNEM--FET, NWFET,FET, NWFET,FeFe--FETFET
TFET, IMOSTFET, IMOS
Dadgour et al., DAC 2007
Sub
thre
shol
d sw
ing
(mV/
deca
de)
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K. Banerjee, UCSB PANEL: FPGA’09, February 22–24, 2009, Monterey, CA
ConclusionsConclusions
CMOS: mature and experienced
Emerging nano-technologies: energetic but inexperienced
CMOS still rules!
Hybrid technologies….way to go!
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© 2009 Altera Corporation
Inflection Point for FPGA
Mojy C. ChianVP, TechnologyAltera CorpFeb ‘09
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2
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Scaling: The Good, Bad and UglyScaling: The Good, Bad and Ugly
� Good:− Higher density− Higher performance & throughput− More features & functionality− Lower power per function− Lower cost per function
� Bad and Ugly:− Higher development cost development− Higher unit cost (wafer)− Increasing complexity− Increasing variability− Higher total power (for fixed die size)
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3
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
ITRS Performance ScalingITRS Performance Scaling
� Introduction of multigate transistor (MuGFET) delayed to 2015� Lgate scaling slowing to ~0.71x every 3.8 years
� Intrinsic speed increase of ~13% per year, down from ~17% per year
1000
10000
2008 2010 2012 2014 2016 2018 2020 2022
Calendar Year
1/T
au (G
Hz)
Planar Bulk
UTB FD SOI
Multiple Gate
From 2008 ITRS Update
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4
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
The Ideal Routing SwitchThe Ideal Routing Switch
� Lower Vcc and higher leakage pose increasing challenges for implementing FPGA routing switch.
� Replacement of routing pass gate could enable significant performance/power benefit.
Parameter ValueNon-volatile YesNumber of Terminals 2 or 3On Resistance < 500 OhmsOff Resistance > 1E9 OhmsProgram/Erase Time >1000 cells/usProgram Current <100 uAProgram Voltage > VccErase Voltage > VccOperating Temp Range From -40 C to 125 CLifetime 10 yearsPlacement of switches No restrictionSEU no SEUon/off cycles >10,000Availability Lead process node
“Ideal” Routing Switch Attributes
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5
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Process Technology: Friend or Foe?Process Technology: Friend or Foe?
� Adopting advanced process technologies
Increased complexity and slow down in benefits?
� But …… ..
We have opportunities ahead like never before
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6
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
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7
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Chip Development Business ModelChip Development Business Model� Cost:
− Development cost: NRE− Unit cost: COGS
� FPGA versus ASIC/ASSP: − Trade off of NRE and COGS− Low volume: emphasis on NRE reduction− High Volume: emphasis on COGS reduction
� Reality check – an example:− R&D = $100M− Market Share = 20%− ASP = $20− R&D = 20% of revenue− � TAM = $2.5B (there are not too many markets of this size)− Many low volume ASIC/ASSP providers have a broken bu siness model
� The financial model is not sustainable� The situation is exasperated with increased R&D cos t for newer technologies
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8
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
ASIC % Design Starts by TechnologyASIC % Design Starts by Technology
76421000000.040 µm
Process Node
2002
%
2003
%
2004
%
2005
%
2006
%
2007
%
2008
%
2009
%
2010
%2011
%
0.022 µm 0 0 0 0 0 0 0 0 0 0
0.032 µm 0 0 0 0 0 0 0 1 2 2
0.045 µm 0 0 0 0 0 1 2 4 6 7
0.065 µm 0 0 0 1 2 6 8 10 13 15
0.09 µm 0 1 8 13 18 23 23 24 24 24
0.13 µm 18 37 42 29 29 27 27 25 24 24
0.18 µm 38 27 23 20 17 14 12 10 10 8
0.25 µm 16 15 12 12 11 9 9 8 7 6
0.35 µm 21 16 12 12 11 10 8 8 6 5
0.5 µm 5 4 3 7 7 6 6 5 4 4
L>0.5 µm 1 1 0 6 6 6 5 5 5 5
Total 100 100 100 100 100 100 100 100 100 100
#1 ASIC Design Technology
Inte
gra
tio
n, L
ow
er C
ost
, Per
form
ance
60
Dev.
Costs $M
110
80
60
55
30
20
13
5
3
2
<1 Incr
ease
d R
isks
& D
evel
op
men
t C
ost
Source: Altera & Gartner
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9
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
ASIC % Design Starts by TechnologyASIC % Design Starts by Technology
76421000000.040 µm
Process Node
2002
%
2003
%
2004
%
2005
%
2006
%
2007
%
2008
%
2009
%
2010
%2011
%
0.022 µm 0 0 0 0 0 0 0 0 0 0
0.032 µm 0 0 0 0 0 0 0 1 2 2
0.045 µm 0 0 0 0 0 1 2 4 6 7
0.065 µm 0 0 0 1 2 6 8 10 13 15
0.09 µm 0 1 8 13 18 23 23 24 24 24
0.13 µm 18 37 42 29 29 27 27 25 24 24
0.18 µm 38 27 23 20 17 14 12 10 10 8
0.25 µm 16 15 12 12 11 9 9 8 7 6
0.35 µm 21 16 12 12 11 10 8 8 6 5
0.5 µm 5 4 3 7 7 6 6 5 4 4
L>0.5 µm 1 1 0 6 6 6 5 5 5 5
Total 100 100 100 100 100 100 100 100 100 100
#1 PLD Design Technology#1 ASIC Design Technology
Inte
gra
tio
n, L
ow
er C
ost
, Per
form
ance
60
Dev.
Costs $M
110
80
60
55
30
20
13
5
3
2
<1 Incr
ease
d R
isks
& D
evel
op
men
t C
ost
Source: Altera & Gartner
FPGA
FPGA
FPGA
FPGA
FPGAFPGA
FPGAFPGA
FPGA FPGA FPGA
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© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Average ASIC DensityAverage ASIC Density
Note: Data based on Gartner Dataquest
0
1
2
3
4
5
6
7
8
9
10
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
Util
ized
logi
c ga
tes
(mill
ions
)
Est. avg. logic gate counts (the Americas) Stratix logic gates
10
11
12
13
130nm FPGA
65nm FPGA
90nm FPGA
40nm FPGA
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11
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
FPGA to Full ASIC PathFPGA to Full ASIC Path
NRE
Unit Cost
FPGA
Hardened FPGA FPGA companion base die with 5 masks programmable
Full ASIC
Re-Packaged FPGAFPGA Companion die in a smaller package
� Solution points in NRE – Unit Cost Space− Rationalized volume forecast is the key to strategy
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12
© 2009 Altera Corporation
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
SummarySummary− Significant challenges exist for technology scaling
� We are in the era of power-constrained scaling� Variability will continue to increase
− Innovations expected to enable continued scaling� HKMG, MuGFETs, high-mobility channels, …
− But they increase complexity and cost− Bifurcation in ASIC/ASSP offerings
� Only a small portion can afford adopting advanced technologies
� This is all music for FPGA− The most significant opportunities for FPGA is in share gain from
ASIC & ASSP− Advanced process technologies are tipping the scale in favor of
FPGA− We are at an inflection point
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DeHon--FPGA panel 2009
Position
1. Beneficial to work with nature (physics).2. Atomic-scale is noisy and statistical.3. Fine-grained reconfiguration and
continuous adaptation are powerful.4. Regularity is good.5. Randomness can be harnessed for good.6. Lithographic CMOS is the new PCB.
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DeHon--FPGA panel 2009
Beneficial to work withnature
• …rather than against it.• Atomic-scale offer:
– New switching/communication phenomena– New ways to define structures, dimensions,
and spacing– New ways to perform assembly
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DeHon--FPGA panel 2009
Beneficial to work withnature
• Deeper understanding atomic-scale physics– Increases our palette better solutions
• Favorable E,D,A tradeoffs, cheaper manufacture
See: http://www.dna.caltech.edu/Papers/DNAorigami-nature.pdffor some wonderful images of DNA Assembly and detailson how to perform the assembly.
See: http://physci.llnl.gov/Research/qsg-090205/carbonNanotubes.htmlfor images of CNT growth.
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DeHon--FPGA panel 2009
Beneficial to work with nature
• …but today, we are stumbling our through it like clumsy, ignorant giants
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DeHon--FPGA panel 2009
Atomic-scale is noisy and statistical.• The nature of atomic-scale
elements is statistical.– anything we build a this scale
• Lithographic or bottom up– ….will behave statistically
• kT, uncertainty principle, tunneling, ….
• Will lead to– Defects, Variation, Misbehavior
• Current approaches are brute force attempts to hide this nature– Millions of electrons, thousands of dopants, large
noise margins.
…work with naturenot against it.
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DeHon--FPGA panel 2009
Fine-Grained Reconfiguration• Selecting devices role mapping after
fabrication is powerful.– Mitigation fabrication
statistics• Defects• variation
– Mitigate lifetimechanges
• FPGA-like architectures have a potential head-start over alternatives.
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DeHon--FPGA panel 2009
Regularity • Regular structures easier to self-assemble
– Low information content– Exploit natural phenomena
• E.g.– Large area 50 nm period grating by multiple nanoimprint
lithography and spatial frequency doubling. B Cui, Z Yu, H Ge, and SY Chou, APPLIED PHYSICS LETTERS, 90, 043118 (2007)
– http://www.research.ibm.com/journal/rd/515/black.html– Large-Scale Hierarchical Organization of Nanowire Arrays for
Integrated Nanosystems. D. Whang and S. Jin and Y. Wu and C. M. Lieber, Nanoletters, 3(9):1255—1259, Sept. 2003.
• FPGA-like architectures exploit regularity– While providing diversity for computation
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DeHon--FPGA panel 2009
Randomness
• Can be a tool for good– Diversity creation – Expanders (LDPCs, network routing)– CAD– Randomized Algorithms– Heavily exploited by nature
• …work with nature.
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DeHon--FPGA panel 2009
CMOS is the new PCB
• Differential Reliability – Islands of stability & determinism
• diagnose, supervise, configure
• Lithographic CMOS does this well• Provides the substrate on which atomic-
scale things can be assembled• Goal: reliability of CMOS with {E,D,A} of
atomic-scale building blocks– Compare DRAM memories
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DeHon--FPGA panel 2009
Position
1. Beneficial to work with nature.2. Atomic-scale is noisy and statistical.3. Fine-grained reconfiguration and
continuous adaptation are powerful.4. Regularity is good.5. Randomness can be harnessed for good.6. Lithographic CMOS is the new PCB.
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S. Fujita, International Symposium on FPGA ’09
Nano-electronics for Near-Future FPGA
Shinobu Fujita
Corporate R&D CenterToshiba Corporation
R&D of Nano-electronics and their Applications
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S. Fujita, International Symposium on FPGA ’09
0
500
1000
1500
2000
2500
3000
3500
4000
4500
2002 2003 2004 2005 2006 2007 2008Source: iSuppli
FPGA Sales
FPGA needs something other than CMOS scaling for future?
Forecast (2005)
FPGA cannot replace ASIC enough..(Power, Area, Speed..)
(M$)
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S. Fujita, International Symposium on FPGA ’09
CMOS
FPGA
Current FutureNear Future
FPGA vs ASIC after CMOS ending
CMOS
ASIC
65nmCMOS
32nmCMOS
45nmCMOS
22nmCMOS
32nmCMOS
16nmCMOS
Ending…Cost(/Performance) is too bad..
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S. Fujita, International Symposium on FPGA ’09
CMOS(65nm,40nm, 32nm..)
NAND-flashROM
NewPost-Si
Transistor
NewPost-Si
Technologies(non-volatile
memory)
Current Future
Time gap…
Current FPGA Architecture Nano Architecture
Near Future
Gap between current FPGA and Future Nano-electronics?
Dilemma..Cost increasemakes CMOS ending..
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S. Fujita, International Symposium on FPGA ’09
CMOS(65nm,40nm, 32nm..)
NAND-flashROM
NewPost-Si
Transistor
NewPost-Si
Technologies(non-volatile
memory)
Current Future
Current FPGA Architecture Nano Architecture
Near Future
CMOS-ExDSS-FETFIN-FET
Nanowire-FET
New-nonvolatileMemories
PRAM, FeRAM,MRAM, ReRAM,
(mature process)
Solutions for Near Future FPGA!
Cons:Very HighParasitic
Resistance…
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S. Fujita, International Symposium on FPGA ’09
CMOS-Ex for FPGA
Doped-Si SD
Parasiticresistance
Silicide
n+-type Si
electron
gate
Metal SD
Silicide
Dopant Segregation
gate
DopantDopant Segregated Schottky (DSS) Segregated Schottky (DSS) MOSFETsMOSFETs
Segregated dopants at the S/D interface efficiently reduce Segregated dopants at the S/D interface efficiently reduce Schottky barrier height.Schottky barrier height.Low Source/Drain resistanceLow Source/Drain resistance(Superior performance of PASS Transistor logic!!)(Superior performance of PASS Transistor logic!!)
--Short channel effect immunityShort channel effect immunity--Enhanced carrier injection velocity Enhanced carrier injection velocity
(A. Kinoshita et al, (Toshiba), IEDM 2006)(A. Kinoshita et al, (Toshiba), IEDM 2006)
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S. Fujita, International Symposium on FPGA ’09
CMOS-Ex for FPGADopantDopant Segregated Schottky (DSS) Segregated Schottky (DSS) MOSFETsMOSFETs
Superior performance of PASS Transistor logic!! Superior performance of PASS Transistor logic!! Also, CMOS performance is superior to conventional one. Also, CMOS performance is superior to conventional one.
(T. Kinoshita et al, (Toshiba), IEDM 2006)(T. Kinoshita et al, (Toshiba), IEDM 2006)
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S. Fujita, International Symposium on FPGA ’09
VDD
VSS=GND
VDD
VSS
High
High
High
High
Vout=Low->High
Low
Vs-d~1/4*Vout
Vsd
Id(∝Ron)
time
Vsd
1/4Vdd
Vdd
1/4Vdd
Vs-d~1/4*Vout
Vs-d~1/4*Vout
Vs-d~1/4*Vout
DSS
Conventional
Higher currentat lower Vsd(DSS-MOSFET)
Pass Tr. Logic(FPGA)
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S. Fujita, International Symposium on FPGA ’09
New-nonvolatile Memories for FPGA
0 1 2 3 4 5
0
0.005
0.01
0.015
0.02
Voltage [V]
Cur
rent
[A]
Voltage Forming
Turn Off
Turn On
0 1 2 3 4 510
-12
10-10
10-8
10-6
10-4
10-2
100
Cur
rent
[A]
Voltage Forming
Turn Off
Turn On
Voltage [V]
On/Off R ratio>107
TiOx based RAM
SRAM-based configuration
NV-RAM
Non-Volatile-RAM-based
W. Wong et al,( Stanford, Toshiba) IEDM 2006
ReducePower &Area
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S. Fujita, International Symposium on FPGA ’09
Thank you!!
High off-Resistance (to reduce leakage current)
( <100pA, = 1V/10Gohm!) @100x100nm2
High On/Off ratio …. At least >100, or >106
Programming voltage: higher than Vdd of CMOS
Long-term retention: > 10years
Long-term reliability: NO memory disturbance during logic operation
Plus.. decreasing programming current
Requirement to NV-RAM for replacing config-SRAM
Different requirements from those for memory circuits!
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S. Fujita, International Symposium on FPGA ’09
CMOS(65nm,40nm, 32nm..)
NAND-flashROM
NewPost-Si
Transistor
NewPost-Si
Technologies(non-volatile
memory)
Current Future
Current FPGA Architecture Nano Architecture
Near Future
CMOS-ExDSS-FET
New-nonvolatileMemories
PRAM, FeRAM,MRAM, ReRAM,
(mature process)
ConclusionSolutions for Near Future FPGA!
Important Bridge between Two
Thank you!
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Work in Progress --- Not for Publication1 ERD WG 3/18/09 Brussels FxF Meeting
FPGA ‘09 Evening PanelCMOS vs. Nano: Comrades or
Rivals?
CMOS Extension and “Beyond CMOS”Information Processing Technologies
February 23, 2009
Jim Hutchby - SRC
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Work in Progress --- Not for Publication2 ERD WG 3/18/09 Brussels FxF Meeting
FPGA ‘09 Evening PanelCMOS vs. Nano: Neither -They
are Family
CMOS Extension and “Beyond CMOS”Information Processing Technologies
February 23, 2009
Jim Hutchby - SRC
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Work in Progress --- Not for Publication3 ERD WG 3/18/09 Brussels FxF Meeting
Evening PanelCMOS vs. Nano: Comrades or
Rivals?
CMOS Extension and “Beyond CMOS”Information Processing Technologies
February 23, 2009
Jim Hutchby - SRC
FPGA ‘09 Evening PanelCMOS IS NANO IS
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Work in Progress --- Not for Publication4 ERD WG 3/18/09 Brussels FxF Meeting
Well doping
channelDepletion layer
isolation
halo
CMOS IS NANO
Critical dimension < 100nmGate length & Channel thickness
New physics for nano deviceQuantum confinement in channel
Channel
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Work in Progress --- Not for Publication5 ERD WG 3/18/09 Brussels FxF Meeting
End of the Road map??
NO!
Geometrical Scaling Functional Scaling
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Work in Progress --- Not for Publication6 ERD WG 3/18/09 Brussels FxF Meeting
The Reign of CMOS Continues –Geometrical Scaling will Shift to Functional Scaling
ITRS ERD & ERM are evaluating devices and technologies to extend CMOS to and beyond 2024ITRS ERD & ERM are looking for novel solutions for
information processing for applications beyond 2024Integrated with CMOS platformEventually stand alone
Heterogeneous integration of diverse functions (e.g., NEMS, Sensors, Analog, RF, Bioelectronics, etc.) in “Functional Diversification” is changing technology requirements for integrated electronics..
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Content Source: ITRS 2008 Update Public Conference Draft 0 – December, Seoul Korea
7
Moore’s Law & MoreMore than Moore: Diversification
Mor
e M
oore
: M
inia
turiz
atio
nM
ore
Moo
re:
Min
iatu
rizat
ion
Combining SoC and SiP: Higher Value SystemsBas
elin
e C
MO
S: C
PU, M
emor
y, L
ogic
BiochipsSensorsActuators
HVPowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm...V
130nm
90nm
65nm
45nm
32nm
22nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Beyond CMOS
2007 ITRS Executive Summary
Traditional ORTC Models
[Geo
met
rical
& E
quiv
alen
t sca
ling]
Scal
ing
(Mor
e M
oore
)Functional Diversification (More than Moore)
Continuing SoC and SiP: Higher Value Systems
HVPower Passives
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8 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
DRAM ½ Pitch (nm) (contacted) 65 57 50 45 40 36 32 28 25 22 20 18 16 14MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) 68 59 52 45 40 36 32 28 25 22 20 18 16 14
MPU Physical Gate Length (nm) 25 22 20 18 16 14 13 11 10 9 8 7 6 6Lg: Physical Lgate for High Performance logic (nm) [1] 25 22 20 18 16 14 13 11 10 9 8 7 6 5.5 5 4.5Effective Ballistic Enhancement Factor , Kbal [12]
Extended Planar Bulk 1 1 1 1 1 1 UTB FD 1.05 1.1 1.16 1.2 1.24 1.28 DG 1.17 1.25 1.31 1.37 1.53 1.67 1.87 1.99 1.97 2.11 2.11 2.11
Ultimate CMOS scaling needs new channel materials with enhanced ballistic velocity
2007 High Performance Logic Roadmap Illustrating Need for New High-velocity Channel Materials
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FPGA ‘09 Evening Panel Discussion – March 2009
[ ITRS DRAM/MPU Half-Pitch Timing: 2007[7.5] 2010 2013 2016 2019]
9
2007/08 - PIDS/FEP - Simplified Transistor Roadmap [Examples of “Equivalent Scaling” from ITRS PIDS/FEP TWGs]
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)
65nm 45nm 32nm 22nm
PDSOI FDSOI
bulk
stressors + substrateengineering
+ high µ SiGematerials
MuGFETMuCFET
elec
tros
tatic
con
trol
SiON
poly
high k
metal
gate stack
planar 3D
16nm
Work in Progress– Do Not Publish
+ III/V High µAlternative
Channel Mat’s
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Work in Progress --- Not for Publication10 ERD WG 3/18/09 Brussels FxF Meeting
Alternate Channel Materials and Structures for Extending CMOS
Alternate channel materials and structures for extending CMOS beyond silicon & III-V compound semiconductors include: − Nanowires, − Nanotubes, and − Graphene
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11 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
Nanotube FET
Band gap: 0.5 – 1 eVOn-off ratio: ~ 106
Mobility: ~ 100,000 cm2/Vsec @RTBallistic @RT ~ 300-500 nmFermi velocity: 106 m/sec (VF)Max current density > 109 A/cm2
Vsd (V)0-0.4-0.8-1.2
I sd(μ
A)
Ph. Avouris et al, Nature Nanotechnology 2, 605 (2007)
Schottky barrier switching
Very High velocity
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12 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
Nanowire FET
SET
Channel 1-dimensional Island/quantum dot
Channel length 5 – 10nm 1 – 10nm1
Capacitance aF aFConductance Channel
resistance or electron-injection
limited 10 –100mS
Tunnel-limited0.02 – 2mS
Gain High/marginal Low2
ON/OFF state Single Multiple
Nanowire & Single Electron Transistors
Single Electron Transistor
Nanowire Transistor
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How low can we go?Future devices could theoretically scale down to – 1.5 nm – with 0.04 ps switching speeds – and 0.017 electron volts in terms of power
consumption.
J. Hutchby, G. Bourianoff, et al., Proc. of IEEE, 2003
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CMOS scaling on track to obtain physical limits for electron devices
0.01
0.1
1
10
100
0.001 0.01 0.1 1LGATE (μm)
Gate Delay(ps)
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
0.001 0.01 0.1 1LGATE (μm)
Switching Energy
(fJ)
Bolzmann-Heisenberg Limit 3kBTln2
George Bourianoff / Intel
104kBT
500kBT
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15 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
Graphene Electronics: Conventional & Non-conventional
Cheianov et al. Science (07)
Graphene Veselago lense
Nonconventional Devices
Trauzettel et al. Nature Phys. (07)
Graphene pseudospintronicsSon et al. Nature (07)
Graphene Spintronics
Conventional Devices
FETBand gap engineered Graphene nanoribbons
Graphene quantum dot
(Manchester group)
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16WIN 16
Spin FET
Ge
MnGe
Al2O3
Al
Al
JingJing Chen and KL Wang et al., App. Phys. Letts. 90, 012501 2007
Schematic Spin gain FET structure with a MnGe/SiGe quantum well.
Transistor with Memory
-3000 -2000 -1000 0 1000 2000 3000
-2
-1
0
1
2
Mom
ent (
10-5
emu)
Field (Oe)
-3V -6V -12V -30V 0V 30V
MnGe on n-type Ge substrateField-Effect
Field Effect in DMS Confirmed
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17 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
Supplementing CMOS
General Purpose Processor
Basis of Existing Assessments of Logic Devices
A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization
SOC-PE Architecture
PEMainProc.
MainMemory
Peripherals
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE PE
Function A Function B Function C
Function D Function E
Multi-Core/Accelerator Engine Platform (SOC-MC/AE Architecture)
Multi-Cores
Accelerator Engine
Accelerator Engine
Accelerator Engine
Accelerator Engine
On-Demand Acceleration
Hi Speed Hi Speed Hi Speed
Connectivity
L3 Cache
Non-Blocking Switch Fabric
Memory Control
System Functions
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
SOC-PE Architecture
PEMainProc.
MainMemory
Peripherals
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE PE
Function A Function B Function C
Function D Function E
SOC-PE Architecture
PEMainProc.
MainMemory
Peripherals
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE PE
Function A Function B Function C
Function D Function E
Multi-Core/Accelerator Engine Platform (SOC-MC/AE Architecture)
Multi-Cores
Accelerator Engine
Accelerator Engine
Accelerator Engine
Accelerator Engine
On-Demand Acceleration
Hi Speed Hi Speed Hi Speed
Connectivity
L3 Cache
Non-Blocking Switch Fabric
Memory Control
System Functions
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core/Accelerator Engine Platform (SOC-MC/AE Architecture)
Multi-Cores
Accelerator Engine
Accelerator Engine
Accelerator Engine
Accelerator Engine
On-Demand Acceleration
Hi Speed Hi Speed Hi Speed
Connectivity
L3 Cache
Non-Blocking Switch Fabric
Memory Control
System Functions
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Multi-Core
L2 Cache
Courtesy Fawzi Behmann - Freescale
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FPGA ‘09 Evening Panel Discussion – March 2009 18
Top down information processing Image Recognition
Tadashi Shibata, University of Tokyo
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19 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
Image recognition
Tadashi Shibata, University of Tokyo
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20 ERD 2008 NSF NSEC Review – Washington, DC – 3 December 2008
SummaryGeometrical and functional scaling is projected by the
ITRS into the 2020’s and likely beyond.– New MOSFET device structures are available– New “Channel Replacement” materials are being explored– Combinations of new materials & new structures are being
investigated.Several new “Beyond CMOS” switching phenomena and
“State Variables” are being pursued for new information processing approaches− No approach has been shown as a clear winner− Carbon-based Nanoelectronics has significant potential
New markets requiring Functional Diversification will become important technology driver
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CMOS vs. Nano:
Steve TrimbergerSafe-Harbor Statement: This document
contains forward-looking statements. Opinions
expressed in this presentation are my own and
do not necessarily represent the opinion of my
employer or my employer’s marketing
department.
No contest.
“Next week I plan to think about the option of using
technology that isn’t yet available.”
- Wally in Dilbert 2007. Scott Adams
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
Engineering Fiction
Nano-scale FPGA!Godzilla!Tell fanciful stories
Design a NAND gate
from CNT switches
Dinosaurs had thick
skin
Cite real, unimpeachable
data
Nano fabrication
facilities
Large creatures can
survive unnoticed
under the oceans
Postulate an infrastructure
around it
Scale up to
manufacturability:
quality, reproducibility
Mutations can cause
creatures to grow to
enormous size
Ignore limitations
Carbon nanotubesRadiation induces
mutation
Cite a new effect or
technology
Engineering FictionScience FictionAction
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
Separating Fact From Fiction
Why CMOS for
FPGAs today?
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
Questions to the Panel
1) Do atomically-engineered materials and fabrication techniques offer new capabilities that are sufficiently compelling to encourage the necessary investment and learning?– Yes, better is better.
2) What impact, if any, will bottom-up fabrication have---augment lithographic processes, replace lithography, or remain a lab curiosity?– Despite problems with optical lithography (see next slide), any
displacing technology will need to give superior quality and reliability. You will know they’re getting serious when they talk about purification techniques.
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
Source: Nikon: http://www.nikonprecision.com/newsletter/summer_2008/toshiba_litho_2008.pdf
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
Questions to the Panel
1) Do atomically-engineered materials and fabrication techniques offer new capabilities that are sufficiently compelling to encourage the necessary investment and learning?– Yes, better is better.
2) What impact, if any, will bottom-up fabrication have---augment lithographic processes, replace lithography, or remain a lab curiosity?– Despite problems with optical lithography, any displacing technology
will need to give superior quality and reliability. You will know they’re getting serious when they talk about purification techniques.
3) What are the pros and cons of the CMOS/Nano hybrid solution?– Cost effective: only apply new technology where needed.
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
Questions to the Panel
4) How will FPGAs fare in this disruption (if any) compared to alternatives (ASICs, processors, multi/many-cores)? Will it upset the balance of power (Intel, Xilinx, Altera, HP, WindRiver, XtremeData, startups)?– Fabrication technology won’t change the balance of power, unless
only one player can get it. Nano is so difficult that it is likely it requires the entire industry to produce it. Then all will have it.
5) Do nanoscale issues force architectural changes and paradigm shifts? What are the trends? Who will be impacted (FPGA designers, FPGA CAD, FPGA users)?– Circuits may change. No change to the model is required. “We do
Deep Sub-Micron design, so you don’t have to” If necessary, we’ll do Nano, so you don’t have to.
6) Will FPGA vendors take the lead in this new paradigm and opportunity? Or, are they so risk-averse that they will leave it to startups?– No. FPGA vendors are too smart to take the lead. Notice that they
don’t take the lead in process development or computer development today.
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
� Nano might work
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Steve Trimberger FPGA 2009 © Copyright 2009 Xilinx
� Nano might work someday.
� But we are WAY too early.
� And there’s plenty to do right now that will benefit our
customers.