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Sequential statement ofVHDL
VHDL process Sequential signal assignment statement
Variable assignment statement
If statement
Case statement
For loop statement
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VHDL process
Contains a set of sequential statements. The whole process is a concurrent statement.
Ma or ma not be able to be mappe! to
phsical har!ware.
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"rocess with sensiti#it list
process$sensiti#it%list&!eclarations'
begin
sequential statement'
sequential statement'
...
en! process'
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"rocess
( process is acti#ate! when a signal the sensiti#it list changes its #aluethen e)ecutes sequentiall.
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"rocess signal a*b*c*+ st!%logic'
process$a*b*c&
begin
,- a an! b an! c'
en! process'
This is interprete! as a input (/D gate
process$a&
begin
,- a an! b an! c'
en! process'
Interprete! as input (/D gate with memor elements $unwante!&
For a combinational circuit* all input shoul! be inclu!e! in the sensiti#it list
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0ait statements
"rocess continues the e)ecution until a wait statement is reache! an! then suspen!e!
Forms of wait statement+
1 wait on signals'
1 wait until boolean%e)pression'
1 wait for time%e)pression'
2input an! circuit
process
begin
,- a an! b an! c'
wait on a* b* c'
en! process'
( process can ha#e multiple wait statements
"rocess with sensiti#it list is preferre! for snthesis
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Sequential signalassignment statement signal%name ,- #alue%e)pression' Snta) is i!entical to the simple
concurrent signal assignment
Insi!e a process* a signal can beassigne! multiple times* but onl thelast assignment ta3es effect
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Sequential signalassignment statement
process$a*b*c*!&begin
,- a or c'
,- a an! b'
,- c an! !'
en! process'
process$a*b*c*!&begin
,- c an! !'
en! process'
The are the same 4
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Variable assignmentstatement
Snta) #ariable%name +- #alue%e)pression'
(ssignment ta3es effect imme!iatel
/o time !imension $i.e.* no !ela& 5eha#e li3e #ariables in C
Difficult to map to har!ware $!epen!ing on conte)t&
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Variable assignmentstatement process$a*b&
#ariable tmp+ st!%logic'
begin
tmp +- 676'
tmp +- tmp or a'
tmp +- tmp or b'
,- tmp'en! process'
process$a*b&
#ariable tmp7* tmp8* tmp9+ st!%logic'
begin
tmp7 +- 676'
tmp8 +- tmp7 or a'
tmp9 +- tmp8 or b'
,- tmp9'en! process'
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IF statement
Snta)if boolean%e)pr%8 then
sequential%statements'
elsif boolean%e)pr%9 then
sequential%statements'
else
sequential%statements'
en! if'
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IF statement
:)amples2 ; to 8 Multiple)er 1 Home wor3
2 9 to ; Deco!er 1 Homewor3
2 ; to 9 "riorit enco!er
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Comparison with con!itionalsignal assignment
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:)ample+ Fin! the ma) of operan!s
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Sharing boolean con!ition
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Incomplete branch
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Incomplete signalassignment
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Conceptual interpretation
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Conceptual interpretation
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Case statement Snta)
case case%e)pression is
when choice%8 -e!uce! =or
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Conceptualimplementation
?nrolling the loop0i!e )or +
$&,- a$& )or b$&'
$9&,- a$9& )or b$9&'
$8&,- a$8& )or b$8&'
$7&,- a$7& )or b$7&'
?se! for repetiti#e co!ere!uce! )or +
temp$7& ,- a$7&
temp$8& ,-a$8& )or temp$
temp$9& ,-a$9& )or temp$
temp$& ,-a$& )or temp$
,- temp$&'
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/otes
Concurrent statements ha#e clear*!irect mapping to phsical structures
Sequential statements can be !ifficult
to be reali@e! in har!ware