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CHAPTER 4
VARIABLE SWITCHING FREQUENCY CARRIER BASED
PULSE WIDTH MODULATION
4.1 INTRODUCTION
The main objective of this chapter is to analysis the performance of
variable switching frequency carrier based pulse width modulation
techniques. The reference voltage is continuously compared with each of the
variable frequency carrier signals. The VSFPWM technique is divided into
two types, such as PD and POD PWM techniques.
• Phase disposition where all the carriers are in phase with
variable frequency.
• Phase opposition disposition where the carriers above the zero
reference are inphase with low frequency but shifted by 180º
from those carriers below the zero reference with high
frequency.
The above PWM techniques are analyzed using SH and SFO methods.
4.2 PHASE DISPOSITION PULSE WIDTH MODULATION
For n-level converter, (n-1) carrier signals with the variable
frequency and peak to peak amplitude are placed in such a way, that they
occupy continuous bands between the positive and negative dc rail of the
inverter. The reference waveform has peak to peak amplitude, the frequency,
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and it is zero centered in the middle of the carrier set. If the reference is
greater than carrier signal, then the active device corresponding to that carrier
is switched off.
The operating rules for VSF PD method when the number of level
n = 5 are given below:
• The n – 1 = 4 carrier waveforms are arranged with variable
frequency. All the carrier waveforms are inphase.
• The converter switches to + Vdc when the reference is greater
than all the carrier waveforms.
• The converter switches to Vdc / 2 when the reference is less than
the uppermost carrier waveform and greater than all other
carriers.
• The converter switches to 0 when the reference is less than the
two uppermost carrier waveform and greater than two
lowermost carriers.
• The converter switches to - Vdc / 2 when the reference is greater
than the lowermost carrier waveform and lesser than all other
carriers.
• The converter switches to -Vdc when the reference is lesser than
all the carrier waveforms.
4.2.1 Subharmonic PWM
In SHPWM technique the intersection of the triangular carrier and
the modulation wave determines the generation of the pulse. This requires a
carrier of much higher frequency than the modulation frequency. The
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generated rectilinear output voltage pulses are modulated such that their
duration is proportional to the instantaneous value of the sinusoidal waveform
at the centre of the pulse; that is, the pulse area is proportional to the
corresponding value of the modulating sine wave.
Figure 4.1 VSF SH-PDPWM
In phase disposition, all the carrier waveforms are inphase with
variable frequency. Figure 4.1 demonstrates the VSF SH-PDPWM method for
a five level inverter. Therein, the phase modulation signal is compared with
four (n-1 in general) triangle waveforms. In carrier-based implementation, at
every instant of time the modulation signals are compared with the carrier and
depending on which is greater, the switching pulses are generated.
The VSF SH-PDPWM generator is shown in Figure 4.2. The three
phase sinusoidal modulating signals are generated by using sine wave
generator. This signal is compared with (n-1) carrier waves with variable
frequency and PWM pulses are generated. These PWM pulses are applied to
three phase five level inverter.
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.2 S
imul
ink
diag
ram
ofV
SF S
H -
PDPW
M g
ener
atio
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80
Figure 4.3 VSF SH – PDPWM Signal generation
The variable switching frequency SH-PDPWM signal generation is
shown in Figure 4.3.
• It is noted that when the sinusoidal reference signal is greater
than all carrier waves, +Vdc is obtained.
• When the sinusoidal reference signal is greater than carrier
wave except upper most carrier wave, +Vdc/2 is obtained.
• When the sinusoidal reference signal is greater than lower
most carrier and less than all carrier, –Vdc/2 is obtained.
• When the sinusoidal reference signal is lesser than all carrier
waves, –Vdc is obtained.
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4.2.1.1 Results
To verify the VSF SH-PD PWM, simulation model, a three phase
five level cascaded H-Bridge inverter is implemented using
MATLAB/SIMULINK. The simulation and hardware parameters for VSF
SH-PD PWM are as follows:
• Three-phase load R = 100 Ohms & L = 20 mH
• Voltage level of each source Vdc = 100V
• Fundamental frequency = 50Hz
• Switching frequency = 2 kHz & 4 kHz
The simulation and hardware output voltage for VSF SH-PDPWM
is shown in Figures 4.4 and 4.5.
Figure 4.4 Simulation output voltage for VSF SH - PDPWM
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Figure 4.5 Hardware output voltage for VSF SH - PDPWM
Figure 4.6 VSF SH – PDPWM frequency spectrum
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Figure 4.7 VSF SH – PDPWM harmonic spectrum
The VSF SH-PDPWM frequency spectrum is shown in Figure 4.6.
In frequency spectrum the switching frequency is 2 KHz with fundamental
frequency 50 Hz. The output voltage obtained by VSF SH-PDPWM is about
180.1V for input voltage of 100V from each source. As switching frequency
is 2 KHz and fundamental frequency is 50Hz so harmonic order is about 40
which is shown in Figure 4.7. The THD value is about 10.10%.
4.2.2 Switching Frequency Optimal PWM
The SFOPWM, a carrier based method where addition of triplen
harmonic to the fundamental frequency sinusoidal reference, thus allowing
operating in over modulation region. This increases the inverter output
voltage without compromising on the quality of the output waveform.
Figure.4.8 shows the sinusoidal pulse width modulation with zero sequence in
which a third harmonic voltage is added to each of the reference waveforms.
.
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Figure 4.8 VSF SFO – PDPWM
The VSF SH-PDPWM generator is shown in Figure 4.9. The three phase third harmonic modulating signals are generated. This signal is compared with (n-1) carrier waves with variable frequency and PWM pulses are generated. These PWM pulses are applied to three phase five level inverter.
The VSF SFO-PDPWM signal generation is shown in Figure 4.10.
• It is noted that when the third harmonic reference signal is greater than all carrier waves, +Vdc is obtained.
• When the third harmonic reference signal is greater than carrier wave except upper most carrier wave, +Vdc/2 is obtained.
• When the third harmonic reference signal is greater than lower most carrier and less than all carrier, –Vdc/2 is obtained.
• When the third harmonic reference signal is lesser than all carrier waves, –Vdc is obtained.
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Figu
re 4
.9 S
imul
ink
diag
ram
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SF S
FO –
PDPW
M g
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atio
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86
Figure 4.10 VSF SFO – PDPWM signal generation
4.2.2.1 Results
The simulation and hardware output voltage for VSF SFO-PDPWM is
shown in Figures 4.11 and 4.12.
Figure 4.11 Simulation output voltage for VSF SH – PDPWM
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Figure 4.12 Hardware output voltage for VSF SH – PDPWM
Figure 4.13 VSF SH – PDPWM harmonic spectrum
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Figure 4.14 VSF SH – PDPWM frequency spectrum
The VSF SFO-PDPWM frequency spectrum is shown in Figure
4.14. In frequency spectrum the switching frequency is 2 KHz with
fundamental frequency 50 Hz. The output voltage obtained by VSF SFO-
PDPWM is about 200V for input voltage of 100V from each source. As
switching frequency is 2 KHz and fundamental frequency is 50Hz so
harmonic order is about 40 which is shown in Figure 4.13. The THD value is
about 22.45%.
The result confines that the output voltage in SH-PWM is 180.1V
and for SFO-PWM it is about 200V. It is reveals, the THD for SH-PWM is
10.10% and for SFO-PWM it is 22.45%. From the above investigation, it
reveals that SH-PWM reduces THD and SFO-PWM enhances the output
voltage.
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4.3 PHASE OPPOSITION DISPOSITION PULSE WIDTH
MODULATION
For phase opposition disposition modulation, all carrier waveforms
above zero reference are in phase with low frequency and are 180º out of
phase with those below zero with high frequency. The phase modulation
signal is compared with four (n-1 in general) triangle waveforms.
The operating rules for VSF POD method when the number of level
n = 5 are given below:
• The n – 1 = 4 carrier waveforms are arranged with variable
frequency. All carrier waveforms above zero reference are in
phase with low frequency and are 180º out of phase with those
below zero with high frequency.
• The converter switches to + Vdc when the reference is greater
than all the carrier waveforms.
• The converter switches to Vdc / 2 when the reference is less than
the uppermost carrier waveform and greater than all other
carriers.
• The converter switches to 0 when the reference is less than the
two uppermost carrier waveform and greater than two
lowermost carriers.
• The converter switches to - Vdc / 2 when the reference is greater
than the lowermost carrier waveform and lesser than all other
carriers.
• The converter switches to -Vdc when the reference is lesser than
all the carrier waveforms.
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4.3.1 Subharmonic PWM
Figure 4.15 demonstrates the VSF SH-PODPWM method for a five
level inverter. Therein, the phase modulation signal is compared with four (n-
1 in general) triangle waveforms. In carrier-based implementation, at every
instant of time the modulation signals are compared with the carrier and
depending on which is greater, the switching pulses are generated. For POD
all carrier waveforms above zero reference are in phase and are 180º out of
phase with those below zero.
Figure 4.15 VSF SH – PODPWM
The variable switching frequency SH-PODPWM generator is
shown in Figure 4.16. The three phase sinusoidal modulating signals are
generated by using phase shift oscillator. This signal is compared with (n-1)
carrier waves and PWM pulses are generated. These PWM pulses are applied
to three phase five level inverter.
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Figu
re4.
16 S
imul
ink
diag
ram
of V
SF S
H -
POD
PWM
gen
erat
ion
92
Figure 4.17 VSF SH - PODPWM signal generation
The VSF SH-PODPWM signal generation is shown in Figure 4.17.
• It is noted that when the sinusoidal reference signal is greater
than all carrier waves, +Vdc is obtained.
• When the sinusoidal reference signal is greater than carrier
wave except upper most carrier wave, +Vdc/2 is obtained.
• When the sinusoidal reference signal is greater than lower most
carrier and less than all carrier, –Vdc/2 is obtained.
• When the sinusoidal reference signal is lesser than all carrier
waves, –Vdc is obtained.
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4.3.1.1 Results
The simulation and hardware output voltage for VSF
SH-PODPWM is shown in Figures 4.18 and 4.19.
Figure 4.18 Simulation output voltage for VSF SH – PODPWM
Figure 4.19 Hardware output voltage for VSF SH - PODPWM
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Figure 4.20 VSF SH – PODPWM frequency spectrum
Figure 4.21 VSF SH – PODPWM harmonic spectrum
The VSF SH-PODPWM frequency spectrum is shown in Figure
4.20. In frequency spectrum the switching frequency is 2 KHz with
fundamental frequency 50 Hz. The output voltage obtained by
VSF SH-PODPWM is about 199.9V for input voltage of 100V from each
source. As switching frequency is 2 KHz and fundamental frequency is 50Hz
so harmonic order is about 40 which is shown in Figure 4.21. The THD value
is about 11.39%.
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4.3.2 Switching frequency optimal PWM
Figure 4.22 demonstrates the variable switching frequency
SFO-PODPWM method for a five level inverter. Therein, the third harmonic
reference signal is compared with four (n-1 in general) triangle waveforms. In
carrier-based implementation, at every instant of time the modulation signals
are compared with the carrier and depending on which is greater, the
switching pulses are generated. For POD all carrier waveforms above zero
reference are in phase and are 180º out of phase with those below zero.
Figure 4.22 VSF SFO - PODPWM
The VSF SFO-PODPWM generator is shown in Figure 4.23. The
three phase third harmonic modulating signals are generated by using
switching frequency optimal generator. This signal is compared with (n-1)
carrier waves and PWM pulses are generated. These PWM pulses are applied
to three phase five level inverter.
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97
Figure 4.24 VSF SFO – PODPWM signal generation
The VSF SFO-PODPWM signal generation is shown in Figure 4.24.
• It is noted that when the third harmonic reference signal is
greater than all carrier waves, +Vdc is obtained.
• When the third harmonic reference signal is greater than carrier
wave except upper most carrier wave, +Vdc/2 is obtained.
• When the third harmonic reference signal is greater than lower
most carrier and less than all carrier, –Vdc/2 is obtained.
• When the third harmonic reference signal is lesser than all
carrier waves, –Vdc is obtained.
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4.3.2.1 Results
The simulation and hardware output voltage for VSF SFO-PODPWM
is shown in Figures 4.25 and 4.26.
Figure 4.25 Simulation output voltage for VSF SFO - PODPWM
Figure 4.26 Hardware output voltage for VSF SFO - PODPWM
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Figure 4.27 VSF SFO – PODPWM frequency spectrum
Figure 4.28 VSF SFO – PODPWM harmonic spectrum
The VSF SFO-PODPWM frequency spectrum is shown in Figure
4.27. In frequency spectrum the switching frequency is 2 KHz with
fundamental frequency 50 Hz. The output voltage obtained by
VSF SFO-PODPWM is about 220.1V for input voltage of 100V from each
source. As switching frequency is 2 KHz and fundamental frequency is 50Hz
so harmonic order is about 40 which is shown in Figure 4.28. The THD value
is about 23.68%.
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The result confines that the output voltage in SH-PWM is 199.9V
and for SFO-PWM it is about 220.2V. It reveals, the THD for SH-PWM is
14.60% and for SFO-PWM it is 24.67%. From the above investigation, it
reveals that SH-PWM reduces THD and SFO-PWM enhances the output
voltage.
4.4 COMPARISON OF CONSTANT AND VARIABLE
SWITCHING FREQUENCY BASED PWM TECHNIQUES
The results of constant and variable switching frequency based
pulse width modulation techniques using SH and SFO methods are analyzed
and THD as well as output voltage values are compared as shown in
Table 4.1, Figures 4.29 and 4.30.
The THD value and output voltage values are small in SH PWM
technique whereas the values are high in SFO PWM technique. It is observed
finally that with minimised THD, SH PWM method gives better results and
the SFO PWM technique is the most suitable in achieving the increased
output voltage.
Table 4.1 Output voltage and THD for CSF and VSF PWM techniques
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Figure 4.29 % of THD value for CSF and VSF PWM techniques
comparison
Figure 4.30 Output voltage for CSF And VSF PWM techniques
comparison
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It is observed that the CSF SH-PWM in PDPWM gives better result
compared to the other methods interms of THD. The CSF SH-PDPWM, the
THD value is 6.70% whereas in other PWM techniques are above the 10% of
THD value. The VSF SFO-PWM in PODPWM gives better result compared
to the other methods interms of output voltage. The VSF SFO-PODPWM, the
output voltage is 220.1 and THD value is 23.68% whereas in CSF SFO-
PODPWM and SFO-APODPWM techniques are maintained 220.2V but THD
values are above 24% of THD value. Here, the SH-PWM strategy reduces the
THD and SFO-PWM strategy enhances the output voltage.
4.5 SUMMARY
The two proposed techniques namely PD, POD and APOD are
simulated and performances analyzed by implementing FPGA SPARTAN-3
processor, the results are obtained from experimental work which is almost
similar to the simulation work. Here, the SH-PWM strategy reduces the THD
and SFO-PWM strategy enhances the output voltage.