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CHAPTER 1
INTRODUCTION
1.1 GENERAL
Power electronic inverters are widely used in industrial power
conversion systems both for utility and drives applications (Tolbert and Peng
1998, 1999, 2002). As the power level increases, the voltage level also
increases accordingly to obtain satisfactory efficiency. Multilevel Inverters
have been attracting attention in recent years due to high power quality, high
voltage capability, low switching losses and low Electro Magnetic
Interference (EMI) concerns; and have been proposed as the best choice in
several medium and high voltage applications such as static VAR
compensators and large electrical drives (Min 1999 and Peng 1996, 1997,
2001). Conventional inverter can switch to each input / output connection
between two possible voltage (and possible current) levels. Multilevel inverter
can switch their outputs between many voltage or current levels and have
multiple voltage or current sources (or simply capacitors or inductors) as part
of their structure.
A multilevel inverter can be implemented in different topology with
its own advantages and limitations. The simplest technique adopted is parallel
or series connection of conventional inverters to form the multilevel inverter.
More complex structures involve, inserting inverter within inverter to form a
multilevel inverter. Whatever approach is chosen, the subsequent voltage or
current rating of the multilevel inverter becomes a multiple of the individual
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switches and so that the power rating of the inverter can exceed the limit
imposed by the individual switching devices. Pulse Width Modulation
(PWM) of multilevel inverter is typically an extension of two level inverters.
The most common types of multilevel voltage source pulse width modulation
are sine triangle modulation and space vector modulation (Bowes1975
Bhagwat and Stefanovic 1983). Multilevel sine triangle modulation relies on
defining a number of triangle waveforms and switching rules for the
intersection of these waveforms with a commanded voltage waveform. This
method is fairly straightforward and insightful for the description of
multilevel systems.
The main function of a multilevel inverter is to produce a desired
AC voltage level from several DC voltage sources. This DC voltage source
may or may not be equal to one another. The AC voltage produced from this
DC voltage appears to be a sinusoidal. One pitfall of using multilevel inverter
is to approximate sinusoidal waveforms concern with harmonics. The
staircase waveform produced by a multilevel inverter contains sharp
transitions. The harmonics which are generated, in addition to the
fundamental frequency of the sinusoidal waveform are analyzed using the
Fourier Series Theory. The harmonics generated on the AC side greatly
influence the power quality of the control system. The multilevel inverter
improves the AC power quality by performing the power conversion in small
voltage steps leading to lower harmonics. For this reason, researchers are
doing considerable work on multilevel inverter in recent years.
1.2 OBJECTIVES OF RESEARCH
To compare the performance of a flying capacitor, the cascaded H
bridge, hybrid H-bridge and new hybrid H-bridge multilevel inverters. The
comparisons are done with respect to number of switches, Total Harmonics
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Distortion (THD) of voltage and motor performances like speed, torque and
stator currents. To confirm the performance comparison of all these multi
level inverters, the results are justified through simulation and hardware
investigation.
1.3 LITERATURE REVIEW
The history of multilevel inverter began in mid 1970s, when the
first patent describing an inverter topology capable of producing multilevel
voltage from various DC voltage sources was published by Baker and
Bannister (1975). Significant works were undertaken from mid 1990s and
various classifications of multilevel inverters have been made with different
topologies. More than 120 research papers and the experience of researchers
have been referred to carry out this research work. The topology wise
distribution of research papers referred is given in Figure 1.1. The contents of
literature have been discussed briefly in the following sections. They are
under five major categories namely, diode clamped, flying capacitor,
cascaded H-bridge, hybrid H-bridge and new hybrid H-bridge multilevel
inverters.
Figure 1.1 Distribution of Literature Survey
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1.3.1 Single Source Multilevel Inverter
Single source multilevel inverter has only one DC source and
remaining are the capacitors or clamping diodes to produce multilevel output
voltage. A multilevel inverter topology was initially introduced with two
topologies, and demonstrated using three level and five level inverters by
Baker and Bannister (1975). A five level inverter with series connected
clamping diodes was proposed by Baker (1980) which differs from the
topology originally demonstrated earlier.
During later 1990s, flying capacitor inverter was introduced and
several patents were published including Meynard and Foch (1992a,b),
Hammond (1997). The topology of the flying capacitor inverter was used for
three level and five level applications. Hammond (1997), on the other hand,
experimented a practical method to implement the cascaded five level
H-bridge Inverters.
1.3.1.1 Diode clamped multilevel inverter
The Diode Clamped Multilevel Inverter (DCMLI) is also known
as neutral point clamped inverter. It consists of two capacitor voltages in
series and uses the center tap as the neutral. Each phase leg of the three level
inverter has two pairs of switching devices in series. The center of each
device pair is clamped to the neutral through clamping diodes(Ali
Khajehoddin et al 2008). The waveform obtained from the three level inverter
is a quasi square wave output. An m level DCMLI consists of (m-1)
capacitors on the DC bus, 2(m-1) switching devices per phase and 2(m-2)
clamping diodes per phase. Diodes are used to clamp the each voltage levels
in the output voltage so called diode clamped multilevel inverter
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Xiaoming Yuan et al (2000) proposed a new diode clamping
inverter. In this inverter, the series associations of the clamping diodes are
neglected. The problem of indirect clamping of the inverter devices solved
with auxiliary resistive clamping network for both the new and conventional
diode clamping inverter.
Yuan and Barbi (2002) introduced a neutral point clamped inverter
which has the characteristics of sharing DC input voltage to several diodes.
Unlike single inverter which is in series connection, this inverter has the
ability to generate multilevel voltage from single DC source with additional
diodes connected to neutral point.
Zhong (2006) developed a linear model of an actively balanced
split DC link to provide high bandwidth robust control with pulse width
modulation control design. This model is designed for a conventional two
level inverter, through it is applicable for three levels neutral point clamped
inverter also. Instead of large neutral current, the controller achieves very
small deviations of the neutral point from the midpoint of DC source.
Aabdul Rahiman Beig et al (2007) proposed a technique to improve
the output of the three level inverter in high power applications, with very low
switching frequency. The above fact was obtained by maintaining the
synchronization, half wave symmetry, quarter wave symmetry and three
phase symmetry in the PWM waveform. The way to achieve the
synchronization and symmetries in terms of space vectors are also discussed.
Jose Rodriguez et al (2007) presented a review of VSI topologies
for industrial medium voltage drives. This review covers the operation of
difficult inverters like high power VSI and the commonly used MLI
topologies including neutral point clamped, cascade H-bridge and flying
capacitor inverter.
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Ali Khajehoddin et al (2008) proposed a simple voltage balancing
scheme for m level diode clamped multilevel inverter. The important feature
of the proposed scheme is its independent from the modulation scheme and
simplicity. Another feature is the voltage sharing accessibility among the DC
link capacitors. The voltages of capacitors of the diode clamped multilevel
inverters are balanced using space vector modulation switching strategy in a
very simple and optimized manner. The voltage balancing scheme for five
level inverter or greater was not developed due to its complexity and its
modeling approaches.
Renge et al (2008) proposed a design for high power induction
machines at medium voltage rating for better performances. The multilevel
inverter reduces the switching losses and leakage current due to its ability to
provide medium voltage with quality output at low switching frequency as
compared to conventional two level inverters. The usage of five level diode
clamped multilevel inverter helps to eliminate the common mode voltage. A
new technique for the selection of switching states for synthesizing a desire
vector was proposed.
Huibin Zhang et al (2008) analyzed the method for balancing
voltages of DC link voltage source possibilities and an algorithm was
proposed to independently balance the capacitor voltages. The two issues are
considered under the proposed algorithm. The first one is average energy
effect of each vector on capacitor voltage and another one is necessary
optimal vector state sequence in each modulation cycle. The advantages of
this algorithm are minimizing the voltage rating of the hardware by which the
voltage ripple gets reduced and the negative effects associated with DC link
voltage oscillations are attenuated.
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Samir Kouro et al (2008) proposed power inverter topologies in
which the modulation techniques are used to control the multilevel inverters
which are conceptually based on the synthesis of non linear waveforms
assuming constant DC link voltages. However in real applications, the supply
dependent DC links has low frequency, ripple, generates undesirable low
frequency voltage and current distortion while modulated and transmitted to
the load. A simple and effective DC link ripple feed forward strategy was
introduced in traditional carriers based modulation techniques. The carriers
are modified directly in the modulation stage by measuring the DC link
ripples.
Wenxi Yao et al (2008) reviewed the relations of space vector
modulation and carrier based PWM for multilevel inverters. The carrier based
PWM scheme is used to achieve the generation of Space Vector Modulation
(SVM), but the modulated wave of SVM is acquired by vectors for
calculation and selection of switching states. There are many types of SVM
modulated waves based on different selection of redundant switching states,
the various types function equivalently through proper selection of common
mode injections in the case of carrier based PWM, the others have more
freedom in switching states selection than carrier based PWM.
Natchpong Hatti et al (2009) presented a 6.6 KV adjustable speed
motor drive for pumps and blowers without transformer. The power
conversion system consists of front end diode rectifier, five level diode
clamped pulse width modulated inverter with a voltage balancing circuit and
hybrid filter for the minimizing of harmonic current in diode rectifiers. The
control of the inverter was characterized by superimposing a third harmonic
zero sequence voltage on each of the three phase reference voltages to achieve
the over modulation and reduce the switching stress of insulated gate bipolar
transistors.
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Mailah (2009) proposed a multilevel inverter which offers several
advantages when compared to the conventional three phase bridge inverter in
terms of dv/dt stress, lower electromagnetic compatibility, smaller rating and
better output features. A space vector modulation technique is used as the
control strategy for the three level neutral point clamped inverter. Comparison
of several types of multilevel inverters with various control strategies has
been made.
1.3.1.2 Flying capacitor multilevel inverter
The Flying Capacitor Multilevel Inverter (FCMLI) requires a large
number of capacitors to clamp the device voltage to one capacitor voltage
level. All the capacitors are provided with equal value, this m level inverter
needs a total of ( 1) × (m 2) /2 clamping capacitors per phase leg in
addition to (m-1) main DC bus capacitors.
Gangui Yan et al (2002) achieved a significant reduction in the
volume of capacitors as well as scalable in terms of voltage levels and control
flexibility. Stacked flying capacitor inverter had gained great industrial
attention recently. The PWM method is applied to control the balance of
flying capacitor voltages in stacked FCMLI, which can be readily
implemented on a digital signal processor and also to guarantee the switching
frequency of each switching device.
Corzine et al (2003) described a flying capacitor MLI with full
binary combination scheme. The number of voltage levels can be increased
for a given number of semiconductor devices when compared to conventional
method which is the main feature of this approach. However, the new scheme
requires fixed floating sources to provide the DC voltages due to its difficulty
of balancing the capacitors.
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Kang et al (2003) proposed a new solution for the voltage
unbalancing problem of flying capacitor multilevel inverter named as carrier
rotation PWM technique. The proposed PWM technique equalizes the
utilization of phase leg voltage redundancies corresponding to charging and
discharging state of individual flying capacitor during each switching period
of all the switches. The average variation of flying capacitor voltages become
zero and keeps their voltage stable during minimum specified period due to
equal charging and discharging voltage of flying capacitor.
Hongyan Wang et al (2004) established a relationship between
carrier shifted PWM and space vector PWM in flying capacitor multilevel
inverter. According to this relationship a minimized switching loss is
achieved in the flying capacitor multilevel inverter. Each phase of the flying
capacitor multilevel inverter can have 120° no switching zone in one period of
the proposed method, when compared to the conventional carrier shifted
PWM method.
Xiaomin Kou et al (2004) designed flying capacitor type multilevel
inverter with fault tolerant features. A new design with single switch fault per
phase was proposed. This method provides the same number of converting
levels by shorting the fault power semiconductors and reconfiguring the gate
controls. The most attractive point of the proposed design was that it can
undertake the single switch fault per phase without sacrificing the quality of
power due to power conversion .
Anshuman Shukla et al (2005) implemented a flying capacitor
multilevel inverter with a multiple voltage level inverter topology intended for
high power and high voltage operations with low distortion. The voltage
across the power semiconductor devices are clamped using capacitors called
flying capacitors. A method for controlling the FCMLI was proposed which
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ensures that the flying capacitor voltages remain nearly constant using the
preferential charging and discharging of these capacitors.
Alian Chen et al (2005) proposed new topology with reduced
number of clamping diodes and flying capacitors when compared to
conventional methods. The topology structure, operating principle and
balance of DC link capacitor voltages with the reduction of clamping diodes
and flying capacitor are discussed in this research. An attempt was also made
for performance comparison of different conventional multilevel topologies.
Bum Seung Jin et al (2005) presented a method for the difference in
charging and discharging time of each capacitor leads to the problem of
voltage unbalancing in FCMLI. The voltage unbalancing of flying capacitor
causes serious problems in safety and reliability of system and also limits
FCMLI’s applications. The proposed method eliminates the problems of
voltage unbalancing.
The research of Jing Huang and Corzine (2006) on flying capacitor
multilevel inverter, reduces the change in the ratio of the capacitor voltages
which leads to the extension in the number of voltage levels. In a three cell
FCMLI, four level of operation will be expected with traditional capacitor
voltage ratio of 1:2:3. However, by altering the ratio, the inverter can operate
as five, six, seven or eight level inverters.
Zhang et al (2006) presented a work based on rule based scheme
for capacitor voltage balancing in a multilevel flying capacitor inverter. The
proposed scheme determines the best switching pattern for maintaining zero
mean current in all capacitors without voltage feedback, by which the
capacitor voltage fluctuations are minimized. The proposed method controls
the static VAR compensators using selective harmonic elimination technique
for sinusoidal voltage generation.
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Zhang et al (2006) reported a switching pattern selection scheme to
control the voltage of a flying capacitor multilevel inverter. The superiority of
this scheme is to reduce capacitor voltage fluctuation without using voltage
feedback. The proposed method is for the generation of sinusoidal voltage
using the selective harmonic elimination technique and the results were
compared with the system of voltage feedback.
Anshuman Shukla et al (2007) described the development of
capacitor voltage balancing methods for flying capacitor multilevel inverters.
In this research two schemes were proposed with sinusoidal pulse width
modulation technique. The first scheme works on the principle of selection of
the most favorable switching state depending on the preferential charging and
discharging of capacitors. It uses a two level comparator for each capacitor
state detection. In the second scheme, capacitor voltages are controlled in a
three level comparator to achieve better performance.
Chunmei Feng et al (2007) proposed a technique to solve the
voltage imbalance problem which is a challenge for the flying capacitor
multilevel inverter. The phase shifted pulse width modulation method had a
certain degree of self balancing properties. However, this method alone is not
enough to maintain balanced capacitor voltages in practical applications.
Gupta and Khambadkone (2007) investigated the different control
techniques used in the multilevel cascaded inverter in order to determine an
efficient voltage utilization and better harmonic distortion technique. Among
them, phase shift PWM technique uses a number of carrier waves equal to the
number of full bridge inverters, employed in cascaded inverter structure.
Wang (2007) proposed a three level PWM voltage source inverter
with inverters of the choice for many high power applications such as medium
voltage motor drives and the three phase neutral point clamped voltage source
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inverter. Compared with two level and three level inverter has half voltage
stress on switching devices for the same DC link voltage and generate lower
order harmonics at the same switching frequency.
Anshuman Shukla (2008) described a method for development of
multilevel hysteresis current regulation strategies. In general, a multiband
concept had been used while developing these strategies. The hysteresis band
size considerations have been presented by taking into account the desired
and existing system conditions. The algorithm takes advantage of switching
redundancies to adjust the switching times of selected switching states and
thus maintaining the capacitor voltages balanced without adversely affecting
the system’s performance.
1.3.2 Multi Source Multilevel Inverter
Multisource multilevel inverter can increase the level with same
number of DC sources with different values. The topologies are cascaded,
hybrid and new hybrid H-bridge multilevel inverter. The topology was
achieved by connecting the H-bridge inverter in series with other H-bridge
inverter. The topology is a series connected H-bridge inverter which is also
known as a cascaded H-bridge inverter. It was developed by Baker and
Bannister in 1975.
The interest in the multilevel inverter except three level inverter
faded during the 1980s, but in the 1990s this technology began to draw more
attention again. For example Marchesoni et al (1990) proposed a cascaded
multilevel inverter which could be used in nuclear fusion experiments.
Moreover, Marchesoni and his research group made a significant contribution
to the multilevel inverter research, especially in control and modulation, in the
early 1990s; (Marchesoni 1998, Marchesoni and Tenca 2002, Marchesoni
et al 1990, Carrara et al 1990, Fracchia et al 1992).
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During 1990 to 2000s, several other variations of multilevel
inverter topologies have been proposed. Several alternative ways to
implement a cascaded inverter were introduced by Stemmler and Guggenbach
(1993), Kawabata et al (1996), Corzine et al (1999), Barcenas et al (2002),
Soto et al (2003). One of the proposed cascaded inverter topologies includes a
machine with open end windings and a two level inverter, which is connected
to one end of the windings and the H-bridge to the other side (Kang et al
2000). Another interesting topology that has attracted increasing attention is
the modular multilevel inverter (Lesnicar and Marquardt (2003), Glinka and
Marquardt (2003, 2005), Hagiwara and Akagi (2008), Rohner et al (2009),
Antonopoulos et al (2009)).
The three topologies, the Series Connected H-bridge Inverter
(SCHBI), the DCMLI and the flying capacitor, had aroused the wide interest.
The SCHBI has an advantage over the DCMLI and flying capacitor
topologies owing to its modularity, as can be noted by comparing these
topologies. The number of voltage levels can be increased without
complicating the circuitry, because the number of levels increased by adding
H-bridge modules in series (Sirisukprasert et al 2001). In this section, the
topology of the cascaded H-bridge inverter was chosen for further
investigation.
1.3.2.1 Cascaded H-bridge multilevel inverter
The serially connected H-bridge with separate DC source is called
as cascaded H-bridge multilevel inverter. In this type of configuration voltage
on each DC source is same value.
Li Li (2000) proposed a multilevel selective harmonic elimination
PWM technique in series connected voltage inverters. Selective harmonic
elimination pulse width modulation method was systematically applied for the
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first time to multilevel series connected voltage source PWM inverters. The
method was implemented based on optimization techniques. The optimization
starting point is obtained using a phase shift harmonic suppression approach.
Corzine Keith et al (2004) introduced a new type of multilevel
inverter which was created by cascading two, three phase three level inverter
using the load connection, but requires only one DC voltage source. This new
seven level inverter splits the power conversion into a higher voltage lower
frequency inverter and a lower voltage higher frequency inverter. This type of
inverters found applications in naval ship propulsion systems which rely on
high power quality, survivable drives. New control methods are described
involving both joint and separate control of the individual three level inverter.
Two types of controlling methods were developed for this inverter. One relies
on controlling the two, three level inverter jointly and the other uses separate
controls. Both the controls include capacitor voltage balancing so that a DC
source was needed for one three level inverter.
Mariethoz et al (2005) developed a cascaded multilevel inverter
which focuses on asymmetrical topologies where the cell input voltages are
different values. These hybrid topologies are advantageous for several
applications. In this inverter the need of DC-DC converter to supply the cells
creates simultaneous commutation problem, which increases the switching
losses for some operating points, reduces the design choice to configurations
of lower resolution. A three phase six switch voltage source inverter and
single phase H-bridge are connected in series to obtain a cascaded multilevel
inverter with attractive properties in terms of inverters cost and losses.
Sahali et al (2006) presented a comparative study between optimal
minimization of total harmonic distortion and harmonic elimination with
voltage control strategies for multilevel inverter. This was devoted to the
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comparative evaluation of the two modulation strategies developed for
multilevel inverter control, the harmonic elimination technique with voltage
control and the optimal minimization of the total harmonic distortion method,
which are very important and efficient strategies of eliminating selected
harmonics from spectrum of the output voltage or minimizing its total
harmonic distortion in order to improve its quality.
Ebrahim Babaei (2008) proposed a cascaded multilevel inverter
topology with reduced number of switches. This new multilevel inverter
topology had many steps with fewer power electronic switches. The proposed
circuit consists of series connected sub multilevel inverter blocks. The
proposed topology results in reduction of the number of switches, losses,
installation area and inverter cost.
Agelidis et al (2008a,b) reported a five level symmetrically defined
multilevel Selective Harmonic Elimination Pulse Width Modulation
(SHEPWM) strategy. This technique has equal number of switching
transitions when compared against the well known multicarrier phase shifted
sinusoidal PWM technique. It was assumed that the four triangular carriers of
the sinusoidal pulse width modulation method have nine levels per unit
frequency resulting in seventeen switching transitions for every quarter
period. The proposed multilevel SHEPWM method controls sixteen
harmonics and the fundamental. It is noted that the proposed Multilevel
SHEPWM offers significantly higher inverter bandwidth in the standard range
of the modulation index.
Chih Chiang Hua et al (2009) proposed a current control technique
with predictive control method for multilevel inverter. In this method,the
inductor current is sensed by the current control method of variable sampling
point. It is reported the switching noise caused by the turn on or turn off
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power devices are avoided by this control method. The measured value of the
inductor current was used to estimate the inverter output voltage at the next
switching period with a simple linear extrapolation by forcing the output
current to follow the current reference. Compared to the conventional
predictive current controllers, the features of the proposed control are as
follows: only the inductor current measurement was required and it was able
to achieve a cost effective and less complex circuit, whereas the output
voltage and current measurements are required for a conventional controller.
Sung Geun Song et al (2009) proposed an isolated cascaded
multilevel inverter employing low frequency three phase transformers and a
single DC input power source. In this topology, four H-bridge modules are
connected to the same DC input source in parallel and each secondary of the
four transformers are connected in series. The proposed circuit configuration
can reduce number of transformers compared with traditional three phase
multilevel inverter using single phase transformers. An optimal switching
pattern identified with the fundamental frequency of the output voltage and
controls the switching phase angle. By the proposed circuit configuration, a
number of transformers can be reduced, compared with traditional three phase
multilevel inverter using single phase transformers.
Zhong Du et al (2009) presented a new multilevel inverter which
was developed without the inductors called cascaded H-bridge multilevel
boost inverter. This research developed for the applications of Electric
Vehicle and Hybrid Electric Vehicles (HEV). At present, the HEV power
inverter system uses a DC-DC boost converter to boost the battery voltage for
a traditional three phase inverter. The disadvantages of the present HEV
traction drive inverters are low power density, expensive and low efficiency.
These problems occur due to the necessity of bulky inductor in the system.
Because all H-bridge needs a DC power supply, the proposed design uses a
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standard three leg inverter and an H-bridge. The H-bridge is in series with
each inverter leg which uses a capacitor as the DC power source.
Gierri Waltrich et al (2010) designed a modular three phase
multilevel inverter specially suited for electrical drive applications. This
topology works based on the power cells connected in cascade using two
inverter legs in series. To achieve a medium voltage operation and low
harmonic distortion, the H-bridge cells are usually connected in cascade on
their AC side. To make this inverter as cost effective, power cells are used
with identical a characteristic which leads to modular structure of the system.
Joachim Holtz et al (2010) demonstrated the different inverter
topologies which are suited for very high power applications. The higher
machine voltages are obtained from these topologies than the three levels
DCMLI topology. The power capabilities of pulse width modulated inverters
are increased for the development of medium voltage drives. Parallel
connection and series connection of power semiconductor devices permits to
increase the output current and output voltage respectively. In both the cases,
additional means are required for balancing the current or voltage stress of the
devices. The technical and economic constraint involved with multilevel
inverter topologies improves the performance of voltage drives. The parallel
connection of two three level inverter doubles the maximum output power by
doubling the maximum output current.
Patricio Cortes et al (2010) presented a model predictive current
control algorithm that was suitable for multilevel inverter. Its application to a
three phase cascaded H-bridge inverter for optimization was proposed in
order to this algorithm reduces the amount of calculations needed for the
selection of the optimal voltage vectors, by choosing a subset of the available
voltage vectors by which the operation of three phase cascaded H-bridge
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inverter is optimized. Although the proposed control method was valid for
any number of levels, by using this method, five level and nine level cascaded
H-bridge multilevel inverters were presented in this paper. The proposed
control method can be easily extended to include any additional requirements.
Young Min Parky et al (2010) designed a cascaded H-bridge
multilevel inverter using power electronics building blocks and high
performance control to improve current control and increase fault tolerance
capability. Since the individual inverter modules operate more independently,
the expansion and modularization characteristics of the cascaded H-bridge
multilevel inverters are improved. It was also shown that the performance of
current control can be improved with voltage delay compensation and the
fault tolerance performance can be increased by using unbalance three phase
control.
1.3.2.2 Hybrid H-bridge multilevel inverter
A serially connected H-bridge with separate DC sources are called
as hybrid H-bridge multilevel inverter. Each succeeding voltage source has
the voltage values in the order of 1Vdc, 2Vdc and 4Vdc.
Manjrekar and Lipo (1998) reported various topologies and
modulation strategies for utility and drive applications. This paper was
devoted to the investigation of a 500 HP induction machine drive based on a
seven level 4.5 KV hybrid inverter. Various design criteria, spectral structure
and other practical issues such as capacitor voltage balancing are discussed.
Manjrekar et al (2000) devoted to the investigation of a hybrid
multilevel power conversion system for medium voltage high power
applications. By trends in power semiconductor technology, the authors
selected different power devices based on their switching frequency and
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voltage sustaining capability and created a new hybrid topology. The new
power inverter topologies permit modular realization of multilevel inverter
using a hybrid approach involving Integrated Gate Commutated Thyristors
(IGCT) and Insulated Gate Bipolar Transistors (IGBT) operating together.
With this modular H-bridge topology, realization of multilevel inverter using
a hybrid approach involving IGCTs and IGBTs is possible, which are useful
in required high power applications.
Lai et al (2002) proposed a new topology for a hybrid multilevel
inverter, which significantly increases the number of levels of the output
waveform and thereby dramatically reduces the low order harmonics and total
harmonic distortion. The presented topology has the greatest level number for
a given number of stages. Moreover, the stage with higher DC link voltage
has lower switching frequency and thereby, reduces the switching losses.
Miguel Lopez et al (2003) proposed an active power filter
implemented with multiples single phase full bridge voltage source inverters
connected in series. It was aimed to compensate current harmonic
components in medium and high voltage power distribution systems.
Cassiano Rech et al (2007) proposed the concept of hybrid
multilevel inverter that had been generalized for different arrangements of
direct current voltage levels, modulation strategies, topologies of series
connected cells or semiconductor technologies to optimize the power
processing of the overall system. Therefore, a given number of level can be
synthesized by several multilevel configurations, significantly increasing
flexibility and complexity in the design of hybrid multilevel inverter.
Haiwen Liu et al (2008) presented a hybrid cascaded multilevel
inverter with PWM method. It consists of a standard three leg inverter and H
bridge in series with each inverter leg. It can use only a single DC power
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source to supply a standard three leg inverter along with three full H-bridge
supplied by capacitors. Multilevel carrier based PWM method was used to
produce a five level phase voltage. Both PWM and fundamental frequency
switching methods can be used for the hybrid multilevel inverter. Multilevel
carrier based PWM strategies are the most popular methods because they are
easily implemented. Three major carrier based modulation techniques that are
used in a conventional inverter can also be applied to multilevel inverter. In
the proposed inverter, the top H-bridge inverter is operated under the SPWM
mode. The bottom standard three phase inverter is operated under square
wave mode in order to reduce switching loss.
Zhong Du et al (2009) presented a Cascaded H-bridge Multilevel
Inverter (CHMLI) that can be implemented using only a single DC power
source and capacitors. Standard cascaded multilevel inverter requires n DC
sources for (2n + 1) level. Without requiring transformers, the scheme
proposed here allows the use of single DC power source with the remaining
(n – 1) DC sources being capacitors, which was referred to as hybrid cascaded
H-bridge multilevel inverter. CHMLI using only single DC source for each
phase is useful for high power motor drive applications as it significantly
decreases the number of required DC power supplies. It also provides high
quality output power due to its high number of output levels. However, the
published technologies cannot be directly applied to CHMLI as the capacitors
are not DC sources.
Zambra et al (2010) reviewed a comparison of three topologies of
multilevel inverter applied to drive an induction motor of 500 HP/4.16 KV
rating. In this paper, Neutral point clamped inverter; symmetrical cascaded
multilevel inverter and hybrid asymmetrical cascaded multilevel inverter are
compared for the performance indexes such as total harmonic distortion, first
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order distortion factor, second order distortion factor, common mode voltage,
semiconductor power loss distribution and heat sink volume.
Domingo Ruiz-Caballero et al (2010) proposed novel symmetric
hybrid multilevel topologies that are introduced for both single phase and
three phase medium voltage high power systems. The topologies are based on
a low switch count three level pulse width modulation switching cell
connected to a low frequency switched bridge, thus, high modularity was
achieved. Compared with an H-bridge cascaded multilevel inverter, the
number of overall insulated DC sources was reduced in the proposed inverter,
Furthermore, by reducing the number of insulated DC supplies; the number of
cables connecting the input transformer terminals to the rectifying bridges is
reduced. With same numbers of semiconductors in cascaded H-bridge inverter
and three insulated DC sources, the three phase topology are generated five
level output.
Jing Zhao et al (2010) proposed a novel pulse width modulation
control method. The PWM control method was called higher and a lower
carrier cell which is an alternative phase opposition PWM for the hybrid
clamped multilevel inverter and developed based on the improvement of
carrier phase disposition PWM. The special carrier waveforms of switching
devices are split into many triangle carrier cells according to the carrier
period. The proposed novel PWM control method called higher and lower
carrier cells alternative phase opposition PWM can be obtained by increasing
carrier cells. This can reduce switching losses and improve the output
harmonic distortion in low order harmonics.
Youhei Hinago et al (2010) presented a novel multilevel inverter
with a small number of switching devices. It consists of an H-bridge and an
inverter which generates multilevel output voltage by switching the DC
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voltage sources in series and in parallel. This inverter can give output more
numbers of voltage levels in the same number of switching devices by using
this conversion. The number of gate driving circuits was reduced, which leads
to the reduction of the size and power consumption in the driving circuits. The
total harmonic distortion of the output waveform was also reduced. The
proposed inverter was driven by the hybrid modulation method.
1.3.2.3 New hybrid H-bridge multilevel inverter
The multilevel inverter using cascaded H-bridge with separate DC
sources synthesizes a desired voltage from several independent sources of DC
voltages. Each succeeding voltage source has the voltage values in the order
of 1Vdc, 3Vdc and 9Vdc called new hybrid H-bridge multilevel inverter.
Ayob and Chee (2005) proposed a new hybrid multilevel inverter
topology with harmonics profile improvement. As per the literature, a largest
output levels and the lowest total harmonics distortion percentage can be
achieved by the hybrid MLI with DC sources in trinary configuration.
However, the output contains low order harmonics topology, due to the
impossibility of modulating all adjacent voltage levels among all adjacent
levels of output waveform.
Jianye Rao et al (2008) devoted to the investigation of a new hybrid
multilevel inverter system typically suitable for high performance high power
applications. In this paper the motors are achieved by an H-bridge inverter
and the three level diode clamped inverter are connected together. But only
the main inverter concerned with DC voltage source. The conditioning
inverter was supplied by the floating ultra capacitors to store the braking
energy of motors, which will be reused. The efficiency of the system can be
improved. Compared with the traditional H-bridge inverter, this new scheme
can reduce the DC sources while maintaining the same voltage output. When
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the motor was at steady state, the improvement in power factor can be
achieved by supplying the motor from the conditioning inverter.
Jianye Rao et al (2009) presented a sensor less drive of induction
motor based on a new hybrid cascaded multilevel and SVM controls. In the
proposed drive system, the main inverter and the conditioning inverter are
connected together to drive motor, but only the main inverter was supplied by
DC voltage source. The conditioning inverter just uses suspended super
capacitors as its power source. The main and conditioning inverters can be
either H-bridge inverter or three level DCMLI inverter. Therefore,
considerable energy efficiency improvement is achieved when compared with
conventional H-bridge inverter.
Ki Seon Kim et al (2009) presented a new hybrid random pulse
width modulation scheme based on a TMS320LF2407 Digital Signal
Processor (DSP), in order to disperse the acoustic switching noise spectra of
an induction motor drive. The random PWM pulses are produced by the
logical comparison of a pseudo random binary sequence bits with the PWM
pulses corresponding to two random triangular carriers. The DSP generates
the random numbers, the Pseudo Random Binary Sequence (PRBS) bits with
a lead lag random bit and the three phase reference signals.
1.4 PROBLEM STATEMENT
The concept of multilevel inverter with separated dc sources is very
interesting due to many reasons. The multilevel inverters have many
advantages over conventional inverters. However the multilevel inverter have
drawbacks like trouble in increasing the voltage levels in the power switching
devices, switching losses ,circuit complexity and economic aspects. Also, the
increasing number of switching devices tends to reduce the overall reliability
and efficiency of the power converter.
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For example, consider the various multilevel inverter topologies
with twelve number of switching devices, the number of levels of output
phase of various inverters are given as
Cascaded H-Bridge multilevel inverter N = 2S + 1
Hybrid H-bridge multilevel inverter N = 2 1
Cascaded H-Bridge multilevel inverter produce output with seven
levels whereas the Hybrid H-bridge multilevel inverter produces fifteen level
output (S is the number of sources, example S=3).
In this research work, a New Hybrid H-bridge multilevel inverter
was described. The inverter generates 3S voltage level. The new hybrid H-
bridge multilevel inverter produces twenty seven level of phase voltage with
the same twelve switching devices. Hence, the Total Harmonic Distortion
(THD) reduced and inverter performances improved.
Therefore the main objective of the thesis is to design a New
Hybrid H-bridge multilevel inverter so as to get reduction in THD and thereby
improve the performance of inverters.
1.5 OUTLINE OF THESIS
This thesis is composed of six chapters. The overall organizations
of the chapters are as follows.
Chapter 2 discusses the theory behind the research presented in
this thesis. The modeling of induction motor and modulation strategies are
also discussed.
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Chapter 3 explores the brief summary of the single source
multilevel inverter, such as diode clamped multilevel inverter and flying
capacitor multilevel inverter. Also, the simulation and experimental results
are discussed.
Chapter 4 highlights the summary of the multisource multilevel
inverter, such as cascaded H-bridge multilevel inverter, hybrid H-bridge multi
level inverter and new hybrid H-bridge multilevel inverter. Also, in addition
to the multilevel fundamental switching scheme, block diagram, circuit
diagram, simulation results and experimental results are provided.
Chapter 5 describes the simulation results and analysis for flying
capacitor multilevel inverter, cascaded H-bridge multilevel inverter, hybrid
H-bridge multilevel inverter and new hybrid H-bridge multilevel inverter with
induction motor drive.
Chapter 6 summarizes the results of the thesis. Finally, suggestions
on possible future research are listed.