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Abstract—Cascaded multilevel converter is a series connection
of several inverters that together generate multiple voltage levels
with controllable frequency, phase and amplitude. Its main
advantages are the high power, reliability and power-quality.
However, it has considerable drawbacks as the high number of
components, many isolated power sources, decreasing voltage-
quality with the modulation index, and regeneration in some
series inverters at specific modulation indexes, even when the
machine is motoring. The authors propose to improve any
cascaded multilevel topology through two solutions; use optimal
voltage asymmetries (ratios), higher than conventional ones; and
replace the voltage sources by floating capacitors balanced with a
new control (PI controller) and/or a high frequency link (HFL).
This paper presents theoretical analysis and experimental
results of cascaded multilevel converters with increased voltage-
quality (levels), some of them keeping this high quality and
avoiding regeneration in motor mode at any motor operation
point, using the proposed voltage asymmetries and simplifying or
eliminating some voltage sources. Experimental results show a
reduction of components, an improved voltage-quality, and a
satisfactory behavior in stationary and dynamic operation.
Index Terms—Cascaded multilevel converters, asymmetric
inverters, multicell inverters, hybrid inverters, power conversion.
I. INTRODUCTION
ULTILEVEL converters are the state-of-the-art in ac
drive system and a great solution for many applications
(minerals, chemical, oil, gas, metals, paper, water, power
generation, energy conversion, manufacturing, transportation,
etc.) [1,2]. Their main advantages are the high-quality power,
wide range of power operation, operation under fault and the
use of traditional semiconductors [3,4]. Their high power-
quality is achieved by generating several voltage levels, which
reduces total harmonic distortion (THD), common-mode and
derivative voltages (dv/dt), isolation motor damage, and output
filters. However, multilevel converters are more complex in
topology, control and modulation than traditional ones (two-
level inverters), they use many semiconductors and their
power-quality decrease with the modulation index m (voltage
Manuscript received November 7, 2011; revised March 12, 2012 and June
26, 2012; accepted September 10, 2012. This work was supported by the
Comisión Nacional de Investigación Científica y Tecnológica through Project
Fondecyt 1100175, ABB Chile, and Iniciativa Científica Milenio through
NEIM Project P-07-087-F.
Copyright © 2012 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purpose must be
obtained from the IEEE by sending a request to [email protected].
The authors are with the Pontificia Universidad Católica de Chile, Santiago
7820436, Chile (e-mail: [email protected]; [email protected]).
amplitude). Multilevel converters can be classified in three
main topologies; neutral point camped (NPC), flying capacitor
(FC) and cascaded multilevel (CM) [5,6].
Cascaded multilevel converters are based on a series
connection of several inverters which are called main and
auxiliary (Aux) inverters. These inverters can have the same
(modular) or different topology (hybrid), and they can
generate the same (symmetrical) or different voltages per level
(asymmetrical). Usually the cascaded converter is composed
by h-bridges connected in series, which is called cascaded h-
bridge (CHB) converter. Anyway, the cascaded converter can
be composed by a series connection of any inverter topology.
The main advantages of cascaded converters are the use of
conventional inverters and semiconductors, the great
flexibility and fault tolerance, but they use many isolated
power supplies. Asymmetrical cascaded converters increase
the voltage-quality per number of semiconductors used [7] and
reduce the switching losses, but they lose modularity and their
auxiliary inverters regenerate at some modulation indexes,
even if the machine is motoring.
This paper proposes two general solutions to reduce or
eliminate the main drawbacks of cascaded converters and to
keep or increase their advantages. Both solutions can be
applied simultaneously or independently and they are:
i) Use new optimal voltage asymmetries among the supplies
of the series inverters to increase the voltage-quality (levels).
These asymmetries were calculated using a proposed formula
which is general to any multilevel converter.
ii) Replace or eliminate the auxiliary voltage sources by two
possible methods; floating capacitors (FC) balanced with a
new PI control; and/or a high frequency link (HFL) [8]. Both
methods can be applied together or independently.
If a main power supply with variable voltage is used, the
proposed auxiliary voltage sources work as variable voltage
supplies and keep the asymmetry without extra hardware or
software. Then, the voltage amplitude of the motor can be
controlled by the main dc voltage, so the modulation index m
of the cascaded converter is fixed. Therefore, voltage-quality
is maintained all the time and regeneration in motor mode is
avoided at any operation point of the motor. Even more, if
variable supplies are used, the voltage asymmetry of the main
inverter can be further optimized (maximized), which was
called as extreme asymmetry.
This document is organized as follow: Section II shows the
cascaded converters topologies. Section III presents the power
supply solutions. Section IV presents the optimal asymmetries.
Finally, Section V shows the experimental results.
Javier Pereda, Student Member, IEEE, and Juan Dixon, Senior Member, IEEE
Cascaded Multilevel Converters: Optimal
Asymmetries and Floating Capacitor Control
M
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II. CASCADED MULTILEVEL CONVERTER TOPOLOGIES
Cascaded multilevel converter uses several inverters
connected in series that may have any topology (Fig. 1).
Cascaded converter can be classified according with the
topologies used, the voltages supplied to each series inverter,
or the motor connection implemented, as follow:
A. Topology classification (Modular or Hybrid)
If all the inverters used in the cascaded converter have the
same topology, then the converter is modular. Otherwise, the
converter is hybrid. Fig. 2 shows all cascaded converter
topologies, which are composed by single and/or three-phase
inverters. Hybrid converters combine the advantages of the
different topologies used but they are less modular and fault
tolerant than modular and symmetrical converters, so this
trade-off must be evaluated in the design.
B. Voltage supply classification (Symmetric or Asymmetric)
If each voltage source inverter (VSI) used in the cascaded
converter generates voltage levels with the same amplitude,
then the converter is symmetrical (1:1). Otherwise, the
converter is asymmetrical. Symmetrical converters have more
redundant voltage vectors than the asymmetrical ones, so they
generate less number of vectors (levels), but they are more
faults tolerant due to their high redundancy and modularity.
Fig. 3 shows the voltage supply classification.
C. Motor Connection (Star, Delta or Open-end winding)
The motor can be connected in Y, ∆ or open-end winding,
depending on the cascaded converter topology (Fig. 2). If the
cascaded converter uses two three-phase inverters, the motor
only can have an open-end winding connection. However, this
open-end winding configuration can get exactly the same
result of Y connection because the floating neutral is created
through the inverters (Fig. 2(c), 2(e) and 2(f)).
If the motor has isolated windings (Fig. 2(b)), which is only
possible using single-phase inverters and a open-end windings
connection, some inverters of the cascaded converter can share
the same power supply, which reduces hardware but also
reduces the number of levels generated in the motor. On the
other cases, the cascaded converter must be powered by an
isolated power supply per each series inverter used.
The non-isolated open-end winding connection generates
the same voltage on each motor winding that Y. And both
generate more levels than ∆ connection due to the floating
neutral generated in the motor or through the inverters.
Fig. 1: Some possible voltage source inverter (VSI) topologies (single-phase and three-phase topologies) used in cascaded multilevel converters.
Fig. 2: Cascaded multilevel converter topologies (possible connections of inverters and motor).
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Fig. 3: Classification of cascaded multilevel converters according with the voltage sources of each voltage source inverter (VSI) connected in series.
III. PROPOSED POWER SUPPLIES FOR CASCADED
MULTILEVEL CONVERTERS
The proposed methods are two; floating capacitors and/or a
High Frequency Link. Both methods replace all the auxiliary
voltage supplies and can work together or alone (Fig. 4).
If the main voltage source is variable, both methods work as
variable voltage supplies to keep the voltage asymmetry and
the modulation index is maintained at any operation point.
Operate the cascaded converter with a fixed modulation index
(m*) has three main advantages; the regeneration on auxiliary
inverters in motor mode is avoided, the high voltage-quality is
maintained at any operation point, and the converter is
operated in the point of zero auxiliary average power.
Both methods are general solutions and applicable to any
cascaded converter (Fig. 2), but some topologies are widely
more improved than others, so the solutions must be evaluated
for each topology (Fig. 3). However, the proposed methods
are focused in asymmetric converters.
A. Method I: Floating Capacitor (FC)
This solution replaces the auxiliary voltage sources by
floating capacitors (Fig. 4a). Some publications also propose
floating capacitors, which are controlled by PWM, PS-PWM,
time-domain modulation and switching state redundancy in
multilevel converter [9-14], but this paper proposes a different
control (PI controller) that adjust a fixed modulation index
(m*) in the cascaded converter to operate the capacitors as
active filters. Therefore, the floating capacitors have zero
average power without using special PWM, PS-PWM or
vector redundancies of the cascaded converter.
As the cascaded converter operates with a fixed modulation
index all the time, the motor voltage amplitude must be
controlled by the main dc voltage source (Vdc) that must be
variable, so the floating capacitor voltages must also vary.
Fig. 5 shows the space voltage vectors of a 9-level cascaded
converter as example and the average power sign zones of the
auxiliary supplies (Paux) in the modulation index domain
[8,15]. The PI control operates the converter between the
discharging and charging area (m*=0.8 approx.) to have zero
average power in the auxiliary supplies (Paux=0). If the
capacitor voltages are lower than the reference, the error is
positive, so the PI controller slightly decreases the modulation
index to operate in the charging zone; otherwise, the PI
controller increases the modulation index to operate in the
discharging zone. The modulation index variation is very low,
so the level number is maintained under normal operation
(only the pulse width changes). However, under very fast
dynamic performance, the number of levels can be reduced
according to the capacitor time response, but this situation is
quite short (e.g. 1 s) if the capacitance is selected according to
the motor current. Moreover, under very fast operation, the
performance will be very similar to a conventional multilevel
converter that generates a level number according with the
output voltage amplitude (modulation index).
Therefore, the converter operates in the external border
(trajectory) shown in Fig. 5, which has the highest modulation
index (levels) of all possible trajectories with zero Pau.=0 The
redundancy areas have smaller modulation indexes because
they use the redundant main vectors which are in the central
area. Then, PI controller can achieve zero auxiliary average
power in a higher modulation index than using redundant main
vectors. Therefore, PI controller can be applied in converters
with very high asymmetries, where redundancy control does
not work because the vector redundancy is minimized.
It is important to clarify that vector redundancy comes from
each series inverter and from the combination of all these
inverters (multilevel converter redundancy). The multilevel
converter redundancy is reduced with voltage asymmetry, but
the redundancy of each series inverter is maintained because
its topology is not manipulated. Therefore, a second control
(capacitor balance control) uses the vector redundancy of the
auxiliary inverters to balance the capacitors and to assist the PI
control, increasing stability and dynamic performance.
PI Control
The proposed PI control is briefly illustrated in Fig. 6 where
a reference voltage vector is introduced from a motor control
(open loop, v/f, DTC, etc.), then its amplitude is compensated
because the cascaded converter is sub-modulated (m*<1). The
compensated amplitude is introduced in the variable source as
reference to obtain Vdc. The capacitor voltages are compared
with the reference, which is obtained applying the voltage
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ratio r to the main voltage Vdc (e.g. r =¼ if the asymmetry is
1:4). Finally, the error is introduced in the PI controller to
adjust the fixed modulation index (m*) of the cascaded
converter, which is the manipulated variable to control the
capacitor voltages.
If two or more floating capacitors are used, the PI control is
the same showed in Fig. 6, but the controlled variable is the
sum of all floating capacitor voltages, so r must be multiplied
by the number of floating capacitors (M) and a second control
must be added to balance the floating capacitors.
Capacitor Voltage Balance Control
This control balances the capacitor voltages and assists the
PI controller using the redundant auxiliary vectors by a model
predictive control (MPC) that minimizes the cost function J
(1). The manipulated variables are the redundant vectors (k) of
the space vector that was previously selected by the space
vector control (SVC). The cost function quantifies the future
quadratic error of each capacitor, using the capacitor voltages
vj and reference Vref (r·Vdc), the phase currents (ia, ib, ic), the
capacitances Cj, the sampling period Ts, the charging effect on
each capacitor Sj(k) and weighting coefficients λj (usually not
used). However, other balance controls can be used as special
carrier-based PWM or space vector modulation (SVM) by the
nearest three vectors (NTV) [16-20].
Fig. 4: Power supply solutions for cascaded converters: a) floating capacitors
(FC), b) high frequency link (HFL), and c) FC combined with HFL.
Fig. 5: 9-level CHB converter (Paux sign and control strategies).
���� = � �� ∙ �� � − ���� + ��|�������� (1)
���� + ��|�� = ���� ∙ �� ∙ ������ + ����� (2)
�� = � � " # $ , & , '( )*+ 1 − -ℎ/01 2�1+�1+03 $ & '4 )*+ 3 − -ℎ/01 2�1+�1+06 (3)
������ =7898: ����� )*+ 1 − -ℎ/01 2�1+�1+0
;��$�����&�����'���< )*+ 3 − -ℎ/01 2�1+�1+06 (4)
�����*+������3=4 = > 1 ) ?@A B/-/B �*+ 0 B*221B�1C C +1B�DE 0 ) ?@A B/-/B �*+ 0 C 0B*221B�1C −1 ) ?@A B/-/B �*+ 0 B*221B�1C 2�1+01DE6 (5)
B. Method II: High Frequency Link (HFL)
HFL is presented in [8] and proposed in this paper because
it is ideal as a multiple variable voltage supply. HFL is also
ideal to work with optimal asymmetries and fixed modulation
indexes because it generates auto-balanced variable voltages
and its power is highly reduced (small HFL).
HFL is a high frequency toroidal transformer to supply the
auxiliary inverters with a fixed voltage (r·Vdc), so the auxiliary
voltages change with the main voltage Vdc and keep the
voltage ratio r (N1/Nmain), even if Vdc is variable. HFL uses an
h-bridge to generate a square voltage, and h-bridge rectifiers
to obtain the auxiliary dc voltages.
HFL works at any modulation index and it can supply all
the auxiliary inverters without close-loop control or works
with the floating capacitors as shown Fig. 6, where the HFL
supplies six auxiliary single-phase inverters as example.
Fig. 6: Floating capacitors (FC) and/or high frequency link (HFL) to supply
each inverter of the cascaded multilevel converter.
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IV. OPTIMAL AND EXTREME VOLTAGE ASYMMETRIES
This section presents the classic and proposed optimization
of voltage asymmetries. The classic one is focus in maximize
the levels generated by the converter (L), and the proposed one
t is focused in maximize the levels generated on each motor
winding (Lm). However, both methods of optimization do the
same; they maximize the voltage ratios (6), which are limited
to different values according on the method of optimization
applied. The parameters are defined in Table I.
The number of space voltage vectors of an inverter is
determined by the number of phases and voltage levels per
phase (7). For a cascaded converter, the voltage vectors are
the product of the vectors of all inverters, so a high number of
vectors are generated, but many of them are redundant. The
conventional optimization increases the non-redundant vectors
indirectly, as consequence of maximize L (8). In contrast, the
proposed optimization maximizes the redundant vectors to
increase Lm directly. Table II and Fig. 7 show some proposed
and conventional optimal voltage asymmetries as examples.
+� = �� ��⁄ (6)
2H = > IJ )*+ / 0 2KD1 2�1+�1+0 L I��JM
��� )*+ / B/0B/C1C B*2�1+�1+6 (7)
2HNONP� QRNQ$N@ = 1 + S ∙ I ∙ �I − 1� (8)
A. Conventional Optimal Asymmetries (Maximizing L)
This conventional optimization maximizes L, which is the
same as maximize each voltage ratio (9-10). However, these
voltage ratios are limited by the level number of the previous
(smaller) series inverters to ensure a generation of equidistant
levels in the phase voltage of the converter.
+� ≤ I��P�� I��� = 1 + ∑ += ∙ �I= − 1��=�� (9)
I = I�M� (10)
B. New Optimal and Extreme Asymmetries (Maximizing Lm)
These proposed optimizations maximize Lm, which is the
same as maximize each voltage ratio or the non-redundant
vectors. However, maximize the non-redundant vectors is
easier and more general than maximize Lm, because the space
voltage vectors of the converter and the motor are always
equivalent, and the converter and motor voltage are different
according with the modulation and motor connection; Y or
open-end winding (Lm>Lff>L); ∆ (Lm=Lff>L); and isolated
open-end winding (Lm=L). So the proposed optimizations are
applicable to any motor connection except for the isolated one
(Fig. 2b), because its space voltage vector is virtual (no phase-
phase voltages) and maximize Lm does not make sense (Lm=L).
The new asymmetries generate distorted converter phase
voltages (non-equidistant levels) and the same L than classic
optimal asymmetry. However, they generate equidistant levels
in each motor winding (phase) and maximize Lm due to the
right combination of the distorted converter phase voltages
that optimizes the phase-phase voltages. So, the converter has
a virtual level number (L*) higher than conventional (L*≥L).
Other advantage is the power reduction in aux. inverters,
ideal to use floating capacitors or HFL as auxiliary sources.
Proposed Optimal Asymmetries
This optimization maximizes the voltage ratios, but they are
limited by (11) to ensure equidistant voltage vectors and levels
in the motor winding voltages at any modulation index.
+� ≤ 1 + )D**+ V32 I��P�� − C�P� − 1�X (11)
C� = Y 0 ) I� 0 *CC /2C C�P� = 0 /2C ? < [)D**+ \]�^_`�P�� − a� C�P�b c�ℎ1+ B/01 6 I∗ = I�M� − CM� ℎ⁄ (12)
ℎ = Ycos h6 ∙ �IM − 1� ) IM 0 *CC /2C CM ≠ CMP� 1 c�ℎ1+ B/01 6
Proposed Extreme Asymmetries
If LN ≤ 3 and the converter works with a fixed modulation
index m*, the last voltage ratio rN can be higher to maximize
Lm to the extreme (non-redundant vectors in the cascaded
converter). Therefore, the voltage ratio of the Nth
inverter
(biggest) is limited by (13) to ensure that the fixed trajectory
has equidistant vectors. So the motor works as if the converter
will generate L* number of levels (14). This fixed trajectory
match with the fixed modulation index (m*) presented in
section III (zero average auxiliary power), so this extreme
asymmetry is compatible with floating capacitors or HFL.
+M ≤ 2 ∙ I�MP�� − 1 (13)
I∗ = 1 + +M ∙ �IM − 1�� ℎ⁄ (14)
ℎ = � 1 ) IM = 2 cos �h 12⁄ � ) IM = 3 6 TABLE I
PARAMETERS OF THE CASCADED CONVERTERS AND INVERTERS
N N° of series inverter in the cascaded converter
L N° of levels in each phase voltage of the entire converter
Lj N° of levels in each phase voltage of the single jth inverter
L(j) N° of levels in each phase voltage of the partial converter
(using from the 1st to the jth series inverter)
Lff N° of levels in each phase -phase voltage of the entire converter
Lm N° of levels in each winding (phase) voltage of the motor
F N° of phases of an inverter
nv N° of space voltage vector of the entire converter
rj Voltage ratio of jth inverter respect to the 1st (smallest)
Vj Voltage of each level generated by the jth single inverter
TABLE II
EXAMPLES OF CONVENTIONAL AND PROPOSED OPTIMAL ASYMMETRIES
Series inverter
levels (e.g.)
Classic optimal
asymmetries
New optimal
asymmetries
New extreme
asymmetries
L1:L2:L3 r1:r2:r3 L r1:r2:r3 L* r1:r2:r3 L*
2-2-2 1:2:4 8(23) 1:2:5 8 1:2:7 8
3-2-2 1:3:6 12(22·3) 1:4:8 14 1:4:13 14
2-3-2 1:2:6 12(22·3) 1:2:8 12 1:2:11 12
3-3-2 1:3:9 18(32·2) 1:4:16 22 1:4:21 22
2-2-3 1:2:4 12(22·3) 1:2:5 13 1:2:7 16
3-2-3 1:3:6 18(32·2) 1:4:8 22 1:4:13 28
2-3-3 1:2:6 18(32·2) 1:2:8 21 1:2:11 24
3-3-3 1:3:9 27(33) 1:4:16 39 1:4:21 45
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Fig. 7: Space voltage vectors of the converter and motor (both are identical) from the examples of Table II.
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V. EXPERIMENTAL RESULTS
Three topologies were implemented with floating capacitors
(22 mF) and proposed asymmetries. A 3 kW motor and
ABB® industrial controller (AC800PEC) were used
sampling period (Ts) of 50 us. The switching
fundamental for the main inverter and it is
fundamental for the smallest auxiliary inverter
rising on each inverter according with its asymmetry
The experimental results illustrate the motor phase
and currents in steady state and dynamic operation
A. 3-Level + 2-Level Inverters
Three possible topologies were tested generating the same
motor voltages (Fig. 8). Fig. 9 shows experimental voltages
with the proposed optimal asymmetries (1:4), where the motor
voltages have 15 levels and a THDv of 5.5%
the voltages using the proposed extreme asymmetries (
where the motor voltages have 18 levels and a THD
B. Two 3-Level Inverters
Four possible topologies are illustrated in Fig.
experimental voltages with the proposed optimal asymmetries
(1:4) are shown in Fig. 12, where the motor voltages have 28
levels and a THDv of 3%. Fig. 13 shows the voltages using the
proposed extreme asymmetries (1:5), where the motor
voltages have 34 levels and a THDv lower than 3%
Vdc
Vdc
n
n1
n2
a1 a2
Vdc
Vdc
n
N
Vdc
Vdc
n
Vdc
n
n1
n2
Fig. 8: Cascaded converter using a 3-level (aux) and a 2-level inverter.
Fig. 9: Motor voltages using proposed optimal asymmetries (1:4)
Fig. 10: Motor voltages using proposed extreme asymmetries (1:5)
10V/ 200mA/ 10ms/ 50V/ 5ms/
10V/ 200mA/ 10ms/ 50V/ 5ms/
floating capacitors
kW motor and an
were used with a
switching frequency is the
and it is LN ·rN times the
inverter, so frequency is
asymmetry.
motor phase voltages
state and dynamic operation.
were tested generating the same
experimental voltages
), where the motor
%. Fig. 10 shows
the voltages using the proposed extreme asymmetries (1:5),
and a THDv of 4.8%.
in Fig. 11 and the
the proposed optimal asymmetries
, where the motor voltages have 28
shows the voltages using the
), where the motor
lower than 3%.
n
level inverter.
: Motor voltages using proposed optimal asymmetries (1:4) in Fig. 8.
using proposed extreme asymmetries (1:5) in Fig. 8.
C. Three 3-Level Inverters
The topologies illustrated in Fig.
using floating capacitors in the middle
the smallest one (the same system illustrated in
Fig. 15 shows the voltages using the optimal asymmetries
1:4:16 (n1=4 and n2=16), where the motor voltages have 1
levels. Fig. 16 shows the voltages using
1:4:21 (n1=4 and n2=21), obtaining
voltage. The trajectory to get equidist
Fig. 14 and matches with the zero power trajectory (
floating capacitors could be used by PI control (Fig. 6
The THDv of both voltage asymmetries are
than 2%) and the voltage is sinusoidal at simple view.
Vdc
n
Vdc
n
Vdc
Vdc
n1
n2
a1
a2
Vdc
n
Vdc
Vdc
N
Vdc
Vdc
n
N
n
a cb
Vdc
n
Vdc
Vdc
n1
Fig. 11: Cascaded converters using two 3-level inverters.
Fig. 12: Motor voltages using proposed optimal asymmetries (1:4)
Fig. 13: Motor voltages using proposed extreme asymmetries (1:5)
50V/ 500mA/ 20ms/
50V/ 500mA/ 20ms/ 50V/
50V/
7
The topologies illustrated in Fig. 14 were implemented
middle inverter and a HFL in
the same system illustrated in Fig. 6.)
shows the voltages using the optimal asymmetries
the motor voltages have 104
shows the voltages using extreme asymmetries
obtaining 123 levels in the motor
ory to get equidistant voltages is shown in
and matches with the zero power trajectory (m*), so
ld be used by PI control (Fig. 6).
of both voltage asymmetries are very low (less
is sinusoidal at simple view.
n
n2
a1 a2
level inverters.
Motor voltages using proposed optimal asymmetries (1:4) in Fig. 11.
Motor voltages using proposed extreme asymmetries (1:5) in Fig 11.
0V/ 5ms/
50V/ 5ms/
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Vdc
n1
n
Vdc
Vdc
N
Vdc
n2
a
c
b
Vdc
n1
n2
Vdc
Vdc
n1
Vdc
n2
Vdc
n2
Vdc
N
n
a cb
Vdc
n1
Vdc
n2
Vdc
n1
Vdc
Vdc
n1
Vdc
n2
Fig. 14: Cascaded converters using three 3-level inverters.
Fig. 15: Motor voltages using new optimal asymmetries (1:4
Fig. 16: Motor voltages using new extreme asymmetries (1:4:21
50V/ 1A/ 50ms/
50V/ 1A/ 50ms/
50V/ 2ms/
50V/ 2
a1 a2
a1 a2
N
level inverters.
optimal asymmetries (1:4:16) in Fig. 14.
Motor voltages using new extreme asymmetries (1:4:21) in Fig. 14.
All the topologies illustrated in Fig. 14
voltages in the motor windings for a determined asymmetry.
The topologies with open-end winding connection do not
have a motor neutral (n) and the converter has two neutral
and n2). However, the motor is connected in star
converter, so these topologies generate
that the star motor connection. The voltage
(15-17), where vaN is the phase voltage of the converter,
the phase-phase voltage of the motor or converter (are the
same), and van is the phase voltage of the motor winding.
�$M = � �$M k *+ ∆ m*�*+�$�N� � �$�N� c-12 ��$& � � ��$M � �&M� k *+��$� � �&�� � ��$� � �&�� c-12
�$N � Y �$& � �'$3 k m*�*+��$� � �$�� c-12 �
Fig. 17 shows these voltages (van
topology of Fig. 14 with extreme asymmetry
phase voltage of the converter (vaN)
the conventional optimal asymmetry (1:3:9), but these
levels are non-equidistant, which generate
distorted waveform. However, the phase
voltages of the motor have equidistant levels
waveform and more voltage levels
so the motor receive a higher power
inverters manages less power. This is possible because the
control is focused on three-phase system
distorted (non-equidistant) phase voltage of the
generate an uniform (equidistant) phase
is possible using the fixed modulation index
D. Floating Capacitor Voltages
Fig. 18 shows the voltage and current
(22 mF) used in Fig. 8 in steady and dynamic
steady operation, the capacitor voltage ripples only can be
seen in the oscilloscope using AC
voltage has not appreciable variations
three voltage capacitors are balanced and controlled.
Fig. 17: Voltages using proposed extreme asymmetries (1:4:21
Fig. 18: Floating capacitor voltage and current
phase capacitor voltages (Fig. 8 topology with extreme asymmetries
2ms/
50V/ vaN
van
2ms/ 5ms/ 200mV/ 2A/
100V/ vcap-dc van
vcap-ac icap vcap (A,B
van
8
opologies illustrated in Fig. 14 generate the same
in the motor windings for a determined asymmetry.
end winding connection do not
and the converter has two neutral (n1
the motor is connected in star through the
, so these topologies generate the same motor voltage
he voltages are defined in
is the phase voltage of the converter, vab is
phase voltage of the motor or converter (are the
is the phase voltage of the motor winding.
m*�*+ B*221B� *2� 12C n 2C 2K 6 (15)
*+ ∆ m*�*+ B*221B� *2c-12 � 12C n 2C 2K 6 (16)
m*�*+ B*221B� *212C n 2C 2K6 (17)
an, vaN and vab) using any
with extreme asymmetry (1:4:21). The
) has the same levels (27) as
the conventional optimal asymmetry (1:3:9), but these voltage
which generate jumped levels and
. However, the phase and phase-phase
have equidistant levels with a sinusoidal
levels than regular asymmetries,
so the motor receive a higher power-quality and the auxiliary
This is possible because the
phase systems, so it combines the
phase voltage of the converter to
phase-phase voltage, which
is possible using the fixed modulation index m*.
and current of floating capacitor
and dynamic operation. In
voltage ripples only can be
using AC coupling because the
variations. In the dynamic test, the
three voltage capacitors are balanced and controlled.
roposed extreme asymmetries (1:4:21) in Fig. 14.
oltage and current (vcap and icap) in phase A and 3-
with extreme asymmetries 1:5).
2ms/ van 50V/
vab 100V/
100ms/ cap 20V/ B,C)
an 5V/
> 11-0849-TIE <
9
VI. DISCUSSION
The dynamic performance and voltage ripples in the
floating capacitor depend on the capacitance, the current load
and switching frequency. When a very fast dynamic operation
is required, the performance will be limited by the
capacitance, which must be over a limit to insurance stability.
In the worst cases, the voltage quality will decrease for
milliseconds until the floating capacitors get the reference.
However, if we compare this limit case with conventional
multilevel converter, which decreases the level number under
nominal operation, the proposed solution is similar or better.
Other solution for high dynamic performance is to replace the
floating capacitors by a HFL because it has a very high
dynamic performance [8,15].
The proposed control is more complex than conventional
ones because it requires a PI controller, a capacitor balance
control and voltage sensors for each floating capacitor, but the
hardware is reduced. The complexity is in the software and
does not represent a limitation or increased cost because the
actual technology allows high computation at low cost.
VII. CONCLUSION
Over-optimal and extreme voltage asymmetries for general
cascaded multilevel converters were presented in this paper
through general formulas. These voltage asymmetries increase
the voltage-quality (levels) compared with conventional ones,
even when they work with lower modulation indexes (m*).
However, the extreme asymmetry requires variable voltage
sources to operate in all the amplitude voltage range without
voltage distortion in the motor (working in a fixed m*).
Two methods to eliminate or replace the isolated voltage
sources were also presented; a PI controller to use floating
capacitors; and a high frequency link (HFL) as isolated
voltage source. Both methods can work together or alone.
The dynamic response of converters with floating capacitors
is limited by the voltage variation rate, which depends on the
capacitance value and motor current, but the capacitance also
increase the control stability, so the design has a tradeoff that
should be evaluated according to the requirements.
The proposed asymmetries are ideal to apply floating
capacitors and/or HFL because they reduce the power
requirement of auxiliary inverters, increasing control stability
and reducing the capacitor and HFL size. Even more, the
single space voltage trajectory (m*) of extreme asymmetries
matches with the zero average power in auxiliary inverters,
which makes possible the application of floating capacitors.
Experimental results of several topologies were shown with
satisfactory results in stationary and dynamic tests.
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> 11-0849-TIE <
Javier Pereda (S’09) was bor
He received the electrical engineering degree with
highest honors from the Pontificia Universidad
Católica de Chile, Santiago, in 2009, where he is
currently working toward the Ph.D. degree.
He is research assistant in power electron
electrical machines, power generation and electric
traction with the Department of Electrical Engineer
ing, Pontificia Universidad Católica de Chile, where
he is also part of the Electric Vehicle Laboratory. He
is currently working on ac motor drives,
control and new multilevel inverter topologies.
Mr. Pereda is a member of Millennium Nucleus of Power Electronics,
Mechatronics and Control Process (NEIM) and a Comisión Nacional de
Investigación Científica y Tecnológica (Conicyt) scholarsh
(S’09) was born in Santiago, Chile.
He received the electrical engineering degree with
highest honors from the Pontificia Universidad
Católica de Chile, Santiago, in 2009, where he is
currently working toward the Ph.D. degree.
He is research assistant in power electronics,
electrical machines, power generation and electric
traction with the Department of Electrical Engineer-
ing, Pontificia Universidad Católica de Chile, where
he is also part of the Electric Vehicle Laboratory. He
is currently working on ac motor drives, direct torque
Mr. Pereda is a member of Millennium Nucleus of Power Electronics,
Mechatronics and Control Process (NEIM) and a Comisión Nacional de
Investigación Científica y Tecnológica (Conicyt) scholarship holder.
Juan Dixon (SM)
received the Ms. Eng. and the Ph.D. degrees from
McGill University, Montreal, PQ, Canada in 1986,
and 1988 respectively. Since 1979, he has been with
the Electrical Engineering Department, Pontific
Universidad Católica de Chile, where he is presently
Professor. He has presented more than 70 works in
International Conferences and has published more
than 40 papers related with Power Electronics in
IEEE Transactions and IEE Proceedings. His main
areas of interest are in Electric Traction, PWM
Rectifiers, Active Filters, Power Factor Compensators and Multilevel
converters. He has created an Electric Vehicle Laboratory, where state
art vehicles are investigated.
10
was born in Santiago, Chile. He
received the Ms. Eng. and the Ph.D. degrees from
McGill University, Montreal, PQ, Canada in 1986,
and 1988 respectively. Since 1979, he has been with
the Electrical Engineering Department, Pontificia
Universidad Católica de Chile, where he is presently
Professor. He has presented more than 70 works in
International Conferences and has published more
than 40 papers related with Power Electronics in
IEEE Transactions and IEE Proceedings. His main
s of interest are in Electric Traction, PWM
Rectifiers, Active Filters, Power Factor Compensators and Multilevel
converters. He has created an Electric Vehicle Laboratory, where state-of-the-