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Carbon Nanotube Imperfection-Immune
Digital VLSI
H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong, J. Zhang
Subhasish Mitra
Robust Systems Group
Department of EE & Department of CS
Stanford University
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Carbon Nanotube (CNT)
Diameter (D) : 0.5 - 3 nm
D
S. Iijima
Carbon Nanotube FET (CNFET)
2
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Ideal CNFET Inverter
N+ dopedSemiconducting
CNTs
Gates
Input
P+ dopedSemiconducting
CNTs Lithographic
pitch
4nm
Sub-lithographicpitch
Output
Vdd
Gnd
3
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CNFET Technology Milestones
4
1998First CNFETdemonstration[Delft, IBM]
1998First CNFETdemonstration[Delft, IBM]
2001Single-CNTlogic gates[IBM]
2001Single-CNTlogic gates[IBM]
2006Single-CNTring osc.[IBM]
2006Single-CNTring osc.[IBM]
2004Best single-CNTCNFET[Stanford]
2004Best single-CNTCNFET[Stanford]
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CNFETs: BIG Promise, BUT
Major barriers for a decade
Mis-positioned nanotubes
Metallic nanotubes
Processing alone inadequate
Imperfection-immune
design essential
5
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Wanted: (A+C) (B+D)
Got : B+D
Out
A B
C D
Vdd
A C
B D
Gnd
Wanted: AC + BD
Got: AC + BD + AD
Mis-positioned CNTs Incorrect Logic
6
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Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)
CNFET with s-CNT CNFET with m-CNT
Metallic CNTs
Typical: 10 50% grown CNTs metallic
Cu
rrent
Vg
Transistor
Vg
Cu
rrent
No gate
control
7
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Results
Yesterday
SSI single-CNT ring oscillator
Today
Imperfection-immune VLSI circuits
8
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CNFET Technology Milestones
9
1998First CNFETdemonstration[Delft, IBM]
2001Single-CNTlogic gates[IBM]
2001Single-CNTlogic gates[IBM]
2006Single-CNTring osc.[IBM]
2006Single-CNTring osc.[IBM]
2004Best single-CNTCNFET[Stanford]
2004Best single-CNTCNFET[Stanford]
2008Mis-positioned-CNT-immuneVLSI logic gates[Stanford]
2008FlexibleCNTcircuits[UIUC]
2009Imperfection-immune adders& latches[Stanford]
2009Defect-tolerantlogic gates[USC]
2009Monolithic3D CNTcircuits[Stanford]
2010Ultra-shortchannelCNFETs[IBM]
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CNFET Technology Outlook
Problem Challenge Status
CNT alignment
& positioning Correct function
Metallic CNTCorrect function
Low leakage
CNT densityHigh current
density
CNT dopingComplementary
CNFETs
10
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Outline
Introduction
Mis-positioned-CNT-immune logic Metallic-CNT-immune logic
CNT variations
Conclusion
11Patil, IEEE TCAD 2008, Symp. VLSI Tech. 2008
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1. Grow CNTs
Mis-positioned-CNT-Immune NAND
12
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BA
A
B
Out
1. Grow CNTs
2. Extended gate & contacts
CRUCIAL
13
Mis-positioned-CNT-Immune NAND
Vdd
Gnd
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BA
A
B
Out
1. Grow CNTs
2. Extended gate & contacts
3. Etch gate & CNTs
4. Chemically dope P & N regions
Vdd
Gnd
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Mis-positioned-CNT-Immune NAND
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BA
A
B
Out
1. Grow CNTs
2. Extended gate & contacts
3. Etch gate & CNTs
4. Chemically dope P & N regions
Etchedregion
ESSENTIAL
Graph algorithms
All possible functions
Vdd
Gnd
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Mis-positioned-CNT-Immune NAND
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Automated Algorithms
Given: Layout
Determine Mis-positioned-CNT immune ?
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Mis-positioned-CNT-Immune NAND
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E
Doped
Doped
Gate B
Contact
Doped
Contact
Gate A
Doped
Etched
1
1A B
1
1
0
Contact
Contact
B
Contact
Contact
A
GA GB
Intended:A or B
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Mis-positioned-CNT-Immune NAND
18
E
Doped
Doped
Gate B
Contact
Doped
Contact
Gate A
Doped
Etched
C-D-A-D-C : A
1
1A B
1
1
0
Contact
Contact
B
Contact
Contact
A
GA GB
Intended:A or B
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Mis-positioned-CNT-Immune NAND
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Gate B
Contact
Doped
Contact
Gate A
Doped
Etched
C-D-A-D-C : A
C-D-B-D-C : B
1
1A B
1
1
0
B
Contact
Contact
A
E
Doped
Doped
Contact
Contact
GA GB
Intended:A or B
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Mis-positioned-CNT-Immune NAND
20
E
Doped
Doped
Gate B
Contact
Doped
Contact
Gate A
Doped
Etched
C-D-A-D-C : A
C-D-B-D-C : B
C-D-B-D-A-D-B-D-C : A & B
1
1A B
1
1
0
Contact
Contact
B
Contact
Contact
A
GA GB
Intended:A or B
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Mis-positioned-CNT-Immune NAND
21
E
Doped
Doped
Gate B
Contact
Doped
Contact
Gate A
Doped
Etched
C-D-A-D-C : A
C-D-B-D-C : B
C-D-B-D-A-D-B-D-C : A & B
C-D-E-D-C : 0
1
1A B
1
1
0
Contact
Contact
B
Contact
Contact
A
GA GB
Intended:A or B
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Mis-positioned-CNT-Immune NAND
22
E
Doped
Doped
Gate B
Contact
Doped
Contact
Gate A
Doped
Etched
Intended:A or B
Implemented:
A or B or
(A & B) or 0==
A or B
C-D-A-D-C : A
C-D-B-D-C : B
C-D-B-D-A-D-B-D-C : A & B
C-D-E-D-C : 0
1
1A B
1
1
0
Contact
Contact
B
Contact
Contact
A
GA GB
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Automated Algorithms
Given: Logic function
Produce
Mis-positioned-CNT immune layout
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Mis-positioned-CNT-Immune Layout
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Gates
Out =A + (B + C)(D + E)
Etched regionsCNTs
CB
Vdd / Gnd Contact
A
Output Contact
ED
IntermediateContact
Immune to LARGE number of mis-positioned CNTs
Efficient
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Most Importantly
VLSI processing
No die-specific customization
VLSI design flow
Immune library cells
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CNT Growth on Silicon Substrates
Highly mis-positioned
Not desirable for VLSI
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10 m 4 m
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27
SEM image (grown CNTs)
Quartz waferwith catalyst
AlignedCNT growth
99.5% CNTs aligned
Quartz wafer
First Wafer-Scale Aligned CNT Growth
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28
Silicon substrates for VLSI
Low temperature (90oC 120oC) processing
2 m 2 m
Before transfer After transfer
Target Substrate (SiO2/Si)Source Substrate (Quartz)
Thermal ReleaseAdhesive Tape
Wafer-Scale CNT Transfer
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29
First VLSI Demonstration
10m10m10m
Mis-positioned-CNT-immune logic gates
NAND, NOR, AND-OR-INV, OR-AND-INV
NOR pullup
Etched Region
0
50
100
off
off
off
on
on
off
on
on
A
B
off = 2V, on = -2V
Curren
t(A)
0
0.75
1.5
off
off
off
on
on
off
on
on
A
B
off = 5V, on = -5V
Curren
t(A)
NAND pullup
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Outline
Introduction
Mis-positioned-CNT-immune logic
Metallic-CNT-immune logic
CNT variations Conclusion
30Patil, IEDM 2009, Shulaker, Nanoletters 2011, Wei, IEDM 2009, Symp. VLSI Tech. 2010
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Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)
CNFET with s-CNT CNFET with m-CNT
Metallic CNTs
Typical: 10 50% grown CNTs metallic
Current
Vg
Transistor
Vg
Current
No gate
control
31
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m-CNT Processing Options
Grow 0% m-CNTs
Open challenge
Remove m-CNTs after growth
99.99% removal required
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Existing m-CNT Removal
Sort CNTs
Inadequate
SDB
Single Device electrical Breakdown Not scalable
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SDB Technique
Current-induced m-CNT breakdown
Single-device level
34m-CNTs
s-CNTs
Collins, Science 2001
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SDB Technique
Current-induced m-CNT breakdown
Single-device level
35m-CNTs
s-CNTs
Collins, Science 2001
Gate
off
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SDB Technique
Current-induced m-CNT breakdown
Single-device level
36m-CNTs
s-CNTs
Collins, Science 2001
Gate
off
High Voltage
Gnd
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SDB T h i
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SDB Technique
Current-induced m-CNT breakdown
Single-device level
38m-CNTs
s-CNTs
Collins, Science 2001
Gate
off
High Voltage
Gnd
m-CNTbroken
Current density(A / m)
102
101
100
10-1
100 102 104 106
Ion/ Ioff
BeforeSDB After
SDB
M j SDB Ch ll
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Major SDB Challenges
Incorrect logic
m-CNT fragments
Impractical for giga-scale ICs
Internal node access
39
I t L i ith SDB
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Incorrect Logic with SDB
40
Output Contact
Gnd Contact
Intermediate Contact
A B
C D
off
off
off
off
Gnd
High
Broken
High
Pull-up Network
Vdd
Incorrect Logic !
Wanted:(A + B) (C + D)
Got:
(C + D)
VMR m CNT Imm ne Design
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VMR: m-CNT Immune Design
New approach: VLSI Metallic CNT Removal
Sufficient
All logic designs
VLSI processing & design flows
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VMR Example
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Final intended design
VDD
GND
VMR Example
42
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VMR Steps
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2. Fabricate VMR electrodes1. Grow and transfer CNTs
Silicon Back-Gate
Back-Gate Oxide
VMR ElectrodesVMR ElectrodesVMR ElectrodesVMR ElectrodesVMR Electrodes
Inter-digitated VMR electrodesElectrical breakdown friendly
44
VMR Steps
VMR Steps
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2. Fabricate VMR electrodes
3. Electrical breakdown (back-gate)
1. Grow and transfer CNTs
High
voltageGnd
Silicon Back-Gate
Back-Gate Oxide
VMR ElectrodesVMR ElectrodesVMR ElectrodesVMR ElectrodesVMR Electrodes
Inter-digitated VMR electrodesElectrical breakdown friendly
45
VMR Steps
VMR Steps
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2. Fabricate VMR electrodes
3. Electrical breakdown (back-gate)
4. Etch CNTs : predefined regions(mis-positioned-CNT-immune design)
5. Etch unneeded VMR electrodes
1. Grow and transfer CNTs
CNFETcontacts
notremoved
46
VMR Steps
VMR Steps
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2. Fabricate VMR electrodes
3. Electrical breakdown (back-gate)
4. Etch CNTs : predefined regions(mis-positioned-CNT-immune design)
5. Etch unneeded VMR electrodes
6. Top-gates (mis-positioned-CNT-immune design), doping, wires
1. Grow and transfer CNTs
47
VMR Steps
Theorem
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Theorem
48
VMR works for arbitrary logic design
if
Any two transistors in series
Connected through contact
Minimum pitch
Immune library cells: very small impact
First Experimental Demonstration
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First Experimental Demonstration
49
Half-adder Sum D-latch
Imperfection-immune CNT VLSI circuits
Arithmetic & storage elements
First Monolithic CNT 3D ICs
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First Monolithic CNT 3D ICs
50
Conventional via, NOT TSV2-layer CNT XOR
Outline
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Outline
Introduction
Mis-positioned-CNT-immune logic
Metallic-CNT-immune logic
CNT variations
Conclusion
51Zhang, IEEE TCAD 2009, DAC 2009, DAC 2010
CNT Variations Challenging
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CNT Variations Challenging
Probabilistic modeling essential [Borkar 07]
52
CNFET Ion variations
OthersCNT diametervariations
CNT density
variations
m-CNTs
Channel lengthvariations
Probabilistic CNT Growth Model
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Probabilistic CNT Growth Model
Probability (m-CNT) = pm
Probability (s-CNT) = ps = 1 - pm
53
2
2 13 0.22
3 3
=
s-CNT m-CNT
3
10.04
3
=
3
20.3
3
=
2
1 23 0.44
3 3
=
m-CNT Removal Alone Inadequate
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m-CNT Removal Alone Inadequate
54
m-CNTs removed
s-CNTs intact
m-CNT
Must be highly unlikely
No CNTs left !
prob. = (pm)3
= (33%)3
= 4%
Probabilistic Design a MUST
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Probabilistic Design a MUST
55
DesignProcessing
% grown m-CNTs
CNT density variations
Special layouts
CNFET sizing
Processing & Design Co-Optimization
LeakageNoise margin Delay variations
Special Layouts
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Special Layouts
56
Yield
low
high
low high
CNT
variation-agnostic
design
Upsize CNFETs
New technique
Aligned-active layouts
Engineered CNT correlations
1
Cost
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Thanks to our Sponsors
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p
Photo credits:H. Dai, ibm.com, Nanoletters, Nature, Science, Stanford, Wikipedia
58
CNFET Technology Outlook
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gy
Problem Challenge Status
CNT alignment
& positioning
Correct function
Metallic CNTCorrect function
Low leakage
CNT densityHigh current
density
CNT dopingComplementary
CNFETs
59
Conclusion
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Imperfection-immune design essential
New solutions: practical, elegantly simple
60
Next challenge: CNT variations
CNT correlation unique layouts