CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
SEQUENTIAL FSM CORE
A graduate project submitted in partial fulfilment for the requirement
Of the degree of Master of Science
In Electrical Engineering
By
Pawan Ghotikar
May 2015
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The graduate project of Pawan Ghotikar is approved:
__________________________________________ ________________________
Dr. Shahnam Mirzaei Date
__________________________________________ ________________________
Dr. Ali Amini Date
__________________________________________ ________________________
Dr. Ramin Roosta, Chair Date
California State University, Northridge
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ACKNOWLEDGEMENT
I would like to express my heartfelt appreciation to all those who contributed their time
and efforts towards successful completion of my graduate project. I feel honored to work
under the guidance of Dr. Ramin Roosta. I am grateful to Dr. Ramin Roosta for his valuable
time, ideas and advice throughout the phase of my project. Dr. Ramin Roosta has been
truly instrumental for all the support I needed for the project. I would like to extend my
appreciation to Dr. Shahnam Mirzaei and Dr. Ali Amini for their valuable time for my
project. I feel fortunate to have them in my Project Committee team.
I am also grateful to my family for their patience and support throughout the phase of my
graduation.
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TABLE OF CONTENTS
SIGNATURE PAGE……………………………………………………………………...ii
ACKNOWLEDGEMENT ................................................................................................. iii
LIST OF FIGURES .......................................................................................................... vii
ABSTRACT ...................................................................................................................... xii
Chapter 1: Introduction ........................................................................................................1
1.1 Types of FSM ................................................................................................................1
1.1.1 Mealy type FSM ..................................................................................................1
1.1.2 Moore type FSM..................................................................................................2
Chapter 2: Design approach .................................................................................................3
2.1 Algorithm and flowchart ................................................................................................4
2.1.1 Algorithm ............................................................................................................4
2.1.2 Flowchart .............................................................................................................5
2.2 GUI Modeling ................................................................................................................6
2.2.1 HDL Select ..........................................................................................................7
2.2.2 FSM Type ............................................................................................................7
2.2.3 No of inputs .........................................................................................................8
2.2.4 No of States .........................................................................................................8
2.2.5 Filename and Pathname .......................................................................................9
2.3 FSM Table .....................................................................................................................9
2.3.1 Generate FSM Table ..........................................................................................10
v
2.3.2 Generate Code ...................................................................................................11
Chapter 3: All about VBA .................................................................................................13
3.1 VBA code approach .....................................................................................................13
3.2 Sample codes ...............................................................................................................14
3.2.1 AASD_label ......................................................................................................14
3.2.2 Acq_states..........................................................................................................15
3.3 Error Checks and guidelines ........................................................................................16
3.3.1 HDL Select Error ...............................................................................................17
3.3.2 No of States Error ..............................................................................................17
3.3.3 Guidelines for FSM Table .................................................................................18
3.3.4 Reset State Error ................................................................................................18
3.3.5 Moore output mismatch error ............................................................................19
3.4 Code Comments ...........................................................................................................20
Chapter 4: HDL modeling .................................................................................................21
4.1 Introduction to HDL for FSM ......................................................................................21
4.2 VHDL code modeling ..................................................................................................22
4.3 Verilog/SystemVerilog HDL code modeling ..............................................................23
Chapter 5: Synthesis and simulation ..................................................................................25
5.1 Quartus II design Synthesis .........................................................................................25
5.2 Modelsim simulation ...................................................................................................26
5.3 Xilinx ISE design synthesis .........................................................................................27
Chapter 6: APPLICATIONS .............................................................................................30
vi
Chapter 7: CONCLUDING REMARKS ...........................................................................31
References ..........................................................................................................................32
APPENDIX A: List of HDL codes ....................................................................................33
APPENDIX B: Quartus II Synthesis reports for FSM.......................................................34
APPENDIX C: Xilinx ISE 14.7 Design Summary for FSM .............................................37
APPENDIX D: HDL Codes...............................................................................................39
vii
LIST OF FIGURES
Figure 1: Mealy FSM .......................................................................................................... 2
Figure 2: Moore FSM ......................................................................................................... 2
Figure 3: Flowchart ............................................................................................................. 6
Figure 4: FSM Core GUI .................................................................................................... 6
Figure 5: HDL Select .......................................................................................................... 7
Figure 6: FSM Type ............................................................................................................ 7
Figure 7: Number of inputs ................................................................................................. 8
Figure 8: Number of States ................................................................................................. 8
Figure 9: Filename & Pathname ......................................................................................... 9
Figure 10: Available States ............................................................................................... 10
Figure 11: FSM Table ....................................................................................................... 11
Figure 12: HDL file created successfully ......................................................................... 12
Figure 13: AASD_label .................................................................................................... 14
Figure 14: Number of states error check........................................................................... 15
Figure 15: acq_states......................................................................................................... 16
Figure 16: Available States ............................................................................................... 16
Figure 17: HDL Select Error............................................................................................. 17
viii
Figure 18: Number of States error .................................................................................... 17
Figure 19: Guidelines for FSM Table ............................................................................... 18
Figure 20: Reset State Error .............................................................................................. 19
Figure 21: Moore output error .......................................................................................... 20
Figure 22: Comment header.............................................................................................. 20
Figure 23: Comment Header for Verilog file ................................................................... 21
Figure 24: AASD VHDL Code......................................................................................... 23
Figure 25: AASD Verilog Code ....................................................................................... 24
Figure 26: Quartus II Post Fitting schematics................................................................... 25
Figure 27: Quartus II FSM State diagram......................................................................... 26
Figure 28: Modelsim simulation waveform ...................................................................... 27
Figure 29: Xilinx ISE RTL top level ................................................................................ 27
Figure 30: Footprint of FSM_MEALY_vhd15................................................................. 28
Figure 31: Gate level for LUT5 ........................................................................................ 29
Figure 32: LUT equation .................................................................................................. 29
Figure 33: Analysis and Synthesis summary FSM_MEALY_vhd15 ............................... 34
Figure 34: Analysis and Synthesis summary FSM_MEALY_sveri15 ............................. 34
Figure 35: Analysis and Synthesis summary FSM_MEALY_veri15............................... 35
Figure 36: Analysis and Synthesis summary FSM_MOORE_vhd15............................... 35
ix
Figure 37: Analysis and Synthesis summary FSM_MOORE_veri15 .............................. 36
Figure 38: Analysis and Synthesis summary FSM_MOORE_sveri15 ............................. 36
Figure 39: Design Summary FSM_MEALY_veri15 ........................................................ 37
Figure 40: Design Summary FSM_MEALY_vhd15 ........................................................ 37
Figure 41: Design Summary FSM_MEALY_veri15 ........................................................ 38
Figure 42: Design Summary FSM_MEALY_vhd15 ........................................................ 38
Figure 43: FSM_MEALY_sveri15.sv part 1 .................................................................... 39
Figure 44: FSM_MEALY_sveri15.sv part 2 .................................................................... 39
Figure 45: FSM_MEALY_sveri15.sv part 3 .................................................................... 40
Figure 46: FSM_MEALY_sveri15.sv part 4 .................................................................... 40
Figure 47: FSM_MEALY_sveri15.sv part 5 .................................................................... 41
Figure 48: FSM_MEALY_sveri15.sv part 6 .................................................................... 41
Figure 49: FSM_MEALY_sveri15.sv part 7 .................................................................... 42
Figure 50: FSM_MEALY_sveri15.sv part 8 .................................................................... 42
Figure 51: FSM_MEALY_veri15.v part 1 ....................................................................... 43
Figure 52: FSM_MEALY_veri15.v part 2 ....................................................................... 43
Figure 53: FSM_MEALY_veri15.v part 3 ....................................................................... 44
Figure 54: FSM_MEALY_veri15.v part 4 ....................................................................... 44
Figure 55: FSM_MEALY_veri15.v part 5 ....................................................................... 45
x
Figure 56: FSM_MEALY_veri15.v part 6 ....................................................................... 45
Figure 57: FSM_MEALY_veri15.v part 7 ...................................................................... 46
Figure 58: FSM_MEALY_veri15.v part 8 ....................................................................... 46
Figure 59: FSM_MEALY_vhd15.vhd part 1.................................................................... 47
Figure 60: FSM_MEALY_vhd15.vhd part 2................................................................... 47
Figure 61: FSM_MEALY_vhd15.vhd part 3.................................................................... 48
Figure 62: FSM_MEALY_vhd15.vhd part 4.................................................................... 48
Figure 63: FSM_MEALY_vhd15.vhd part 5.................................................................... 49
Figure 64: FSM_MEALY_vhd15.vhd part 6.................................................................... 49
Figure 65: FSM_MEALY_vhd15.vhd part 7.................................................................... 50
Figure 66: FSM_MEALY_vhd15.vhd part 8.................................................................... 50
Figure 67: FSM_MOORE_sveri15.sv part 1 .................................................................... 51
Figure 68: FSM_MOORE_sveri15.sv part 2 .................................................................... 51
Figure 69: FSM_MOORE_sveri15.sv part 3 .................................................................... 52
Figure 70: FSM_MOORE_sveri15.sv part 4 .................................................................... 52
Figure 71: FSM_MOORE_sveri15.sv part 5 .................................................................... 53
Figure 72: FSM_MOORE_veri15.v part 1 ....................................................................... 53
Figure 73: FSM_MOORE_veri15.v part 2 ....................................................................... 54
Figure 74: FSM_MOORE_veri15.v part 3 ....................................................................... 54
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Figure 75: FSM_MOORE_veri15.v part 4 ....................................................................... 55
Figure 76: FSM_MOORE_veri15.v part 5 ....................................................................... 55
Figure 77: FSM_MOORE_veri15.v part 6 ....................................................................... 56
Figure 78: FSM_MOORE_vhd15.vhd part 1 ................................................................... 56
Figure 79: FSM_MOORE_vhd15.vhd part 2 ................................................................... 57
Figure 80: FSM_MOORE_vhd15.vhd part 3 ................................................................... 57
Figure 81: FSM_MOORE_vhd15.vhd part 4 ................................................................... 58
Figure 82: FSM_MOORE_vhd15.vhd part 5 ................................................................... 58
Figure 83: FSM_MOORE_vhd15.vhd part 6 .................................................................. 59
Figure 84: aasd_m.sv ........................................................................................................ 59
Figure 85: aasd_m.v ......................................................................................................... 60
Figure 86: aasd_m.vhd .................................................................................................... 60
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ABSTRACT
SEQUENTIAL FSM CORE
By
Pawan Ghotikar
Master of Science in Electrical Engineering
Sequential Finite State Machine (FSM) can be defined as a logic circuit used to realize a
specific sequential task dependent behavior. There are two types of FSM namely Mealy
and Moore. Project has a GUI for the user to define specifications namely type of FSM,
number of inputs, states, type of HDL for the target device. Depending on the user
specifications a FSM table will be generated for user to fill. Using the user inputs for the
desired FSM a completely synthesizable Verilog, System Verilog or VHDL file is
generated.
The project overcomes the need to write FSM behavioral code. The aim of the project is to
take into account the user inputs in terms of number of states, number of inputs and specific
type of FSM desired and then generate respective HDL for their specific target synthesis
tool. Future scope of the project is to understand different HDL tools and also the supported
FPGAs and make this project a powerful tool to generate large FSMs for the target device.
Visual Basic for Application (VBA) is used for GUI interface and processing the user
inputs. The project serves a good purpose of automation of generating completely
synthesizable HDL files which can be used practically in any of the FSM application.
1
Chapter 1: Introduction
Electrical and electronic process controllers go through state transitions before producing
the final desired result. On understanding the process and the final upshot, different states
can be designed and modeled into electrical circuits. The electrical circuits used to control
the flow of electrical signals and hence, the state transitions are called State Machines.
Finite State machines (FSM) are the subset of state machines which have finite state
transitions for controlling the desired process. With the advent of technology and market
competition, the need of Application Specific Integrated Circuits (ASICs), Complex
Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs)
increased. Finite State Machines are modeled using Hardware Descriptive Language
(HDL) and synthesized into physical circuits on ASIC, FPGAs or CPLDs. Many of the
communication protocols, too, can be modeled into FSMs e.g.: JTAG, SPI.
1.1 Types of FSM
FSM are broadly classified into two types:
1) Mealy type FSM
2) Moore type FSM
FSM can be represented using state transition diagram and state transition table. This
project focuses on state transition table representation which is easier to understand.
1.1.1 Mealy type FSM
In Mealy type FSM, the next state (NS) of the machine depends on the current input. Output
of Mealy type FSM depends on the input and the present state (PS). Figure1 shows general
2
block diagram of Mealy type FSM. Figure 1 shows the block diagram of Mealy FSM.
Mealy FSM can have a single input or multiple inputs.
Figure 1: Mealy FSM
1.1.2 Moore type FSM
In Moore type FSM, next state (NS) of the machine depends on the current input. Output
of Moore type FSM depends only on the present state (PS) and is not affected by the input.
Figure2 shows general block diagram of Moore type FSM. Figure 2 shows the block
diagram of Moore FSM. Moore FSM can have single input or multiple inputs.
Figure 2: Moore FSM
3
Chapter 2: Design approach
FSM cores developed by most of the competitors in the market are specific to their
respective HDL synthesizing tools. Moreover, these vendors provide the structure of FSM
and not the internal state transition HDL design. The whole idea of the project is to
overcome the need to design HDL and provide the engineers with standard HDL design
code acceptable and synthesizable by most of the HDL compiling and synthesizing tools.
This eliminates the need to know the HDL compilers used specific HDL design tools like
Xilinx ISE, Altera. By decoding the specifications of the design for the user and providing
the user with completely synthesizable HDL design code saves time to model the respective
HDL design code. With a click of a GUI button, user is able to generate Verilog, System
Verilog or VHDL design code.
In the design, timestamps are provided in the comment header whenever a HDL
file is created. This helps to keep a revision check and understand when the file is created.
It also displays relevant information for the HDL such as type of FSM created and the type
of output for that FSM. It also gives information about AASD type of reset used.
One of the features it provides is an option to use some synthesis tool specific
directives like “fsm_style” (Xilinx specific) used for the target design. This type of
directive is only applicable to advanced FPGAs and hence, is in comment header. Before
using this type of directive user is provided a link to refer to serving as guidelines for using
such directives. This directive is only used by Xilinx Synthesis Technology and not by
Altera. Hence, by providing such relevant information an attempt is made in the direction
4
to allow user to use the tool for advanced FPGAs without knowing their specific feature.
This may also help in optimization of the design at the compiler level.
2.1 Algorithm and flowchart
Some of the important features which are taken into consideration are simple to understand
VBA code, covering most of the necessities for a FSM and designing a GUI model to make
it user friendly. The VBA code used for the design has comment headers wherever
necessary to help decoding the code and/or modifying for future use. Moreover, final HDL
code is modeled in a simple to understand CASE statements.
2.1.1 Algorithm
The main idea for the algorithm is to go through two processes mainly to generate a FSM
table and then create a HDL file. The steps involved are as follows:
Get user specifications namely type of HDL, type of FSM, number of inputs and
number of states from the user.
Prompt user for any missing parameters missed by user.
Generate FSM table for the desired number of states and inputs.
Provide user with the available states.
Get a reset state from the user
Let the user fill the table as per requirement.
Once the table is filled, prompt user for errors, if any.
Get filename and file path from the user for saving the HDL file to be created.
If the details provided by user are sufficient then prompt user to generate the HDL
file.
5
Provide user with completely synthesizable HDL file at the location specified by
user.
Prompt the user if the HDL file has been created successfully or not.
2.1.2 Flowchart
Following figure shows a flowchart used for complete process beginning from the user
inputs to creating a completely synthesizable HDL code. As we see, it has two processes.
One of them is creating a FSM table and the second is to create a HDL file on interpreting
the user inputs from the FSM table. This modular approach helps in extensive two step
error checks for user specifications needed for FSM table and then specifications entered
in FSM table for HDL code.
START
Get user inputs
Check errors if any
Prompt user for
generating FSM table--> button input
Check for errors if any
Prompt user for creating HDL file -->
button input
6
2.2 GUI Modeling
In GUI modeling, the focus is to keep it simple yet covering all the basic required
specifications. Figure 3 shows the GUI. The basic required specification tabs are HDL
select, FSM type, No. of inputs, Filename and Pathname. The combined user input for all
the required specifications is used to model the HDL code which gets saved in the
Pathname specified by the user.
Figure 4: FSM Core GUI
Create HDL file using VBA
STOP
Figure 3: Flowchart
7
2.2.1 HDL Select
Hardware Descriptive Language (HDL) as the name suggests is a language to describe
hardware. HDL is a language used to model different hardware circuit models mostly
digital logic circuits. ‘HDL Select’ is a dropdown list which gives the user options to select
from popular HDL namely Verilog, System Verilog and VHDL. Figure 4 shows the
dropdown list of HDL Select
Figure 5: HDL Select
2.2.2 FSM Type
‘FSM Type’ is a dropdown list giving the user option to select desired FSM type namely
Mealy and Moore. Mealy and Moore designs chosen for the project have registered output
and are designed to have asynchronous assertion and synchronous deassertion for reset.
The reset signal modeled is active low. Figure 5 shows FSM Type.
Figure 6: FSM Type
8
2.2.3 No of inputs
FSM can have single line or multiple line inputs. To provide user with both the features,
the project prototype is designed for 1 or 2 input FSM covering both single and multiple
line inputs. Figure 6 shows No of inputs drop down list providing user options to select one
of the two input/inputs desired for FSM.
Figure 7: Number of inputs
2.2.4 No of States
‘No of states’ is a dropdown list which allows user to select 3 to 15 number of states for
the target FSM. The project can be extended to have more number of states but with some
modifications in the VBA code used for writing the HDL files for the FSM. Figure 7 shows
‘No of States’.
Figure 8: Number of States
9
2.2.5 Filename and Pathname
Filename provides flexibility to the user to provide a suitable filename for the FSM. In
order to create FSM and save it in a location for the user, user needs to specify the Pathname
for the HDL file to be created. VBA code is used to save the respective HDL file in the
Pathname location specified by the user. Figure 8 shows the Filename and Pathname
Textboxes.
Figure 9: Filename & Pathname
2.3 FSM Table
Once the user fills out the FSM Core template, user is prompted to generate the FSM table.
The requirements for FSM table is to use name of the states from the available states only.
For instance, number of states entered by user will produce corresponding alphabets in the
available states textbox. Let’s look at the following examples to have a better
understanding of how it works.
e.g1: if the user enters 3, the available states will be A,B,C.
e.g2: if the user enters 5, the available states will be A,B,C,D,E
Figure 9 shows an example of 15 No of States and corresponding available states
10
Figure 10: Available States
2.3.1 Generate FSM Table
‘Generate FSM Table’ button is used to generate FSM Table for the user to fill. User is
assumed to have know-how of State transition table in order to fill the generated FSM table.
User can generate either single input or two inputs FSM table with 3 to 15 states. User is
also required to specify a reset state for the FSM to get to this respective state on system
reset. This allows the FSM to begin from a known state once reset. Figure 10 shows an
example of 15 states, 2 input Moore FSM with ‘A’ as reset state.
In the Figure PS stands for Present State and NS stands for Next State of FSM. As
Figure 10 is for 2 input FSM the combinations 00, 01, 11, 10 are listed as primary inputs
and PS in alphabetical sequence. User needs to fill the NS and outputs for the corresponding
input. For Moore the outputs are not dependent on NS but PS. This has been taken care by
the error checks in the VBA code which prompts the user for errors, if any while filling up
the FSM Core completely.
11
Figure 11: FSM Table
2.3.2 Generate Code
Generate Code button is used to generate the desired HDL code. On click of this button, it
performs following functions:
Checks the validity of the states and outputs entered by the user and prompts the
user for errors, if any.
After successful error check it creates a file with the filename and in the filepath
specified by the user.
After creating the file, the code prints the desired HDL code in the respective file
and saves it.
12
On completion of the task the code is automated to provide user if the HDL file is
created or not.
Figure 12: HDL file created successfully
13
Chapter 3: All about VBA
Visual Basic for Applications is used to model the GUI and assign functions to the
respective GUI. It has variety of pick and place GUI form controls like command buttons,
list box, combo box, text box, message box. These controls can be interactively used to
give a feel of hardware user interface but embedded in software.
With added features of XML the form can be uploaded on internet and can be accessed
from any place having internet access.
The XML documents can be password protected as well. This feature adds security
to qualified projects. Moreover, VBA programming can be used to interact with hardware
around and can be used for process control as well. The programming for VBA is similar
to C/C++ programming. VBA is one of the subsets for object oriented programming (a.k.a.
OOP).
3.1 VBA code approach
The approach for VBA code is to focus on keeping it simple and easy to understand. The
idea is to scan the input parameters from different form controls and use these for making
respective HDL file. Following shows two flow diagrams
1. To generate FSM table
Scan FSM parameters Process data Generate FSM Table
2. To generate HDL File
Scan FSM Table inputs Process data Generate HDL File
14
3.2 Sample codes
3.2.1 AASD_label
Object Oriented Programming is mainly used to assign functionality to different form
objects. It can also be used to print data into files. The project mainly focuses on decoding
the user input and modeling the desired result into a HDL file. A sample code of one such
function is shown in figure 11. The function “AASD_label” is used to interpret the user’s
HDL selection, Filename and filepath. On interpreting the respective specified selections
and inputs by the user, the code creates a HDL file with its appropriate extension (.v, .vhd,
.sv) and stores the file created in the location specified by the user.
Figure 13: AASD_label
15
3.2.2 Acq_states
The function “acq_states” is a private function having Boolean as a return value. Figure 13
shows acq_states function. It checks the user input of number of states. If it finds it blank
then a message box pops up asking the user to select desired number of states. This error
check code is as shown in following figure 12.
Figure 14: Number of states error check
If the code finds a number in the “No_of_states” combobox then it generates an array of
alphabets in its respective alphabetical order and displays the available states (Figure 14)
for the user to use in FSM table generated.
16
Figure 15: acq_states
Figure 16: Available States
3.3 Error Checks and guidelines
For any project to be error free, there has to be error checks in place. Taking into
consideration all the possibilities of errors, this project prompts the user for errors, if any.
For instance, user can forget to mention some of the parameters and press “Generate FSM
17
Table”. For such mistakes there are error message boxes to prompt the user about specific
error.
3.3.1 HDL Select Error
If the user forgets to select HDL and presses “Generate FSM Table”, an error message box
for the respective error pops up as shown in figure 15. As we can see the error message
prompts the user to select the HDL
Figure 17: HDL Select Error
3.3.2 No of States Error
If the user forgets to select no of states for the desired FSM and presses “Generate FSM
Table”, an error message box pops up as shown in figure 16. From the error message it is
clear that the GUI prompts the user to select no of states.
Figure 18: Number of States error
18
3.3.3 Guidelines for FSM Table
Once the user fills in all the necessary information required for generating the FSM table
and presses the “Generate FSM Table” the code is equipped with giving user guidelines
for filling up the FSM Table. Figure 17 shows the message box for these guidelines.
Figure 19: Guidelines for FSM Table
3.3.4 Reset State Error
If the user happen to press “Generate Code” button without entering reset state, the code
gives an error message box to the user asking to enter a reset state from the available states.
The figure 18 shows the reset state error message box. The code halts till the user enters all
the required information.
19
Figure 20: Reset State Error
3.3.5 Moore output mismatch error
Unlike Mealy, the outputs for Moore FSM are PS dependent only and input independent.
The automated code will give an error if it finds any output mismatches for Moore machine
for the same PS. Figure 19 shows an error occurring in Moore FSM table for output
mismatch for A as the present state. The project is powerful enough to give some guidelines
to the user as which row has the error. For this example, as there is a mismatch of output
for the row of PS=A, it shows error in row 22 of respective GUI sheet. It is seen from the
figure that with PS=A and under input = 01, output printed in the table is ‘0’ whereas, under
input= 00, 11, 10 the output printed in the table is ‘1’. Hence, the code generates an error
saying “Output Mismatch for Moore in the row22”. Moreover, it also gives a warning that
outputs for Moore type FSM are PS dependent only.
20
Figure 21: Moore output error
3.4 Code Comments
The code has lot of comments for letting other users understand each section and make it
easier to modify, if needed, in future. Having enough comments in code is recommended
and has been adopted widely in the companies. Figure 22 shows a comment header for
AASD module instantiation in HDL file. It helps understand the user to interpret the code
in a better way and also may help to modify it, if needed
Figure 22: Comment header
21
Chapter 4: HDL modeling
4.1 Introduction to HDL for FSM
Hardware Descriptive Language (HDL) is a language used to realize a logical circuit using
different synthesizing tools like Altera, Xilinx and Cadence. FSM can be modeled using
HDL. The most widely used HDLs are VHDL, Verilog and System Verilog. Great
emphasis is given to structure different processes for VHDL and likewise, always blocks
in Verilog and System Verilog. Every file created has a timestamp with relevant
information such as type of FSM, AASD information and special features, if any.
Figure 23: Comment Header for Verilog file
Figure 20 shows an example of Verilog file comment header. Similarly, VHDL and System
Verilog files have comment headers too. It is seen from the above example that it also gives
additional information for using tool specific directives like “fsm_style”. The use of such
directives is limited to Xilinx tools and that too for advanced FPGAs only. If the user wants
to use such directives, user has to refer to the link given in the comment header.
22
Scope of the project is to target such technologies of the future and use these to expand this
project into an automated HDL tool to model designs like FSM for any control machines
with a click of a button. As a prototype project focuses on modeling just FSM.
4.2 VHDL code modeling
In order to define a structure which can be recursively generated and generalized for the
ease of software usage is the focal point for modeling HDL. One of the methods used to
design VHDL is to identify positioning of different directives, attributes in the file.
Structure of any VHDL file follows a particular format which made it easy to position
different directives. The sequence of definition is as follows:
LIBRARY which always is at the top of the code
USE directive for IEEE standards
ENTITY with the PORT definition
ARCHITECTURE behavior
SIGNAL definitions
COMPONENT declaration
Main structure of the VHDL code
PROCESS
END PROCESS
END behavior
A sample code for AASD VHDL code model is shown in figure 21 as a reference. The
code uses the above guidelines for its structure and modeling.
23
Figure 24: AASD VHDL Code
4.3 Verilog/SystemVerilog HDL code modeling
In Verilog/System Verilog HDL, “timescale” directive is defined which is used for
simulation of the unit under test (uut). Like VHDL, Verilog/System Verilog also can be
modeled using a standard code structure. The sequence of definition of different code
directives/compiler parameters are as follows:
24
● `timescale definition used for simulation
● Module definition – for inputs, outputs, clock, reset
● reg and wire definitions used within the module, if any.
● Always blocks for defining behavioral Verilog/system Verilog model
● Endmodule directive for allowing compiler to decode end of module definition
Figure 25: AASD Verilog Code
25
Chapter 5: Synthesis and simulation
HDL design can be realized using different synthesizing tools. Before design is
implemented, it needs simulation and verification. Many synthesis tools have their own
editor, simulation tools built-in. Out of the many Synthesis and simulation tools, popular
in the market are Xilinx and Altera and hence, used for this project. For Xilinx Integrated
Synthesis Environment (ISE) for design synthesis and ISim for design simulation are used.
For altera quartus II for design synthesis and Modelsim design simulation are used.
5.1 Quartus II design Synthesis
Quartus II design synthesis tool is used to model Mealy FSM with 15 states. Figure 20
shows the RTL post-synthesis schematics for FSM_MEALY_vhd15. The elaboration of
the state transition is shown in figure 21 in Quartus II FSM state diagram.
Figure 26: Quartus II Post Fitting schematics
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Figure 27: Quartus II FSM State diagram
5.2 Modelsim simulation
Modelsim is a simulation tool mainly used for HDL design simulation. It has features like
force to a constant value, force a clock which is useful if one lacks know-how of developing
a test fixture for their HDL design. Figure 22 shows the simulation waveform for
FSM_MEALY_vhd15. It shows the state transitions on the positive edge of the clock at
respective inputs. For example, with stateA as PS and input “01” on the rising edge of clock
machine goes to NS stateG.
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Figure 28: Modelsim simulation waveform
5.3 Xilinx ISE design synthesis
Xilinx ISE is used for design synthesis and realize a HDL model. For ease of comparison,
same VHDL design of FSM_MEALY_vhd15 is synthesized using Xilinx ISE. Following
figure 23 shows the RTL top level for the respective HDL design. Xilinx ISE gives a better
gate level design for FSM schematics
Figure 29: Xilinx ISE RTL top level
Scoping further, if we double-click the top-level module in the schematics window, it
shows the internal footprint of the design. Figure 30 shows the footprint of
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FSM_MEALY_vhd15 design synthesized using Xilinx ISE 14.7. It is seen that the internal
structure is made up of different look up tables (LUT), buffers and flip-flops.
Figure 30: Footprint of FSM_MEALY_vhd15
One can still scope deeper in the design to understand the gate-level structure. For instance,
if we double-click the LUT highlighted, we get the underlying schematics shown in figure
31. Different LUTs have different structures and gates depending on driving inputs for that
LUT. As compared to Altera, Xilinx tools give better understanding of the modular level
LUTs as it gives an option to look at the respective truth table for that LUT. If we look at
the LUT gate level schematic shown in figure 31, we see that it has five inputs. Hence, the
name LUT5.
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Figure 31: Gate level for LUT5
To understand the way this LUT is derived, Xilinx also gives an option for equation of
LUT. To see the equation of that LUT we can press the equation tab. Figure 32 shows
equation for one such LUT with 6 inputs.
Figure 32: LUT equation
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Chapter 6: APPLICATIONS
Finite State Machine finds many applications in process control systems. Some of the
applications of the state machines are as follows:
JTAG
Vending machines
Propulsion Controls of Hybrid vehicles
ALU Controller
PROM data flow controller for FPGA
Traffic Lights
Synchronous Communication protocols like I2C, SPI.
Pattern search
Image processing
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Chapter 7: CONCLUDING REMARKS
The project was started with an aim to facilitate end user with completely synthesizable
FSM HDL code as per the requirement. HDL code files created by the project are
synthesized and simulated using Xilinx ISE and Altera’s Quartus II tools. The limitations
of Xilinx ISE 14.7 is that it cannot be used for synthesizing System Verilog HDL. The
synthesis reports help one understand that the codes are synthesizable and the schematics
give the mapped logical circuit. The whole process gave me a better understanding of HDL
code synthesis, simulation and verification. The project can be extended further by making
provisions for more number of inputs and states. Moreover, VBA code can be made
flexible to allow user defined states and inputs. This project has a good scope to be a
complete synthesis tool for any type of FSM.
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References
1. ECE 623 Notes by Dr. Ramin Roosta, CSU, Northridge
2. ECE 420 Notes by Dr. George Law, CSU, Northridge
3. ECE 524 Notes by Dr. Shahnam Mirzaei, CSU, Northridge
4. ECE526 Notes by Dr. Ronald Mehler, CSU, Northridge
5. http://web.cs.ucdavis.edu/~rogaway/classes/120/spring13/eric-applications.pdf
Retrieved March, 2015.
6. http://asic-world.com/examples/verilog/index.html Retrieved March, 2015.
7. http://www.csun.edu/edaasic/roosta/VHDL_Examples.pdf Retrieved March, 2015.
8. http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/
Retrieved March, 2015.
9. http://www.xilinx.com/itp/xilinx10/isehelp/pp_db_xst_hdl_synthesis_options.htm
Retrieved March, 2015.
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APPENDIX A: List of HDL codes
FSM_MEALY_vhd15.vhd
FSM_MOORE_vhd15.vhd
FSM_MEALY_veri15.v
FSM_MOORE_ veri15.v
FSM_MEALY_ sveri15. sv
FSM_MOORE_ sveri15.sv
AASD_vhd.vhd
AASD_veri.v
AASD_sveri.sv
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APPENDIX B: Quartus II Synthesis reports for FSM
Figure 33: Analysis and Synthesis summary FSM_MEALY_vhd15
Figure 34: Analysis and Synthesis summary FSM_MEALY_sveri15
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Figure 35: Analysis and Synthesis summary FSM_MEALY_veri15
Figure 36: Analysis and Synthesis summary FSM_MOORE_vhd15
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Figure 37: Analysis and Synthesis summary FSM_MOORE_veri15
Figure 38: Analysis and Synthesis summary FSM_MOORE_sveri15
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APPENDIX C: Xilinx ISE 14.7 Design Summary for FSM
Figure 39: Design Summary FSM_MEALY_veri15
Figure 40: Design Summary FSM_MEALY_vhd15
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Figure 41: Design Summary FSM_MEALY_veri15
Figure 42: Design Summary FSM_MEALY_vhd15
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APPENDIX D: HDL Codes
Figure 43: FSM_MEALY_sveri15.sv part 1
Figure 44: FSM_MEALY_sveri15.sv part 2
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Figure 45: FSM_MEALY_sveri15.sv part 3
Figure 46: FSM_MEALY_sveri15.sv part 4
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Figure 47: FSM_MEALY_sveri15.sv part 5
Figure 48: FSM_MEALY_sveri15.sv part 6
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Figure 49: FSM_MEALY_sveri15.sv part 7
Figure 50: FSM_MEALY_sveri15.sv part 8
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Figure 51: FSM_MEALY_veri15.v part 1
Figure 52: FSM_MEALY_veri15.v part 2
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Figure 53: FSM_MEALY_veri15.v part 3
Figure 54: FSM_MEALY_veri15.v part 4
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Figure 55: FSM_MEALY_veri15.v part 5
Figure 56: FSM_MEALY_veri15.v part 6
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Figure 57: FSM_MEALY_veri15.v part 7
Figure 58: FSM_MEALY_veri15.v part 8
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Figure 59: FSM_MEALY_vhd15.vhd part 1
Figure 60: FSM_MEALY_vhd15.vhd part 2
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Figure 61: FSM_MEALY_vhd15.vhd part 3
Figure 62: FSM_MEALY_vhd15.vhd part 4
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Figure 63: FSM_MEALY_vhd15.vhd part 5
Figure 64: FSM_MEALY_vhd15.vhd part 6
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Figure 65: FSM_MEALY_vhd15.vhd part 7
Figure 66: FSM_MEALY_vhd15.vhd part 8
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Figure 67: FSM_MOORE_sveri15.sv part 1
Figure 68: FSM_MOORE_sveri15.sv part 2
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Figure 69: FSM_MOORE_sveri15.sv part 3
Figure 70: FSM_MOORE_sveri15.sv part 4
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Figure 71: FSM_MOORE_sveri15.sv part 5
Figure 72: FSM_MOORE_veri15.v part 1
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Figure 73: FSM_MOORE_veri15.v part 2
Figure 74: FSM_MOORE_veri15.v part 3
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Figure 75: FSM_MOORE_veri15.v part 4
Figure 76: FSM_MOORE_veri15.v part 5
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Figure 77: FSM_MOORE_veri15.v part 6
Figure 78: FSM_MOORE_vhd15.vhd part 1
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Figure 79: FSM_MOORE_vhd15.vhd part 2
Figure 80: FSM_MOORE_vhd15.vhd part 3
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Figure 81: FSM_MOORE_vhd15.vhd part 4
Figure 82: FSM_MOORE_vhd15.vhd part 5
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Figure 83: FSM_MOORE_vhd15.vhd part 6
Figure 84: aasd_m.sv
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Figure 85: aasd_m.v
Figure 86: aasd_m.vhd