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Business Models to Support Supply Chain
Readiness for Mainstream 2.5D & 3D Technologies
GSA 3D IC Working Group Meeting
San Jose, CA
Rich Rice Sr. Vice President ASE Group Jan 23rd, 2013
Presented by
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Logic, Memory & Analog Enjoy The Wave
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Logic 3D SoC/SiP including interposer chips, APU, GPU, CPU, MCU, FPGA, and covering integration with wide IO memory
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Agenda
Critical enabling process technologies Roles Business model options 2015 outlook
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Critical enabling process technologies
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Heterogeneous Integration 3D + 2.5D evolution
IC
IC
IC
IC
Wirebond BGA FC BGA
Stacked Die PoP EPS 2.5D IC (Si Interposer)
3D IC direct die stack
FO-WLP
MEMs & Wireless
FO-WLP SiP
Time
WLCSP
Heterogeneous Integration Assembly + Substrate
Heterogeneous Integration IC + Assembly
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Si Interposer Enabling Chip Integration
+
Alternative SoC Solution (Allow IC designer to partition chips and re-organize in Si interposer platform)
Provide platform for heterogeneous chip integration (IPD, MEMS, Sensor…)
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Middle (MEOL) and Backend Process Flow
TSV wafer
1. Via-first TSV Wafer (w/ Cu pillar bump)
2. Mount TSV wafer onto Carrier
3. Backside Process
Wafer Carrier
* 6. TSV die TC Bonding to Substrate
7. Top die TC Bonding to TSV wafer
9. Marking, Ball Mount 8. Molding (option)
4. Release TSV Wafer from Carrier
5. TSV Wafer Dicing
Wafer Carrier Wafer Carrier
MEOL Process
Backend Process
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What does Middle-End (MEOL) Mean?
Start with a thick wafer with TSVs (either Via first, or via middle) Wafer thinning / reveal TSV on backside TSV Surface conditioning Capping RDL Repassivation Bumping (or interconnect to substrate, or other wafer)
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RDL Ni
Si
Passivation
RDL Cu
TSV
RDL Ni
Si
Passivation
RDL Cu
TSV
TSV Wafer
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- 50 um via/ 30um core
- Full-fill and lining available
Wafer Thinning / Handling through MEOL process
- 50 um thick
Double Side Photo-Litho Via Formation
- 15um/ 15um L/S qualified
- 10um/10um L/S pro’type
- 2L metal layer
Microbump
- 20um size/ 40um pitch
- AR > 2.5
- Direct bump on Al pad capability
40 um pitch Microbump
Critical Wafer Level Capabilities
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Critical Assembly Capabilities
C2C/C2W Bonding
• Thermo-compression bonding • High precision FC bonding (3um, 12” wafer)
Encapsulation
• CUF (10um~25um gap)
• NCP
• NCF
Thin Wafer Handling in Assembly Bonding chip-to-substrate
• 50um chip-to-substrate • Cu pillar bump – 80um/40um
• Solder bump – 150um
• Au stud bump – 60um
40um pitch Cu pillar
Solder bump (100um)
F2F w/ wire bond
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Product Type Criteria 200 mm Wafer Readiness 300 mm Wafer Readiness
Y2009 Y2012 Y2009 Y2012
Wafer Thinning / Grinding 50 µm
Via Last
Via Etching 20 ~ 50 µm, AR 10
Via Isolation 20 ~ 50 µm, AR 10
Via Seedlayer 20 ~ 50 µm, AR 10
Via First
Via Etching 5 ~ 10 µm, AR 10
Via Isolation 5 ~ 10 µm, AR 10 Via Seedlayer 5 ~ 10 µm, AR 10
Thin Wafer Handling 50 µm With Carrier With Carrier
Via Surface Finish No Cu Dishing
Re-distribution (Double Sides) -
Micro-bumping 30 µm Pitch
TSV Wafer Probing & Testing 30 µm Pitch 50 um Now 50 um Now
Wafer Singulation -
C2C/C2W Bonding Solder / Micro Bump
Assembly -
Final Test -
Ready for Mass Production Ready for Qualification No Solution Yet
Ready for Prototyping
Source: 2009 Data from ASE’s Ho Ming Tong in SEMICON Taiwan
Industry 2.5D / 3D IC Production Tooling Readiness
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Roles
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Typical Roles System Integrator / Product Owner
Procures all silicon components Designs package, or co-designs with assembly provider Provides test program and initial hardware - responsible for test coverage
and overall product functionality Procures final manufactured module
IC Foundry / Interposer Foundry Receives IC design from product owner Delivers sorted die, KGD, or interposer to product owner / assembly
provider Reliability level is known, FA is done at die level for returns
Assembly / Test provider Receives all die, package config info, testing programs from product owner Deploys assembly and test manufacturing infrastructure with suitable
technologies, interconnect yields and reliability Delivers finished goods to product owner
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Responsibilities of OSAT Design
Provides package design rules with necessary technology solutions aligned to manufacturing
Executes package co-design with customer Consults on applicable test flow and hardware requirements
Manufacturing Provides appropriate technology solution and manufacturing capacity
infrastructure at bump, assembly and test Procures necessary manufacturing materials Inspects consigned materials (die) to agreed upon specifications
Yield and Reliability Maximizes interconnect yields through assembly and test Reports all yield information to customer (product owner) Ensures interconnect reliability to meet the customer requirements Conducts package level FA, reports results to product owner
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Business Models
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3D IC Ecosystem Models
Logic IC Fab with via formation MEOL CoC
Assembly
Memory
Final Test
• Foundry w/via OSAT MEOL + backend
• Foundry w/via + MEOL OSAT backend
• IDM / Foundry Captive Turnkey
• ALL 3 FLOWS WILL LIKELY DEPLOY
Memory supplied by product owner
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MEOL CoW / CoC Assembly
Memory
Final Test
• Foundry IC Interposer foundry OSAT MEOL
• Foundry IC Interposer foundry OSAT ASSY
• Foundry IC + Interposer OSAT MEOL
• Foundry IC + Interposer w/MEOL OSAT ASSY
• IDM / Foundry Captive Turnkey
• MOST OR ALL FLOWS WILL LIKELY DEPLOY
All components supplied by product owner
RF Chip 1 RF Chip 2
Silicon Interposer
BGA Substrate
Chip 1 Chip 2
Analog
Sensors
Logic IC
2.5D IC Ecosystem Models
Interposer Fab with via formation
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What will the 2.5D and 3D packaging landscape look like in 2015 and beyond?
System Integrators Product Architect / Owner Performance and cost is aligned with market requirements Die supply agreements for multi die products are in place
Fabless Semi and OEM system integrator OSAT ecosystem model supports heterogeneous and multi foundry
products (high mix / volume) Foundry supply model supports homogeneous and like foundry multi-
die products (low mix) Foundry directed outsource to OSAT possible
IDM Few IDM’s with internal capability, but large volume / high value
products (low mix) IDM directed outsource to OSAT possible
Interposer suppliers will have emerged Logic foundries Interposer foundries
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Survival of the Fittest
“Market” Always Gives a “Fair Test” to Select The One to Survive!
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Thank you
www.aseglobal.com