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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 0 of 56 IMSE-Des ign Group
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odriguez-Vzquez
IMSE
Avda. Reina Mercedes s/n,
41012-Sevilla, SPAIN
FAX:
Instituto de Microelectrnica de Sevilla(IMSE-CNM-CSIC)
E-mail: [email protected]
Phone: +34 95 505 6666/6669
+34 95 505 6686
Camino de los Descubrimientos s/n,41092-Sevilla, SPAIN
Escuela Superior de Ingenieros
Universidad de SevillaDpto. Electrnica y Electromagnetismo
Phone: +34 954487377
IMSE
Band-Pass Sigma-Delta Modulators:
Angel Rod rguez-Vzquez and JosM. de la Rosa
Avda. Reina Mercedes s/n,
41012-Sevilla, SPAIN
FAX:
Instituto de Microelectrnica de Sevilla(IMSE-CNM-CSIC)
E-mail: [email protected]
Phone: +34 95 505 6666/6669
+34 95 505 6686
Camino de los Descubrimientos s/n,41092-Sevilla, SPAIN
Escuela Superior de Ingenieros
Universidad de SevillaDpto. Electrnica y Electromagnetismo
Phone: +34 954487377
Princ iples, Arch itectures and Circuits
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 1 of 56 IMSE-Des ign Group
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Out l i ne
Motivation and Applications
Basic Concepts
Architectures
Circuit Errors
State-of-the-Art
TEXTJ.M. de la Rosa, B. Prez-Verd and A. Rodrguez-Vzquez, Systematic Design of CMOS Switched-
Cur rent BandPass Sigma-Delta M odulators. ISBN 0-7923-7678-1, Kluwer Academics Pub. 2002.
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 2 of 56 IMSE-Design Group
Motivations
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odriguez-Vzquez
Dig i ta l Wire less Communicat ion s Scenar io
Digital Cellular Phones(GSM, CDMA, UMTS-2000) Traffic Telematic Applications
(GPS)
Digital Radio Receivers(Software controlled broadcast AM, FM radios)
Telemetry Instrumentation(Ultrasounds, narrowband-source generators...)
Wireless LANsDigital RF Communication
(PDAs, others...)
Portable Devices
RF, IF(BANDPASS )
ANALOG-TO-DIGITALCONVERTERS
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 3 of 56 IMSE-Design Group
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Receiver Arch i tec tures I
An alog (Superh eterodyn e) Receiver
Digi ta l Receiver
RF Bandpass Filter
LO1
Common Tuning
Antenna
LNA
IFBandpass Filter
LO2
RF Section IFSection Dem. Section
DemodulatorLNA
Processing in the analog domain (Filtering, mixing, demod.) Limited functions: voice telephony, paging.(AMPS, NMT,...)
First-Generation
AntennaADC
&
DEMODULATION
DIGITAL SIGNAL PROCESSING(DSP)
ANALOG SIGNAL PROCESSING(ASP)
Most functions in the digital domain: programmability, multi-stand-ard,...
New functions: ISDN-compatible data, call forwarding, short mes-saging, software controlled receivers (in radio app.), etc...
Continuous technology scaling will allow one-chip receiversSecond-Generation(GSM, CDMA,...)
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 4 of 56 IMSE-Design Group
Motivations
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Receiver Arc hi tectu res I I: Digi ta l RF Receivers
Superheterodyne Receiver
Direct-Convers ion Receiver
IF-Convers io n Receiver
RF Bandpass FilterLO1
Common Tunning
AntennaLNA
IF Bandpass FilterLO2
RF IF Baseband
Lowpass
ADCDSPLNA
Section Section
Two much analog cir-
cuitry: High-Q High-F BPfilters
Not appropriate for one-
Better suited for integrated
receivers
Sensitive to RFmixer errors:
offset, flicker noise,...
RFADCs required
RFBandpass FilterLO1
Common Tuning
AntennaLNA
RF Baseband
Lowpass
ADC
DSP
Section
RFBandpass FilterLO1
Common Tuning
AntennaLNA DSP
RF IF
IF(Bandpass)ADC
IFmixing realized in thedigital domain
An IFADC is required
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 5 of 56 IMSE-Design Group
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Two Ap proach es to IF Dig i t i zat ion
Analog Domain Digital Domain
Analog quadrature mixer
(= I/Q mismatch, 1/fnoise, offset)
Two lowpass ADCs needed
LP Filter
LP Filter
2
I data
Q data
IF
LP Filter
LP Filter
2
I data
Q data
2fIFt( )cos
2fIF
n Ts
( )cos 1 0 1 0 1 0 , , , ,, ,=
fI F fs 4=
signal
Lowpass
ADC
Lowpass
ADC
IF
ADC
(Bandpass)
Digital quadrature mixer
One IF(bandpass) ADC
Digital channel selec-tion, gain control...
fIF fs 4=Digital mixing simplifiedfo r
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 6 of 56 IMSE-Design Group
Motivations
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Interest of B andPass Co nv erters for IF Digi t izat ion
0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0
Normalized frequency (to fs)
PSDof the digitized signal (dB)
Signal BandBandPass Converters:
Quantization noise has to be smallonly in the band of interest
Oversampling reduces the quantiza-tion noise within the band
Noise-shaping further reduces the
noise within the band
Nyquist-Rate Data Converters
Quantization noise has to bereduced within the whole Nyquistband
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Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 7 of 56 IMSE-Design Group
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Sampl ing o f BandPass Signals
fS2fS1
> PE2PE1
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BandPass Error Feedback and Noise Shaping
Y z( )X z( )
2Lth
BP Filter
DAC+
+G
Eq z( )fn
As for LPM, something more than just oversampling is needed for practical BPMs
Y z( ) STF
z( )X z( ) NTF
z( )Eqz( )+=
In-band:
Out-of-band: for stability
for causality
NTFz( )
NTFf fnlim 0=
NTF 1,6 2
Stability conditions are not preserved
Generalized Transformation
Re(z)
Im(z)
UnityCircle
zn e2 fnTs
=
NTFBandpass
1 2 2fn
fs
( )z 1 z 2+cos
1 2 fn fs( )z 1
cos
----------------------------------------------------------------------
L
=
A hit t
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Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 25 of 56 IMSE-Design Group
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Opt imized Syn thes is of STF(z) and NTF(z)
Direct synthesis of and
Optimize poles and zeroes according to a given specification
can be designed to perform a bandpass function
Architecture (interpolative) is more sensitive to mismatch
ST F z( ) NT F z( )
ST F
z( )
z 1
1 z 1
------------------ z 1
1 z 1
------------------
R1b1
a1
a2
b2
z 1
1 z 1
------------------ z 1
1 z 1
------------------
R2b3
a3
a4
b4DAC
x
y
0 0.1 0.2 0.3 0.4 0.5-80
-70
-60
-50
-40
-30
-20
-10
0
Frequency / Sampling Frequency
+
12
21
Ca0Ci0
Cx1
+
12
21
Ca1Ci1
Cx2
+
12
21
Ca2Ci2
Cx3
+
12
Ca3Ci3
+
1
2+
IN
2
1Cr1
Cb0 Cb1 2
1Cr1
Cb2 Cb3
2
1
2
1
OUT
Vref
[Jantzi , 1994]
A hit t Q d t B d M d l t I
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Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 26 of 56 IMSE-Design Group
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Quadrature B andpass Modula tors I
RFBandpass Filter
LOCommon Tuning
AntennaLNA
RFBandpass Filter
LOCommon Tuning
AntennaLNA
BPADC
BPADC
BPADC
QuadratureMixer
DSP
I DATA
Q DATA
RFBandpass Filter
LOCommon Tuning
AntennaLNA Quadrature
MixerDSP
I DATA
Q DATA
QuadratureBPADC
I
Q
I
Q
Digital QuadratureMixer & DSP
RFStage IF Stage
Image spectral componentscorrupt the signal unless a
Quadrature mixer solves in
One quadrature modulatordirectly digitizes I and Q compo-
nents
narrow-band high-QRFfilteris used.
part this problem, but twomodulators are required.
1
2
3
[Jantzi, 1997]
Architect res Q d t B d M d l t II
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Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 27 of 56 IMSE-Design Group
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Quadrature Band pass Modu lators II
+
-
xQ
DAC
fn
Complex Filter
+
-x
I
DAC
yQ
yI
NTF
1 z2
+
2= vs N
TF1 jz
1
4
=Example
-0.5 -0.3 -0.1 0.1 0.3 0.5-100
-80
-60
-40
-20
0
20
40NTFdB
Re(z)
Im(z)
zn
e
j2---
=
zn
e
j
2---
=
Unity
Circle
Normalized frequency to fs
Quadrature bandpass modulators
Use complex bandpass filters
has complex-coefficients (not
symmetric with respect to DC)
Can place L zeroes at fnwithout plac-
ing any zero at fn
NTF
z( )
Architectures Comple Fi lters for Q adrat re BP Mod lators
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Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 28 of 56 IMSE-Design Group
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Complex Fi lters for Quadrature BP Modulators
+
-
xiRe
HR e
z( )
HR e
z( )
HI m
z( )
HI m
z( )
+-
xiIm
xo
Re
xo
Im
XoRe
HRe
z( )XiR e
HIm
z( )XiIm
z( )=
XoIm HRe z( )XiIm HIm z( )XiRe z( )+=
Xo z( ) XoRe z( ) j XoIm+=
Usual l y rea l ized throug h cross-cou p led rea l -f i l ters
+x
iRe
z 1
1 z 1
-----------------
+
+xiIm
z 1
1 z 1
-----------------
+
xo
Re
xo
Im
b
b
+
-
a 1( )
a 1( )
Example
H z( ) 1
z a j b +( )-----------------------------=
Two integrators to make a complex pole
A complex Lth
-order BP M uses 2Linte-grators but has 2Lzeroes atNT F
z( ) fn
Architectures Fourth Order Quadrature BP Mod u la to r
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Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 29 of 56 IMSE-Design Group
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+
Cd
Ci
Cc
12 2 1
+
Cd
Ci
Cc
12 2
1
xiRe
xiIm
xo
Re
xo
Im
Fourth -Order Quadrature BP Mod u la to r
[Jantzi, 1997]
Undesired Image due to mismatch between real and imaginary channels
It can be partially cancelled by placing one zero at the image frequency
b1
a1
a2
b2
b3
a3 a4
b4
DAC
x
y1
z p2
-------------
1
z p3
-------------
1
z p4
-------------
Complex
integrator
pn 1 dn jcn+ +=
H z( ) 1z p
n
---------------=
1
z p1-------------
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0
Normalized frequency tofs
Mag. (dB)
Image band zero
complexsignal path
Complex SC Integrator
Architectures N Path A rch i tec tures I
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Architectures
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N-Path A rch i tec tures I
H zp
( )1
1
H zp
( )2
2
H zp
( )N
N
X z( ) Y z( )
1
2
N
Tp
Y z( )X z( )------------ H zp( )
zp zN
=
=
H z( )z
2
1 z 2
+
-----------------zp
1
1 zp1
+
-----------------
zp z2
=
= =
+
+
2
zp
1
1 zp
1
----------------------
zp
1
1 zp
1
----------------------
2fs
2----
nTs
cos n( )cos 1 1 1 1, ,,= =
Alternative 2-path reson ators
Each path clocked at 1/Nthe overall rate
[Ong, 1998]
Opamp bandwidth requirements can be relaxed using N-path filters[Gregorian, 1986]
Architectures Examples o f N-Path BP Ms I
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Architectures
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Examples o f N-Path BP Ms I
0,4zp
1
1 zp1
+--------------------
zp1
1 zp1
+--------------------
+
+
+
+
0,5
DAC
1 1
0,4zp
1
1 zp1
+--------------------
zp1
1 zp1
+--------------------
+
+
+
+
0,5
DAC
2 2
X z( )
2 11+
vref2
+
vout+
+
1+
vin
11
2
2 11
21
12
2
12
[Ong, 1997]
A 2-path 4th-order modulator
Architectures Examples o f N-Path BP Ms II
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Architectures
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Examples o f N Path BP Ms II
bzp1
1 zp1
+--------------------
azp1
1 zp1
+
--------------------+
+
+
+
4 bit DAC
1
X z( )
Quantizerbzp
1
1 zp1
+
--------------------
1,-1,1,-1...
+
+
1 bit DAC
bzp1
1 zp1
+
--------------------azp
1
1 zp1
+--------------------
+
+
+
+
4 bit DAC
2Quantizer
bzp1
1 zp1
+--------------------
1,-1,1,-1...
+
+
1 bit DAC
I DATA
Q DATA
[Tabatabaei , 1999]
A 2-path 6th-order modulator (dual quantizer, multibit)
Image components due to path mismatch
Architectures Cont inuous-Time Arch i tec tu res I
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Architectures
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Cont inuous Time Arch i tec tu res I
D A C s( )f
nH s( )
fs
x1
t( )
E z( ) 0=
yn
y t( ) x1 n,
X1 z( )Y z( )-------------- Z L
1DAC s ( )H s( )[ ]
t n Ts=Z DAC ( )h t ( ) d
t n Ts=
= =
Equivalent discrete-time system
Continuous-Time BandPass Modulators
Speed enhancement
Implicit anti-alias filter
Sensitive to clock jitter
Excess modulator loop delay
+
-
x yn
DAC s( )
fnH s( )
fs
x1
t( ) x1
nTs( )
Internal sampling
Architectures Cont inu ous -Time Arch i tec tures II
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Cont inu ous Time Arch i tec tures II
Synthesis process
Select an appropriate DT architecture
Apply a DT-to-CT transformation
Impulse invariant transformation
DAC s( ) esp 1Ts
esp 2Ts
s-------------------------------------------=DAC t ( )
1 , p1Ts t p2Ts
0 , otherwise
=
Equivalent CTand DTloop filter transfer function for a BPM.
Non-Return-to-Zero (NRZ),
Return-to-Zero (RZ),
Half-delay Return-to-Zero (HRZ),
2nd
order
DAC t ( ) H z( ) H s( )
p1 0 p2, 1= =z
11 z
1( )
1 z 2
+
------------------------------
o
s
s2 o
2+
-------------------p1 0 p2, 1 2= =1
2
2-------
z 1 22
------- z 2
1 z 2
+
----------------------------------------------------
p1 1 2 p2, 0= =
2
2------- z
11
2
2-------
z 2
1 z 2
+
----------------------------------------------------
[Gao, 1998]
Circuit Errors Main Lim i tat ions of (LDI) Reson ators
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( )
2 1
12Ibias Ibias
1 2
22Ibias 2Ibias Ibias
1
1 : 1 1 1 : 1 -2 1: :
ii io
:
1io1 -2io
Current mirror mismatching
Finite Output/Input
Conductance ratio
Charge injection
Settling error
Non-linearities
Swi tched-Current
+
11 2
C1
C2+
vin +
C2
2
1
1
2
2C12
1
-1
+
vout
Capacitor mismatchingFinite opamp DC gain
Settling error
Clock jitter Thermal Noise
Non-linearities
1
C1 21
2
Switched-Capaci tor
Circuit Errors Fin i te A vin SC; gand qin SI - I
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v g q
2 1
1
go go
id1 id2
go2
2Ibias Ibias
ii io
+
22
1
C2
+
vin
C1
12+
vout
+
vaAvva
+
-vout
SC LDI integrator with finite opamp DC gain (Av)
SI LDI integrator with:
and charge injection error (q)finiteoutput-input conductance ratio error (g)
+
-
s
Ms
M
COLCOL
q q
CgsVgs
Hi n t z( ) 1 ( )z 1 2
1 1 ( ) z 1-------------------------------
1
A v------- 1
C1
C2
-------+
1
A v-------
C1
C2
-------
Hi n t z( ) 1
g
q( )z 1 2
1 1 2g
2q
+( )[ ] z 1-----------------------------------------------------------
g
2go
gi n----------
q
Vqo f fqVT( )
Vg s
VT( ) Q
----------------------------------------- 2q
vq
qi n j
Cg s-------------- V
qo f fqvg sM
=
similar effect
Circuit Errors Fin i te A vin SC; gand qin SI - II
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g q
1
2F 2FB gFgFB
, for SI circuits+ + +
2 4, for SC circuits
=
2
4g
4q
gF
gFB
for SI circuits,+ + +
2 for SC circuits,=
F FB,
ro n
go F FB ,
= gF FB,
go F FB ,
gm
( ) 1 F FB,
( )=
Different effect at the resonator level
NT F
z( ) 1 1z
11
2( )z 2+ +[ ]
2
Noise transfer function o f a 4t h-order BP modulator
0.24 0.25 0.26-100
-80
-60
-40
-20
NTF(dB)
Frequency/Sampling Freq.
0.24 0.25 0.26-100
-80
-60
-40
-20
Frequency/Sampling Freq.
NTF(dB)
Hres z( ) 1
1( )z 1
2z 2+
1 1z 1 1 2( )z
2+ +----------------------------------------------------------
LDI reson . tran. funct io n
0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0IdealReal
PSD(dB)
Freq./Sampling Freq.
0 0.1 0.2 0.3 0.4 0.5-120
-100-80
-60
-40
-20
0
IdealReal
Freq./Sampling Freq.
Effect on the resonant frequency
Effect on the Q-factor
PSD(dB)
Hr e s z( ) 1
1( )z 1
2z 2+
1 1z 1 1
2( )z 2+ +
----------------------------------------------------------
Circuit Errors Fin i te A vin SC; gand qin SI - III
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0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
Model
Simulation
Model
Simulation
Av
60dB=A
v30dB=
Model
Simulation
0.2 0.25 0.3
-120
-100
-80
-60
-40
-20
0
0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
Model
Simulation
g
0,1%= g 1%=
Normalized frequency tofs
Magnitude (dB) Magnitude (dB)
Normalized frequency to fs
Normalized frequency to fs
Magnitude (dB) Magnitude (dB)
Normalized frequency to fs
Circuit Errors Mismatch Gain Error
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1
b1
iiio1 2
1 : k
Ibias kIbias
2 V, T2
1V,
T1
+
22
1
C2
+
vin
C1
12+
vout
m i s
-------
VT
vg s VT( )Q
---------------------------------
kC
1
C2
-------= m is
C1
C1
-----------C
2
C2
-----------=
Hr e s z( ) z 1
1 m is
z 1 z 2+ +---------------------------------------------
0.225 0.25 0.275
-50
0
Magnitude (dB)
Normalized frequency to fs
fn
m i s
M
-----
BW
2---------
Notch f requency er ror
MonteCarlo Simulation
Gain factor mismatchare mapped into:
Capacitor ratiomismatch for SC circuits
Transistor ratiomismatch for SI circuits
In Lowpass, mismatch error is criti-cal in cascade architectures
In Bandpass, mismatch error affects
also to the notch frequency position
Circuit Errors Linear Set t ling I
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+
22
1
C2
+
vin
C1
12
+
vout
+
va
gmva+
voutCo
go
SC LDI integrator with linear settling error
SI memory cell with linear settling error
Vbias Ibias
1 2
1M
ii io
gmQvgsgoQ
Cgs
+
vgs
1
1 2ii io
+
vds
+
vgs
+
vdsids
MB
Hi n t z( ) gi1 s( )z
1 2
1 z 1
----------------------------------
s eTs 2
= Ceq gm=
Ceq C1 Co 1C
1
C2
-------+
+=
s eTs 2
= Cg s gm Q=
Hi n t
z( )z
1 21 s( ) 1 sz
1( )
1 z 1
( ) 1 s2z
1( )
--------------------------------------------------------------
Circuit Errors Lin ear Sett l ing II
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LDI resonator trans fer fun ct ion
Notch frequency error
0.225 0.250 0.275-120
-100
-80
-60
-40
Normalized Frequency (Freq./fs)
s=0.1%s=0.5%s=1.0%
Effect of son NTFin SI circuits
0.225 0.25 0.275-120
-100
-80
-60
-40
Normalized Frequency (Freq./fs)
s=0.1%s=0.5%s=1.0%
Effect of son NTFin SC circuits
NTF(dB) NTF(dB)
fn 4sM
-----
BW2
---------
1
4s, for both SC and SI circuits{=
2
4s for SI circuits,
0 for SC circuits,
=Hr e s z( )
1 1
( )z 1 2z 2+
1 1z 1 1
2( )z 2+ +
----------------------------------------------------------
Circuit Errors Summary of Effect of Lin ear Errors on a 4th-Order Arc hitectu re I
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2
LDIX
1 1 2
RSY
LDI
2
+
2
LDI
1
LDI
2
+
0.5
+
HalfDelay
io+
DA CHalfDelay
NT F
z( ) 1 1z
11
2( )z 2+ +[ ]
2
loss of attenuation in the signal band
shifts of the Notch Frequency:
2
0
1
0 fn
1
M
-----
BW
2---------
Switched-Capacitor Switched-Current
Finite opamp DC gain
Incomplete Settling error
Mismatch gain error
Mismatch gain error
Incomplete settling error
Finite opamp DC gain Incomplete settlingCharge injection error
Finite output-input conductance ratio error
1
0
2
0
Circuit Errors Summary of Effect of L inear Errors on a 4th-Order Arc hitectu re II
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Quantization Noise Power(4th-order Modulator)
PSD signal
PQ
4
2
60M5-------------- 1
10
3
------ 3
1
2
2
2+
M
-----
2 5 1
2
2
2+
2
M
-----
4+ +=
8 16 32 64 128 256 512102420
40
60
80
100
Half-scaleSNR
(dB)
M
max=0.1%
max=0.5%max=1%
max(%)0.01 0.1 140
60
80
100Half-scale SNR(dB)
M=256M=128
M=64
Theory
Simulations
Assuming all errors to be below an error bound max
Circuit Errors Non- l inear Behaviour : Harmonic Distor t ion I
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gelRodriguez-Vzquez Main non- l inear error mechanism s in SC circui ts:
Capaci tor non- l inear i ty
+
C v( ) C
nom 1 v v
2+ + +( )=v
Non- l inear opamp DC-gain A v v( ) A 0 1 1v 2v2
+ + +( )=
+
22
1
C2
+
vi
C1
12+
vout
vo n, vo n 1, C1
C2
------- vi n, vi n, vo n,+
A0
---------------------------- 1 1vo n, 2 vo n,
2( )+
vo n, vo n 1,C
1nom
C2nom
----------------- vi n 1, 1
2---vi n 1,+
2--- vo n 1,
2vo n,
2( )+ +
Circuit Errors Non- l inear Behaviou r : Harmonic Disto r t ion I I
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gelRodriguez-Vzquez Ibias
io
2
1
1
+
ii
vgs
io n,
Io f f
1 1
( ) ii n 1 2,
k
k 2=
ii n 1 2,k
=
Non- l inear (s tat i c ) mode l of the mem ory c e l l
io n,
1 21
( ) io n 1,
1 1
( ) ii n 1 2,
31
1( )
-------------------- io n 1,3 i
o n,3+
Ful ly-d i f ferent ia l integr ators
EXAMPLE: g
1gout Vgs VT( )Q
Ibias
-------------------------------------------
2gout Vgs VT( )Q
2 Ibias
2-------------------------------------------
33 g
ou tV
gsV
T( )
Q
8 Ibias3
-------------------------------------------------
Main n on- l inear errors in SI circui ts:
Source of non-linearity:
Output-input conductance ratio error (g(%) charge
injection error (q(%) settling error (s(%) mismatch error
gm ii n( ) gmQ
1ii n
Ib i a s
------------+=
Circuit Errors Non- l inear Behaviou r : Harmon ic Distor t ion I II
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2
LDIX
1 1 2
RSY
LDI
2
+
2
LDI
1
LDI
2
+
0.5
+
HalfDelay
+
AH 3,
DA CHalfDelay
0.22 0.23 0.24 0.25 0.26 0.27 0.28-140
-120
-100
-80
-60
-40
-20
0
Magnitude (dB)
Frequency/Sampling Frequency
Reson 1 non-linear
Reson 2 non-linear HD3
fi fs 4 fi'=( )
fi
fs 4 3fi'+
Analysis of the effect of nonlinearity on the resonator is required
App roaches to ana lyse d is to r t ion :
HD3 at the modulator input is
equal to HD3at the modulator output
The contribution of Resonator 2is attenuated bythe gain of Resonator 1in the signal bandwidth
Typical figures:
ST Fz( ) 1=
HD3
AH 3,
X------------- IM
3 3HD
3
Circuit Errors
EXAMPLE ff t f l i f l l d i f f t i l SI BP MNon- l inear Behavio ur : Harmon ic Distor t ion IV
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IM3
3HD3
123X
21 16
1( ) 1 12fi'Ts+( )=
HD3
43X
21 16
1( ) 1 12fi'Ts+( ) c
AH 3,
3X
3
2 1 21
( )-------------------------- 1 12fi'Ts+( )
EXAMPLE, ef fect of non - l inear errors o n ful ly-d i f ferent ia l SI BP Ms
0.22 0.23 0.24 0.25 0.26 0.27 0.28-100
-80
-60
-40
-20
0
Frequency/Sampling Frequency
IM3 =-43dB
Magnitude (dB)
IM3 =-54dB
0.1 1-80
-70
-60
-50
-40
3
pp m A( ) 2
IM3 dB( )
CalculatedSimulated,Simulated,
IDA C 50A=IDA C 25A=
Circuit Errors Thermal Noise
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2
X
1 1
Y
2
+
212
+
0.5
+
HalfDelay
+
DA CHalfDelay
vn1 vn2 vn3 vn4
Pt h
PSDi n
f( ) fd
fs 4 Bw 2
fs 4 Bw 2+
=
vin
0.23 0.24 0.25 0.26 0.28-100
-80
-60
-40
-20
0
Magnitude (dB)
Normalized frequency to fs
Consideringvn2
Consideringvn1Considerat ions for Analysis :Contributions of 3rd and 4th integrators to theinput noise are attenuated by the first resonator
Second integrator contributes to the input equiva-lent noise as:
vi n2
vn12
1 z 1
2vn2
2+
fn
fs
4= 1 z 1 2 2
Circuit Errors
U t i ti i th li ti b d ll d (t) ( T )
Clock J i t ter
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Uncertainties in the sampling time can be modelled as
a (white) noise,jitter noise, with in-band noise power,
In BP Ms, is a substantial fraction of
(Typically )
PJ
f( ) A2
2-------
2fi
t( )2
M------------------------=
fi
fs
fi fs 4=
Increase with the
sampling frequency
clkx (t) x (nTs)
clk
x n Ts +( ) x n Ts( ) 2fiA 2fin Ts( )cos
Sinusoidal inputs
[Tao, 1999]
Cont inuo us-t ime bandpass modulators :
More sensible to clock jitter
DACs clock jitter-induce errors with the input signal,
NRZ DAC
RZ DAC
PJf( )
tfs( )2
M----------------------
2
c fifs
( )sin( )2----------------------------------------= 0 4
PJ f( ) 8
t
fs
( )2
M---------------------
2
c fi fs( )sin( )2----------------------------------------=
State-of-the-Art State-of- the-Ar t on CMOS BP Ms I
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Author DR(bit)fs
(MHz)fn (MHz) Bw(kHz)
Power Cons.
(mW)Process Architecture
Switched-Capacitor[Jant93] 10.2 1.825 0.455 8 210 3mm DP / 5V 4th, Optim. NTF[Long93] 15 7.2 1.8 30 -- 1mm DP / 5V 4th, LP-to-BP[Song95]
9 8 2 30 0.8 2mm DP / 3.3V 4th, LP-to-BP[Hair96] 11.7 13 3.25 200 14.4 0.8mm DP / 3V 4-2, LP-to-BP[Andr96] 8 8 2 64 8 0.5mm DP / 3.3V 6th, LP-to-BP[Liu97] 11.8 0.827 0.413 2 -- 2mm DP / 5V 4th, Optim. NTF[Corm97] 9.5 1.25 0.25-.375 6.25 -- 2mm DP / 5V 4th, LP-to-BP[Ong97] 12.2 80 20 200 72 0.6mm SP 3.3V 4th, LP-to-BP[Jant97] 10.8 10 3.75 200 130 0.8mm SP / 5V 4th, Quadrature[Andr98] 9.2 4 1 200 19 0.5mm DP / 3V 3th-3bit, Optim. NTF[Baza98] 6.7 40 20 1250 65 0.5mm DP / 5V 2nd, LP-to-BP[Chua98] 13 0.5 0.125 0.5 -- 2mm DP / 5V 6th, Optim.NTF[Park99] 12.2 20 5 200 180 0.65mm SP / 4V 4th, LP-to-BP
[Taba99] 13 80 20 1250 90 0.25mm DP / 2.5V 6th, LP-to-BP[Toni99] 12.7 42.8 10.7 200 80 0.35mm SP / 3.3V 6th,Optim. NTF[Baza99] 9.4 68 17 1250 48 0.6mm DP / 3V 4-4, LP-to-BP[Taba00] 12 64 16 2000 110 0.25mm SP / 2.5V 6th, 2-path, IF-to-BB[Cusi00] 12 37.05 10.7 200 116 0.35mm SP/ 3.3V 6th, Optim. NTF[Cheu01] 6.7 42.8 10.7 200 12 0.35mm SP/ 1V 2nd, LP-to-BP[Burg01] 8.6 184.32 138.24 3840 13.5 0.25mm SP/ 2.5V 3rd, IF-to-BB
14 104 78 200 11.5Continuous Time
[Enge99] 11.7 40 9.15 200 60 0.5mm DP / 5V 6th, Optim. NTF
10.8 80 10.7 200[Tao99] 8 400 100 200 330 0.35mm SP/ 3.3V 2nd, IF-to-BB[Bree00] 13 13 13 100 1.8 0.35mm SP/2.5V 2nd, IF-to-BB[Zwan00] 16 21.07 10.7 9 8 0.25mm SP/2.5V 5th, IF-to-BB
13.3 200 11
State-of-the-Art State-of -the-Ar t o n CMOS BP Ms II
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Statistics of the State-of-the-Art CMOS BPMs
Synthesis method: (~50%)
Passband location: (~80%)
Circuit technique: Switched-Capacitor(~80%)
Technology: CMOS (double-poly)(~54%)
z 1
z 2
fn fs 4=
Comparison figure of LowPass modulators,
is not appropriate ( is missing)
FOM
FOMPowerW( )
2Resolution bit( )
fd Samples s( )---------------------------------------------------------------------------------------- 10
12=
fn
4
6
8
10
12
14
16
18
1 10 100 1000 10000
Bw (kHz)
DR(bits
SC LP-to-BP
SC OPTIM. NTF
SC IF-to-BB
SC Quadrature
CT OPTIM. NTF
CT IF-to-BB
0
50
100
150
200
250
300
350
1 10 100 1000 10000
Bw (kHz)
PowerCons.(mW)
SC LP-to-BP
SC OPTIM. NTF
SC IF-to-BB
SC Quadrature
CT OPTIM. NTF
CT IF-to-BB
State-of-the-Art State-of- the-Art o n CMOS BP Ms III
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1,E-06
1,E-05
1,E-04
1,E-03
1,E-02
1,E-01
1,E+00
1 10 100 1000 10000
Bw (kHz)
FOM
BP
SC LP-to-BP
SC OPTIM. NTF
SC IF-to-BBSC Quadrature
CT OPTIM. NTF
CT IF-to-BB
AM, IS-54 FM, GSM, PCS
UMTSIS-95BLUETOOTH
FOMBP
Power (mW)
2DR b i t s ( )
fn
MHz( )----------------------------------------------------------=
State-of-the-Art SI Ms vs. State-of- the-Art Ms I
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1,00
10,00
100,00
1000,00
10000,00
0,0001 0,01 1 100
DOR (MS/s)
FO
M1(pJ)
SC
SI
SI lowp ass modulators obtain wors e performance than SC ones
State-of-the-Art SI Ms vs. State-of- the-Ar t Ms II
Best com par ison is obtained in the bandp ass case
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1,E-04
1,E-03
1,E-02
1,E-01
1,E+00
1 10 100 1000 10000
Bw (kHz)
FO
MBP
SC LP-to-BP
SC OPTIM. NTF
SC Quadrature
CT OPTIM. NTF
SI
Best com par ison is obtained in the bandp ass case
[de la Rosa, 2002]
State-of-the-Art References I
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ngelRodriguez-Vzquez [Andr96] E. Andr, D. Morche, F. Balestro and P. Senn: A 2-pathModulator for Bandpass Application, Proc. of IEEE-CAS
Workshop on Analog and Mixed IC Design, pp. 87-91, September 1996.
[Andr98] E. Andr, G. Martel, D. Morche, and P. Senn: A Bandpass A/D Converter and its I/Q Demodulator for Integrated
Receivers, Proceedings of the 24th European Solid-Stated Circuits Conference, ESSCIRC98, pp. 416-419, Sep-
tember 1998.
[Baza98] S. Bazarjani, W.M. Snelgrove: A 160MHz Fourth-Order Double-Sampled SC Bandpass Sigma-Delta Modulator,IEEE Trans. Circuits and Systems-II, Vol. 45, pp. 547-555, May 1998.
[Baza99] S. Bazarjani, S. Younis, J. Goldblatt, D. Butterfield, G. McAllister, S. Ciccarelli: An 85MHz IF Bandpass Sigma-Delta
Modulator for CDMA Receivers, Proceedings of the 25th European Solid-Stated Circuits Conference, ESSCIRC99,
pp. 266-269 , September 1999.
[Burg01] T. Burger and Q. Huang: A 13.5-mW 185-Msample/s DS Modulator for UMTS/GSM Dual-Standard IF Reception,
IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1868-1878, December 2001.
[Bree00] L. J. Breems, E. J. van der Zwan and J.H. Huijsing: A 1.8-mW CMOS Modulator with Integrated Mixer for A/DConversion of IF Signals, IEEE Journal of Solid-State Circuits, Vol. 35 pp. 468-475, April 2000.
[Cheu01] V. S. L. Cheung, H.C. Luong and W.H. Ki: A 1V 10.7MHz Switched-Opamp Bandpass Modulator Using Double-
Sampling Finite-Gain Compensation Technique, 2001 IEEE Int. Solid-State Circuit Conference, pp. 52-53, Feb.2001.
[Chua98] S. Chuang, H. Liu, X. Yu, T.L. Sculley, R. H. Bamberger: Design and Implementation of Bandpass Delta-Sigma
Modulators Using Half-Delay Integrators, IEEE Trans. Circuits and Systems-II, Vol. 45, pp. 535-546, May 1998.
[Corm97] R. F. Cormier, T. L. Sculley, and R. H. Bamberger: A Fourth Order Bandpass Delta-Sigma Modulator with Digitally
Programmable Passband Frequency, Int. Journal of Analog Integrated Circuits and Signal Processing, pp. 217-229,
1997.
[Cusi00] P. Cusitano, F. Stefani and A. Baschirotto, A 73dB SFDR 10.7MHz 3.3V CMOS Bandpass Modulator sampled at37.05MHz", Proc. of the 26th European Solid-State Cicuits Conference, pp. 80-83, September 2000.
[Enge99] J. van Engelen, R. van de Plasshe, E. Stikvoort, A. Venes: A Sixth-Order Continuous-Time Bandpass Sigma-Delta
Modulator For Digital Radio IF, IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1753-1764, December 1999.
[Hair96] A. Hairapetian: An 81-MHz IF Receiver in CMOS, IEEE Journal of Solid-State Circuits, pp. 1981-1986, December
1996.
State-of-the-Art References II
[Jant93] S A Jantzi M Snelgrove and P F Ferguson: A fourth-order Bandpass sigma-delta Modulator IEEE J Solid-State
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[Jant93] S.A. Jantzi, M. Snelgrove and P.F. Ferguson: A fourth-order Bandpass sigma-delta Modulator , IEEE J. Solid-State
Circuits, Vol. 28, pp. 282-291, March 1993.
[Jant97] S.A. Jantzi, K. W. Martin, and A. S. Sedra: Quadrature Bandpass Modulation for Digital Radio, IEEE J. Solid-StateCircuits, Vol. 32, pp. 1935-1949, December 1997.
[Long93]L. Longo and H. Bor-Rong: A 15b 30kHz Bandpass Sigma-Delta Modulator, Proceeding 1993 IEEE Int. Solid-State
Circuit Conference, pp. 226-227, March 1993.[Liu97] H. Liu, X. Yu, T. Sculley and R. H. Bamberger: A Fourth Order Bandpass Delta-Sigma A/D Converter with Input Mod-
ulation Network and Digitally Programmable Passband, Proc. 1997 IEEE Int. Symp. Circuits and System, pp. 385-388,
May 1997.
[Ong97] A.K. Ong and B.A. Wooley: A Two-Path Bandpass Modulator for Digital IF Extraction at 20MHz, IEEE Journal ofSolid-State Circuit, Vol. 32, pp. 1920-1933, December 1997.
[Park99] J. Park, E. Joe, M. Choe, B. Song: A 5-MHz IF Digital FM Demodulator, IEEE Journal of Solid-State Circuit, Vol. 34,
pp. 3-11, January 1999.
[Song95]B.S. Song: A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps, IEEE Journal of
Solid-Stated Circuits, Vol. 25, pp. 1309-1315, December 1995.
[Taba99]A. Tabatabaei, B. Wooley: A Wideband Bandpass Sigma-Delta Modulator for Wireless Applications, IEEE Int. Symp.
on VLSI Circuits, pp. 91-92, 1999.
[Taba00]A. Tabatabaei and B. Wooley: A Two-path Bandpass Sigma-Delta Modulator with Extended Noise Shaping, IEEE J.
Solid State Circuits, Vol. 35, pp. 1799-1809, December 2000.
[Tao99] H. Tao, J.M. Khoury: A 400-MS/s Frequency Translating Bandpass Sigma-Delta Modulator, IEEE J. Solid State Cir-
cuits, Vol. 34, pp. 1741-1752, December 1999.
[Toni99] D. Tonietto, P. Cusinato, F. Stefani, A. Baschirotto: A 3.3V CMOS 10.7MHz 6th-order bandpass Modulator with78dB Dynamic Range, Proceedings of the 25th European Solid-Stated Circuits Conference, ESSCIRC99, pp. 78-81,
September 1999.
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