![Page 1: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/1.jpg)
Prepared by:Rathod Gaurang
ME1212, EC
BCD counter with mode control & parallel load capability
09 August 2012 [email protected]
![Page 2: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/2.jpg)
BASIC BLOCK DIAGRAM
![Page 3: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/3.jpg)
BCD COUNTER USING MODE CONTROL
LOAD
MODE
CLOCK
RESET
INPUTS
OUTPUT
![Page 4: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/4.jpg)
USING BEHAVIORAL METHOD
![Page 5: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/5.jpg)
VHDL CODE
![Page 6: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/6.jpg)
• entity hb is• Port ( in1 : in STD_LOGIC_vector(3 downto 0); -- load inputs• out1 : out STD_LOGIC_vector(3 downto 0); -- counter output • clk : in STD_LOGIC; -- clock input• ld1 : in STD_LOGIC; -- load control input• mode : in STD_LOGIC; -- mode control input : '1' for up and '0' for down count• clr : in std_logic); -- reset (clear) input : active high• end hb;
• architecture Behavioral of hb is• begin• process(in1,mode,ld1,clr,clk)• variable t: std_logic_vector(3 downto 0) :="0000"; --temperary variable that store count• begin• if ( clk' event and clk = '1') then -- for rising clock edge trigger•• if(clr)='1' then t:="0000"; -- reset the count to zero• • elsif (ld1 and not clr) = '1' then t := in1; --load the count• • elsif (mode and not ld1 and not clr) = '1' then t:=t+1; --for up count• if (t="1010") then t:="0000"; end if;• • elsif (not mode and not ld1 and not clr) = '1' then t:=t-1; --for down count• if(t="1111") then t:="1001"; end if;• end if; • end if; • out1 <= t; -- data store in temperary variable is given to outputs• end process;• end Behavioral;
![Page 7: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/7.jpg)
SIMULATION
WAVEFORM
![Page 8: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/8.jpg)
![Page 9: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/9.jpg)
RTL SCHEMATIC
![Page 10: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/10.jpg)
![Page 11: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/11.jpg)
USING
DATA FLOW
METHOD
![Page 12: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/12.jpg)
VHDL CODE
![Page 13: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/13.jpg)
entity ctr_df is Port ( mode : in STD_LOGIC; -- mode control input: 1 for up & 0 for down counter in1 : in STD_LOGIC_VECTOR (03 downto 0); -- parallel load input out1 : out STD_LOGIC_VECTOR (03 downto 0); -- counter output ld1 : in STD_LOGIC; --parallel load control bit clr : in STD_LOGIC; -- reset bit clk : in STD_LOGIC); --clock inputend ctr_df;architecture Behavioral of ctr_df issignal temp : std_logic_vector(3 downto 0) := "0000"; begintemp <= "0000" when ( clr = '1') else – reset
in1 when (clr = '0' and ld1 = '1' and clk = '1') else -- load input-- up count"0001" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0000") else "0010" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0001") else "0011" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0010") else "0100" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0011") else "0101" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0100") else "0110" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0101") else "0111" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0110") else "1000" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "0111") else "1001" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "1000") else "0000" after 200 ns when (clr = '0' and ld1 = '0' and mode = '1' and temp = "1001") else
![Page 14: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/14.jpg)
-- down counter
"1001" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0000") else
"1000" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "1001") else
"0111" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "1000") else
"0110" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0111") else
"0101" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0110") else
"0100" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0101") else
"0011" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0100") else
"0010" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0011") else
"0001" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0010") else
"0000" after 200 ns when (clr = '0' and ld1 = '0' and mode = '0' and temp = "0001") else
temp after 200 ms;out1 <= temp; --give outputend Behavioral;
![Page 15: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/15.jpg)
SIMULATION
WAVEFORM
![Page 16: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/16.jpg)
1
CLK
![Page 17: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/17.jpg)
RTL SCHEMATIC
![Page 18: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/18.jpg)
1
CLK
![Page 19: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/19.jpg)
BASIC BLOCK DIAGRAM
![Page 20: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/20.jpg)
1
CLK
![Page 21: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/21.jpg)
VHDL CODE
![Page 22: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/22.jpg)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;
entity countstruct is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; M : in STD_LOGIC;
count: out STD_LOGIC_VECTOR (3 downto 0)); end countstruct;
architecture Structural of countstruct iscomponent or_3
port ( a : in std_logic; b : in std_logic;
c : in std_logic; q : out std_logic);
end component;
component or_4port ( a : in std_logic; b : in std_logic;
c : in std_logic; d : in std_logic;
q : out std_logic);end component;
component tffport ( clk : in std_logic; rst : in std_logic; data : in std_logic;
q : out std_logic);end component;
![Page 23: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/23.jpg)
signal o1,o2,o3,Iinv0,Iinv1,Iinv2,Iinv3,Minv,n1,n2,n3,n4,m1,m2,m3,v1,v2,v3: std_logic;signal Q : STD_LOGIC_VECTOR (3 downto 0):="0000";
beginIinv0 <= not Q(0);Iinv1 <= not Q(1);Iinv2 <= not Q(2);Iinv3 <= not Q(3);Minv <= not M;
n1 <=Q(3) and Iinv0 and Minv;n2 <=Iinv3 and Q(0) and M;n3 <=Q(1) and Iinv0 and Minv;n4 <=(Q(2) and Iinv0 and Minv);m1 <=(Q(2) and Iinv1 and Iinv0 and Minv);m2 <=(Q(3) and Iinv0 and Minv);m3 <=(Q(1) and Q(0) and M);v1 <=(Iinv2 and Iinv1 and Iinv0 and Minv);v2 <=(Q(3) and Q(0) and M);v3 <=(Q(2) and Q(1) and Q(0) and M);
U1 : or_4 port map (n1,n2,n3,n4,o1);U2 : or_3 port map (m1,m2,m3,o2);U3 : or_3 port map (v1,v2,v3,o3);U4 : tff port map (clock,reset,'1',Q(0));U5 : tff port map (clock,reset,o1,Q(1));U6 : tff port map (clock,reset,o2,Q(2));U7 : tff port map (clock,reset,o3,Q(3));
count <= Q ;
end Structural;
![Page 24: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/24.jpg)
RTL SCHEMATIC
![Page 25: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/25.jpg)
![Page 26: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/26.jpg)
![Page 27: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/27.jpg)
![Page 28: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/28.jpg)
APPLICATIONS OF COUNTER
![Page 29: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/29.jpg)
Many applications use counters
Digital Clocks Automobile Parking Control Parallel-to-Serial Data Conversion A/D Converters Frequency Meters/Counters Signal Generators Microprocessors
![Page 30: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/30.jpg)
UP-DOWN COUNTER APPLICATION AS A SEMI-AUTOMATED PARKING LOT
GATE
![Page 31: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/31.jpg)
WHEN A CAR APPROACHES THE ENTER GATE ON THE RIGHT, THE DRIVER PUSHES A BUTTON TO
DISCHARGE THE TICKET, AND THE GATE OPENS UNTIL THE CAR PASSES
![Page 32: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/32.jpg)
WHEN THE ENTER GATE COMES FULLY DOWN, IT CLOSES A LIMIT SWITCH THAT CAUSES THE PLC
COUNTERS TO INCREMENT
![Page 33: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/33.jpg)
TO EXIT THE PARKING AREA,DRIVER PRESENTS A TICKET TO THE CASHIER AT THE WINDOW. AFTER
PAYMENT,THE EXIT GATE IS OPENED UNTIL THE CAR PASSES.
![Page 34: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/34.jpg)
WHEN THE EXIT GATE COMES FULLY DOWN,IT CLOSES THE LIMIT SWITCH THAT CAUSES THE PLC
COUNTERS TO DECREMENT
![Page 35: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/35.jpg)
CAPACITY OF PARKING LOT IS 100 CARS
![Page 36: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/36.jpg)
WHEN THE COUNT IS BETWEEN 0 AND 99, THE VACANCY LIGHT TURNS ON
![Page 37: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/37.jpg)
WHEN THE 100TH CAR ENTERS,PLC COUNTERS INCREMENT,TURNING OFF THE VACANCY LIGHT AND
ILLUMINATING THE FULL LIGHT
![Page 38: Bcd counter with mode control & parallel load capability](https://reader031.vdocuments.us/reader031/viewer/2022032117/55c3c935bb61eb5e398b45c7/html5/thumbnails/38.jpg)
THANK YOU