•VLSI Design I; A. Milenkovic •1
CPE/EE 427, CPE 527 VLSI Design I
L02: Design Metrics & IC Manufacturing
Department of Electrical and Computer Engineering University of Alabama in Huntsville
Aleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F
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Fundamental Design Metrics
• Functionality• Cost
– NRE (fixed) costs - design effort– RE (variable) costs - cost of parts, assembly, test
• Reliability, robustness– Noise margins– Noise immunity
• Performance– Speed (delay)– Power consumption; energy
• Time-to-market
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Cost of Integrated Circuits• NRE (non-recurring engineering) costs
– Fixed cost to produce the design• design effort• design verification effort• mask generation
– Influenced by the design complexity and designer productivity– More pronounced for small volume products
• Recurring costs – proportional to product volume– silicon processing
• also proportional to chip area– assembly (packaging)– test
VolumecostFixedICpercostVariableICperCost +=
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NRE Cost is Increasing
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Cost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢¢--perper--transistortransistor
Fabrication capital cost per transistor (Moore’s law)
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Silicon Wafer
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
•VLSI Design I; A. Milenkovic •2
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Recurring Costs
yieldtestFinalcostPackagingcostTestingcostDiecostVariable ++
=
yieldDiewaferperDieswaferofCostdieofCost×
=
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Dies per Wafer
areaDie2diameterWaferπ
areaDie)diameter/2(WaferπwaferperDies
2
×
×−
×=
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Yield
α
αareaDieareaunitperDefects1yieldWaferyieldDie
−
⎟⎠⎞
⎜⎝⎛ ×+×=
α is approximately 3
4area) (die cost die f=
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Examples of Cost Metrics (1994)
$4179%402961.5$15000.803Pentium
$27213%482561.6$17000.703Super SPARC
$14919%532341.2$15000.703DEC Alpha
$7327%661961.0$13000.803HP PA 7100
$5328%1151211.3$17000.804PowerPC 601
$1254%181811.0$12000.803486DX2$471%360431.0$9000.902386DX
Die cost
YieldDies/wafer
Area (mm2)
Defects/cm2
Wafer cost
Line width
Metal layers
Chip
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Yield Example
• Example #1: – 20-cm wafer for a die that is 1.5 cm on a side.– Solution: Die area = 1.5x1.5 = 2.25cm2.
Dies per wafer = 3.14x(20/2)2/2.25 – 3.14x20/(2x2.5)0.5=110.
• Example #2– wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
α = 3 (measure of manufacturing process complexity)– 252 dies/wafer (remember, wafers round & dies square)– die yield of 16%– 252 x 16% = only 40 dies/wafer die yield !
• Die cost is strong function of die area– proportional to the third or fourth power of the die area
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Functionality and Robustness
• Prime requirement –IC performs the function it is designed for
• Normal behavior deviates due to – variations in the manufacturing process (dimensions and
device parameters vary between runs and even on a single wafer or die)
– presence of disturbing on- or off-chip noise sources• Noise: Unwanted variation of voltages or currents
at the logic nodes
•VLSI Design I; A. Milenkovic •3
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Reliability Noise in Digital Integrated Circuits
i(t)
Inductive coupling Capacitive coupling Power and groundnoise
v(t) VDD
• from two wires placed side by side– inductive coupling
• current change on one wire caninfluence signal on the neighboring wire
– capacitive coupling• voltage change on one wire can
influence signal on the neighboring wire• cross talk
• from noise on the power and ground supply rails– can influence signal levels
in the gate
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Example of Capacitive Coupling
• Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology
0.16m CMOS0.12m CMOS
0.35m CMOS
0.25m CMOS
Pulsed Signal
Black line quietRed lines pulsedGlitches strength vs technology
From Dunlop, Lucent, 2000
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Static Gate Behavior
• Steady-state parameters of a gate – static behavior –tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances.
• Digital circuits perform operations on Boolean variables x ∈{0,1}
• A logical variable is associated with a nominal voltage level for each logic state
1 ⇔ VOH and 0 ⇔ VOL
• Difference between VOH and VOL is the logic or signal swing Vsw
V(y)V(x)VOH = ! (VOL)
VOL = ! (VOH)
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DC OperationVoltage Transfer Characteristic
VOH = f(VOL)VOL = f(VOH)VM = f(VM)
V(x)
V(y)
f
V(y)V(x)
VOH = f (VIL)
VIL VIH
V(y)=V(x)
Switching ThresholdVM
VOL = f (VIH)
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Mapping between analog and digital signals
• The regions of acceptable high and low voltages are delimited byVIH and VIL that represent the points on the VTC curve where thegain = -1 (dVout/dVin)
V IL V IH V in
Slope = -1
Slope = -1
V OL
V OH
Vout
“ 0” VOL
VIL
VIH
VOH
UndefinedRegion
“ 1”
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Definition of Noise Margins
Gate Output Gate Input
Large noise margins are desirable, but not sufficient …
For robust circuits, want the “0” and “1” intervals to be as large as possible
Gnd
UndefinedRegion
"1"
"0"
VOH
VIL
VOL
VIHNoise Margin High
Noise Margin Low
NMH = VOH - VIH
NML = VIL - VOL
VDD VDD
GndGnd
•VLSI Design I; A. Milenkovic •4
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The Regenerative Property
• A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level
v0 v1 v2 v3 v4 v5 v6
-1
1
3
5
0 2 4 6 8 10
t (nsec)
V (v
olts
) v0
v2
v1
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Conditions for Regeneration
v1 = f(v0) ⇒ v1 = finv(v2)
v0 v1 v2 v3 v4 v5 v6
v0
v1
v2
v3 f(v)
finv(v)
Regenerative Gate
v0
v1
v2
v3
f(v)
finv(v)
Nonregenerative Gate
To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points.
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Noise Immunity
• Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise
• For good noise immunity, the signal swing (i.e., the difference between VOH and VOL) and the noise margin have to be large enough to overpower the impact of fixed sources of noise
• Noise margin expresses the ability of a circuit to overpower a noise source– noise sources: supply noise, cross talk, interference, offset
• Absolute noise margin values are deceptive– a floating node is more easily disturbed than a node driven by a
low impedance (in terms of voltage)
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Directivity
• A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit– In real circuits full directivity is an illusion (e.g., due to capacitive
coupling between inputs and outputs)
• Key metrics: output impedance of the driver andinput impedance of the receiver– ideally, the output impedance of the driver should be zero– input impedance of the receiver should be infinity
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Fan-In and Fan-Out
Fan-out – number of load gates connected to the output of the driving gate
gates with large fan-out are slowerN
M
Fan-in – the number of inputs to the gate
gates with large fan-in are bigger and slower
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The Ideal Inverter
• The ideal gate should have– infinite gain in the transition region– a gate threshold located in the middle of the logic swing– high and low noise margins equal to half the swing– input and output impedances of infinity and zero, resp.
g = - ∞
Vout
Vin
Ri = ∞
Ro = 0
Fanout = ∞
NMH = NML = VDD/2
•VLSI Design I; A. Milenkovic •5
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An Old-time Inverter
NM H
Vin (V)
V
o u t
( V )
NM L
VM
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
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Delay Definitions
t
Vout
Vin
inputwaveform
outputwaveform
t
Vin Vout
Propagation delay?
signal slopes?
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Delay Definitions
t
Vout
Vin
inputwaveform
outputwaveform
tp = (tpHL + tpLH)/2Propagation delay
t
50%
tpHL
50%
tpLH
tf
90%
10%tr
signal slopes
Vin Vout
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Modeling Propagation Delay
• Model circuit as first-order RC network
R
C
vin
vout
vout (t) = (1 – e–t/τ)V
where τ = RC
Time to reach 50% point ist = ln(2) τ = 0.69 τ
Time to reach 90% point ist = ln(9) τ = 2.2 τ
• Matches the delay of an inverter gate
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Power and Energy Dissipation
• Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates– supply line sizing (determined by peak power)
Ppeak = Vddipeak– battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T ∫ p(t) dt = Vdd/T ∫ idd(t) dt– packaging and cooling requirements
• Two important components: static and dynamic
E (joules) = CL Vdd2 P0→1 + tsc Vdd Ipeak P0→1 + Vdd Ileakage
P (watts) = CL Vdd2 f0→1 + tscVdd Ipeak f0→1 + Vdd Ileakage
f0→1 = P0→1 * fclock
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Power and Energy Dissipation
• Propagation delay and the power consumption of a gate are related
• Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors– the faster the energy transfer (higher power dissipation) the
faster the gate
• For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant– Power-delay product (PDP) –
energy consumed by the gate per switching event• An ideal gate is one that is fast and consumes little energy, so the
ultimate quality metric is– Energy-delay product (EDP) = power-delay 2
•VLSI Design I; A. Milenkovic •6
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• Digital integrated circuits have come a long way and still have quite some potential left for the coming decades
• Some interesting challenges ahead– Getting a clear perspective on the challenges and
potential solutions is the purpose of this course• Understanding the design metrics that govern
digital design is crucial– Cost, reliability, speed, power and energy
dissipation
Summary
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The MOS Transistor
Polysilicon Aluminum
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The NMOS Transistor Cross Sectionn areas have been doped with donor ions (arsenic) of concentration ND - electrons are the majority carriers
p areas have been doped with acceptorions (boron) of concentration NA - holes are the majority carriers
Gate oxide
n+Source Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide(SiO2)n+
PolysiliconGate
L
W
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Switch Model of NMOS Transistor
Gate
Source(of carriers)
Drain(of carriers)
| VGS |
| VGS | < | VT | | VGS | > | VT |
Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)
Ron
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Switch Model of PMOS Transistor
Gate
Source(of carriers)
Drain(of carriers)
| VGS |
| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |
Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)
Ron
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CMOS Inverter: A First Look
VDD
Vout
CL
Vin
•VLSI Design I; A. Milenkovic •7
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CMOS Inverter: Steady State Response
VDD
Rn
Vout = 0
Vin = V DD
VDD
Rp
Vout = 1
Vin = 0
VOL = 0VOH = VDD
VM = f(Rn, Rp)
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Growing the Silicon Ingot
From Smithsonian, 2000
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CMOS Process at a Glance
Define active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
• One full photolithographysequence per layer (mask)
• Built (roughly) from the bottom up5 metal 24 metal 12 polysilicon3 source and drain
diffusions1 tubs (aka wells, active
areas)
exception!
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oxidationoptical
mask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dry
acid etch
photoresistdevelopment
stepper exposure
Photolithographic Process
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Patterning - Photolithography
1. Oxidation2. Photoresist (PR) coating3. Stepper exposure4. Photoresist development
and bake5. Acid etching
Unexposed (negative PR)Exposed (positive PR)
6. Spin, rinse, and dry7. Processing step
Ion implantationPlasma etchingMetal deposition
8. Photoresist removal (ashing)
mask
SiO2 PR
UV light
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Example of Patterning of SiO2
Si-substrate
Silicon base material
Si-substrate
3. Stepper exposure
UV-lightPatternedoptical mask
Exposed resist
1&2. After oxidation and deposition of negative photoresist
PhotoresistSiO2
Si-substrate
Si-substrate
SiO2
8. Final result after removal of resist
Si-substrate
SiO2
5. After etching
Hardened resist
SiO2Si-substrate
4. After development and etching of resist, chemical or plasma etch of SiO2
Hardened resist
Chemical or plasmaetch
•VLSI Design I; A. Milenkovic •8
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Diffusion and Ion Implantation
1. Area to be doped is exposed (photolithography)
2. DiffusionorIon implantation
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Deposition and Etching1. Pattern masking
(photolithography)
2. Deposit material over entire wafer
CVD (Si3N4)chemical deposition
(polysilicon)sputtering (Al)
3. Etch away unwanted material
wet etchingdry (plasma) etching
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Planarization: Polishing the Wafers
From Smithsonian, 20008/29/2005 VLSI Design I; A. Milenkovic 46
Self-Aligned Gates
1. Create thin oxide in the “active” regions, thick elsewhere
2. Deposit polysilicon
3. Etch thin oxide from active region (poly acts as a mask for the diffusion)
4. Implant dopant
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Simplified CMOS Inverter Process
cut line
p well
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P-Well Mask
•VLSI Design I; A. Milenkovic •9
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Active Mask
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Poly Mask
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P+ Select Mask
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N+ Select Mask
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Contact Mask
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Metal Mask
•VLSI Design I; A. Milenkovic •10
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A Modern CMOS Process
p-
p-epip well n well
p+n+
gate oxide
Al (Cu)
tungsten
SiO2
SiO2
TiSi2
Dual-Well Trench-Isolated CMOS
field oxide
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Modern CMOS Process Walk-Through
p+
p-epi Base material: p+ substrate with p-epi layer
p+
After plasma etch of insulating trenches using the inverse of the active area mask
p+
p-epi SiO2
3SiN
4
After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer)
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CMOS Process Walk-Through, con’t
SiO2 After trench filling, CMP planarization, and removal of sacrificial nitride
After n-well and VTpadjust implants
n
After p-well and VTnadjust implants
p
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CMOS Process Walk-Through, con’t
After polysilicon deposition and etch
poly(silicon)
After n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon.
p+n+
After deposition of SiO2insulator and contact hole etch
SiO2
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CMOS Process Walk-Through, con’t
After deposition and patterning of first Al layer.
Al
After deposition of SiO2insulator, etching of via’s, deposition and patterning of second layer of Al.
AlSiO2
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Layout Editor: max Design Frame
•VLSI Design I; A. Milenkovic •11
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max Layer Representation
• Metals (five) and vias/contacts between the interconnect levels– Note that m5 connects only to m4, m4
only to m3, etc., and m1 only to poly, ndif, and pdif
– Some technologies support “stacked vias”
• Wells (nw) and other select areas (pplus, nplus, prb)
• Active – active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc))
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CMOS Inverter max Layout
VDD
GND
NMOS (2/.24 = 8/1)
PMOS (4/.24 = 16/1)
metal2
metal1polysilicon
InOut
metal1-poly via
metal2-metal1 via
metal1-diff via
pfet
nfet
pdif
ndif
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Simplified Layouts in max• Online design rule checking (DRC)• Automatic fet generation (just overlap poly and
diffusion and it creates a transistor)• Simplified via/contact generation
– v12, v23, v34, v45– ct, nwc, pwc
0.44 x 0.44 m1
0.3 x 0.3 ct
0.44 x 0.44 poly
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Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um
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Design Rules• Interface between the circuit designer and process
engineer• Guidelines for constructing process masks• Unit dimension: minimum line width
– scalable design rules: lambda parameter– absolute dimensions: micron rules
• Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
• A complete set includes– set of layers– intra-layer: relations between objects in the same layer– inter-layer: relations between objects on different layers
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Why Have Design Rules?To be able to tolerate some level of fabrication
errors such as1. Mask misalignment
2. Dust
3. Process parameters (e.g., lateral diffusion)
4. Rough surfaces
•VLSI Design I; A. Milenkovic •12
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Intra-Layer Design Rule Origins
• Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab– minimum line width is set by the resolution of the
patterning process (photolithography)• Minimum spaces between objects (that are not
related) on the same layer to ensure they will not short after fab
0.150.15
0.3 micron
0.3 micron
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Intra-Layer Design Rules
Metal2 4
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal1 3
32
Contactor Via
Select2
or6
2Hole
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Inter-Layer Design Rule Origins
1. Transistor rules – transistor formed by overlap of active and poly layers
Transistors
Catastrophic error
Unrelated Poly & Diffusion
Thinner diffusion,but still working
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Transistor Layout
1
2
5
3
Tran
sist
or
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Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
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Inter-Layer Design Rule Origins, Con’t
2. Contact and via rulesM1 contact to p-diffusion
M1 contact to poly
Mx contact to My
Contact Mask
Via Masks
0.3
0.14
both materials mask misaligned
M1 contact to n-diffusion
Contact: 0.44 x 0.44
•VLSI Design I; A. Milenkovic •13
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Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
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CMOS Process Layers
COGpassivation, overglass, pad=glassglass
CMTthird-level metal=m3metal3
CVSmetal2/metal3 via=via2via2
CMSsecond-level metal=m2metal2
CMFfirst-level metal=m1metal1
CCP and CCAcontact cut, poly contact, diffusion contact=contactcontact
CSPpdiff, p-select, pplus, p+=grow(pdiff)p-diffusion implant
CSNndiff, n-select, nplus, n+=grow(ndiff)n-diffusion implant
CPGpoly, gate=polypolysilicon
CAAthin oxide, thinox, island, gate oxide=pdiff+ndiffactive
CWPbulk, substrate, tub, p-tub, moat=pwellp-well
CWNbulk, substrate, tub, n-tub, moat=nwelln-well
MOSIS mask labelAlternative names for mask/layerDerivation from drawn
layers
Mask/Layer name
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To probe further
• http://www.leb.e-technik.uni-erlangen.de/lehre/mm/html/start.htm