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Atoms to go… Atoms to go… Ionic memory and data storageIonic memory and data storage
Michael N KozickiMichael N KozickiMichael N. KozickiMichael N. KozickiProfessor of Electrical Engineering
School of Electrical, Computer, and Energy Engineering, ASU
Adjunct Professor, GIST, Korea
Visiting Professor, University of Edinburgh, UK
d d C O A h l i CFounder and CTO, Axon Technologies Corp.
Chief Scientist, Adesto Technologies Corp.
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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“The future ain't what it used to be ” Y i Bused to be.” - Yogi Berra
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Facebook server racks – www.time.com
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F
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Exponential growth - Moore’s Law3 1 billi t i t d t ISSCC 2011
?3.1 billion transistor processor announced at ISSCC 2011
chip
s pe
r si
stor
sTr
ans
“Scaling”½ F ¼ 4 d it½ F → ¼ area → 4x density
http://commons.wikimedia.org/wiki/File:Moores_law_(1970-2010).PNG
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64 Gb Flash memory shrink
32 billion storage
Source: Intel/Micron
32 billion storage elements in 118 mm2
If a 20 nm feature in the chip was the size of a residential street how big would the chip be?street, how big would the chip be?
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Why the future ain't what it used to be• The fruits of Moore’s “Law”
Discrete electronics turned into microelectronics and– Discrete electronics turned into microelectronics and Moore’s Observation was born
– More devices/cm2 means more performance for less $$p $$» Higher speed, higher reliability, smaller systems also result
– The best way to get more devices per cm2 is to make th ll th lt f li t bli h dthem smaller – the cult of scaling was established
• But scaling is breaking down at nano-di idimensions
– Nano devices don’t behave like wee versions of their bigger brothersbigger brothers
» Inhomogeneity and quantum mechanics make life interesting– Tightly packed structures, ultra-thin layers, smallTightly packed structures, ultra thin layers, small
numbers of electrons all lead to big issues
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The end of scaling as we know it?
• “…innovation has overtaken scaling as gthe driver of semiconductor technology performance...” - Bernard Meyerson, IBM
• Really smart design will keep logic on the Moore’s Law performance trajectory p j y
– e.g., multi-core processors…
• But what about memory?
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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The memory marketMarkets and applications utilizing memory devices:
Total memory market size for two key types of memory:
Flash and DRAMComputersCell PhonesMusic PlayersDigital CamerasA li
70
ons)
FLASH Memory
Flash and DRAM
AppliancesCars/automotivePrintersTVsGame consoles 40
50
60
ue in
($ Billio DRAM Memory
Game consolesVideo playersServers
20
30
40
dwide Reven
0
10
2005 2006 2007 2008 2009 2010
Total W
orld
2005 2006 2007 2008 2009 2010YEAR
Source: Denali, 2010
Solid state drives (SSDs)
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The challenge we are facing…–The demand for memory capacity is growing
Y h t h !» You can never have too much memory!–Memory scaling is stalling as existing charge-
storage devices will struggle to meet futurestorage devices will struggle to meet future industry requirements
» Smaller devices mean fewer electrons stored» Smaller devices mean fewer electrons stored• small charge is difficult to retain and detect
» Lower programming voltage is required to prevent p g g g q pclosely-spaced devices talking to one another
• programming time rises greatly• compensate by changing structure• results in greatly reduced retention
Flash storage cell in a Samsung 4 Gb MLC chip taken from an iPod Nano by ChipWorks
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Requirements for next-generation q gmemory
• Physical scalability–Assume 1012 bits in a “chip-like” form factor p
with extremely compact periphery/high array efficiencyF 20 20 2 t bit d 4–For a 20 x 20 mm2 terabit array area and a 4 -6F2 cell, F must be less than 10 nm
–Not good news as nobody knows how to–Not good news as nobody knows how to define/make reliable sub-10 nm metallic interconnects in a manufacturing environment!environment!
– Implies F should be > 10 nm but then multi-level cell and/or multi-layer array is absolutelylevel cell and/or multi layer array is absolutely necessary to achieve density
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More requirements…• Electrical scalability
–At the F = 22 nm technology node, the supplyAt the F 22 nm technology node, the supply voltage is < 1V
–Critical current at 22 nm is no more than a few tens of μA
–Programming in the pJ range for energy conservation and heat dissipationconservation and heat dissipation
• Manufacturability /economicsO ll t d t f fi t bit–Overall cost and cost of first bit
–Compatible with existing processesL it ( lti l li ti d–Longevity (multiple applications and technology generations)Reliability the killer of promising new–Reliability… the killer of promising new technologies!
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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The basics of resistive memoryy• Change in resistance on the
application of a voltage/currentapplication of a voltage/current– Devices have a high resistance state
(HRS reset off) and one or more low(HRS, reset, off) and one or more low resistance states (LRS, set, on)
– Usually not a subtle effecty• A variety of mechanisms are
possiblep– Field- or current-driven– Can involve a change in materialg– Bulk, interfacial, or filamentary
• Can be unipolar or bipolarCan be unipolar or bipolar
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Resistive memory taxonomy
R. Waser et al., “Redox-Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges”, Adv. Mater., vol. 21, 2632–2663 (2009).
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Physical changes in materials• “Heine Rohrer showed five examples of where, if
the space becomes small new phenomena
y g
the space becomes small, new phenomena happen… if the distance is very short, diffusion, atomic or ionic motion, is very fast.”, y
Interview with Masakazu Aono, ACS Nano, Vol. 1, No. 5, 379-383 (2007)
• Physical changes can result in highly stable, y g g y ,widely spaced states
– inherently non-volatile resistance levels– small # of atoms can lead to large macroscopic effects
• Filamentary processes are typically more scalable as on-state resistance is independent of device area
– filaments can be a few nm in radius
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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Solid electrolytes• Solid electrolytes behave like liquid electrolytes…
ORM M+
M+
M+
e- e-
MM M
M M
ORM+
M+
M+
M+
M+
M+ M+M+
M+M+
M+M+
M+
e-
Mobile ions
Mobile ions
Liquid Lateral/coplanar Vertical
MM
• Ions move under the influence of an electric field and electrochemical reactions are possible
Liquid Lateral/coplanar Vertical
and electrochemical reactions are possiblecathode (conductor): M+ + e- → M reductionanode (with excess M): M → M+ + e- oxidationanode (with excess M): M → M+ + e- oxidation
Electrochemistry occurs at a few 100 mVy
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http://en.wikipedia.org/wiki/Chemical_synapse
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Rainer Waser and Masakazu Aono
…ion-migration effects are coupled to redox
nature materials | VOL 6 | NOVEMBER 2007 | www.nature.com/naturematerials
…ion migration effects are coupled to redoxprocesses which cause the change in resistance. They are subdivided into cation-migration cells, y g ,based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths
f b id f d d dof sub-oxides are formed and removed…
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The famous Memristor
J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, R. S. Williams, “Memristive
D.-H. Kwon et al., “Atomic structure of conducting nanofilaments in TiO2 resistive switching memory,” D. R. Stewart, R. S. Williams, Memristive
switching mechanism for metal/oxide/metal nanodevices,” Nature Nanotechnology, Vol. 3,
429 (2008).
2 g y,Nature Nanotechnology, published online: 17
January 2010, DOI: 10.1038/NNANO.2009.456(2010).
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Cation-based solid electrolyte device
+e-Cryo-TEM
Oxidizableelectrode
Cryo TEM image of filament 15nm
electrodeMM → M+ + e-
Bias > write
Ion cuMetallic electrodeposit low resistanceGlassy electrolytehigh resistance M+ + e- → MM
threshold
urrent
Mobile ions added during processing or via electroforming
Inertelectrode
-e-Low energy approach High energy approach
Reverse bias or high forward current dissolves electrodeposit
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El t l t El t d t l
Materials - electrolytes & electrodesElectrolyte Electrode metals
Ag CuGexSy W WG S W Pt Ni WGexSey W, Pt, Ni WGe-Te TiW TaNGST MoA S AAs-S AuZnxCd1-xS PtCu2S Pt, TiT O Pt RTa2O5 Pt, RuSiO2 Co W, Pt, IrWO3 W WTiO PtTiO2 PtZrO2 AuMSQ (SiO2) PtCuTe/GdOx WCuTe/GdOx WGexSey/SiOx PtGexSey/Ta2O5 WCu S/Cu O PtCuxS/CuxO PtCuxS/SiO2 Pt
Compiled by John Jameson, Adesto Technologies
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Electrolyte example:
16
Resistivity of Ge-S vs. Ag content
12
14T = 25 ºC
6
8
10
(.c
m)
0 5A S 0 5G S
(Bychkov)
Concentration and distribution
2
4
Log
() ( Percolation 0.5Ag2S-0.5GeS2
(Belin)Ag saturated Ge-S(Elliott)
of Ag as well as geometry determines resistance of layer
-4
-2
00.001 0.01 0.1 1 10 100 Ag2S
(Miyatani)
(Elliott)
ρ change due to electrodeposition
-6
4
Ag (at %)
Ag
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Growth of electrodeposit p
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Reversal of electrodeposit growthp g
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Reaction environmentAnodic dissolution• equilibrium → oxidation for applied bias
j ~ exp (qVc/kT)
• electrochemical electron transfer (Butler-Volmer)• no overpotential, fast reactionAg, Cu
Cation transportAg+,Cu++ V Cation transport• drift /diffusion transport• high fields → drift dominant• non-linear very fast at high fieldSE
Ag ,CuazeEWa
0
Applied Field EVc
Pt, W, ...
• non-linear, very fast at high fieldSE
Cathodic deposition• electrochemical electron transfer (Butler-Volmer)electrochemical electron transfer (Butler Volmer)• crystallization overpotential
Filament growth• Even with multiple nucleation sites,“winner takes all” (field confinement)
• Filament forms within electrolyte
Adapted from R. Waser, MRS Spring Meeting 2009 RRAM Tutorial.
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Building a filament: voltage, time & charge• Total charge transferred in time t is Q0 = jtAeff
Aeff is the effective area of the electrodepositj = j0 exp (αqVc/kT)j j0 exp (αqVc/kT)
tprog = Q0 ⁄ [ j0 exp (αqVc/kT) Aeff ]
Saturation at low voltage(nucleation
i l
Q0 is in the fCrange (from electrodeposit
l ) ioverpotential, work function difference, , t ?)
volume) - gives programming energy in the
d f fJetc.?) order of fJ…
WriteRead
j0=exchange current density, α =transfer coefficient, q=cation charge, Vc= cell voltagej0 exchange current density, α transfer coefficient, q cation charge, Vc cell voltageU. Russo, D. Kamalanathan, D. Ielmini, A.L. Lacaita, and M.N. Kozicki, “Study of Multilevel
Programming in Programmable Metallization Cell (PMC) Memory,” IEEE Transactions on Electron Devices, Vol. 56, 1040 – 1047 (2009).
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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Endurance and retention
91215
rent
(μA
)
Endurance >1010 cycles with no degradation evident for 75 nm
0369
circ
uit c
urAg-Ge-Se device (Iprog= 12 µA)
M.N. Kozicki, M. Park, and M. Mitkova,
-30
1.0E+09 1.0E+10 1.0E+11
Test
c
M.N. Kozicki, M. Park, and M. Mitkova, “Nanoscale Memory Elements Based on Solid-
State Electrolytes,” IEEE Trans. Nanotechnology, vol. 4, 331-338 (2005).
1E+13m
] OFF
Cycles
Retention >10 yrs at 100ºC
1E 0
1E+09
1E+11
ance
[Ohm
25°C70°C100°C
Retention >10 yrs at 100 C for 90 nm Ag-Ge-S device
(full wafer results)
1E+03
1E+05
1E+07
Res
ista
ONR. Symanczyk, „Conductive Bridging Memory
Development from Single Cells to 2Mbit Memory Arrays” 8th Non Volatile Memory 1E+03
1E-01 1E+01 1E+03 1E+05 1E+07 1E+09
Time [s] 10y
Memory Arrays , 8th Non-Volatile Memory Technology Symposium, 2007.
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On-state resistance vs.programming currentprogramming current
Ultra-low current 00
01 Multiprogramming 01
10
11
Multi level cell (MLC)
More reasonable range
Data compiled by John Jameson, Adesto Technologies. Some data taken from R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-Based Resistive Switching Memories – Nanoionic
Mechanisms, Prospects, and Challenges”, Adv. Mater., Vol. 21, 2632–2663 (2009).
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Low voltage operationProgram: 600mV @ 400nA
0 7
0.8
Cathode
Anode
Tprog ~ 14us
0.3
0.4
0.5
0.6
0.7
Voltage (V)
Vprog ~ 0.6V Ron < 750KΩ
0
0.1
0.2
0 5 10 15 20 25 30
Time (us)
Erase: 600mV @ 200nA1 4
Cathode
Anode
0 8
1
1.2
1.4
age (V)
Verase ~ 0.6V
Roff > 50MΩ
600 mV, 400/200 nA operation3 36 J it 240 fJ
0 2
0.4
0.6
0.8
Volta
Terase ~ 2usN. Derhacobian, S.C.Hollmer, N. Gilbert, M.N. Kozicki “Power and Energy Perspectives of
3.36 pJ write, 240 fJ erase
0.2
84 85 86 87 88 89 90 91 92
Time (us)
Kozicki, Power and Energy Perspectives of Nonvolatile Memory Technologies,” Proc. IEEE, vol. 98, 283-298 (2010).
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Dynamic (pulse) programmingf A G S d iof Ag-Ge-Se devices
M acro M odel Fit to W-GeSe-Ag 0.5 μm Device M acro M odel Fit to W-GeSe-Ag 0.5 μm Device Transimpedance Amplifier, Rf=1k (WRITE)
0.4
0.6
)
Lab_IN
Lab_OUT
Sim in
Transimpedance Amplifier, Rf=1k (ERASE)
0
0.2
)
0 2
0
0.2
Volta
ge (V
) Sim_in
Sim_outOff
0 6
-0.4
-0.2
Volta
ge (V
)
Lab_in
Lab_out
Sim out
On Off
Continued
-0.4
-0.2
0 100 200 300 400 500Time (ns)
On-0.8
-0.6
0 100 200 300 400 500Time (ns)
_
Sim_indecrease in resistance
Time (ns)
Write
Time (ns)
Erase
Output signal is via a transimpedance amplifier so that increasing voltage magnitude means increasing current (or decreasing device resistance)
N. Gilbert, C. Gopalan, and M. N. Kozicki, “A Macro model of Programmable Metallization Cell Devices,” Solid State Electronics, vol. 49, 1813-1819 (2005).
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Schematic diagram of two-stage g gconducting filament formation process
Both the initial formation and radial growth are driven by ion migration
U R D K l th D I l i i A L L it d M N K i ki “St d f M ltil l
But… is this everything?
U. Russo, D. Kamalanathan, D. Ielmini, A.L. Lacaita, and M.N. Kozicki, “Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory,” IEEE Transactions on Electron
Devices, Vol. 56, 1040 – 1047 (2009).
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Joule heating during programming with high currents
• Joule heating is evident at low Rload/high current• Maximum temperature rise for 1 kΩ load is 40ºC
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Conservative programming model
1 pJ operating point
Model is based on a Ag/Ag-Ge-S/W 1T-1R cell and includes transistor load and Joule heating effects
U. Russo, D. Kamalanathan, D. Ielmini, A.L. Lacaita, and M.N. Kozicki, “Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory,” IEEE Transactions on Electron
Devices, Vol. 56, 1040 – 1047 (2009).
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Erase kinetics
Erase time defined by 10x increase in resistance
D. Kamalanathan, U. Russo, D. Ielmini, and M.N. Kozicki, “Voltage-Driven On–Off Transition and Tradeoff With Program and Erase Current in Programmable Metallization Cell (PMC) Memory,”
IEEE Electron Device Letters, Vol. 30, 553 – 555 (2009).
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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Photo: William West
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Photo: Chakku Gopalan
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Electrodeposit evolution in a homogeneous solid electrolytehomogeneous solid electrolyte
Highest R region
1,2D nucleation Outwardth
3D growth Constrained3D thgrowth 3D growth
Growth speed of a MA=atomic massGrowth speed of a (cylindrical) nanofilament
A2[cm/s] [A]Mh I
N=&
MA=atomic massNA=Avogadro’s #Ze0=charge on ionρ=filament densityr=filament radius2
A 0r zN eπ ρExample: Ag filament of 10nm diameter at I = 1 μA 1 3 /h→ & X. Guo, C. Schindler, S. Menzel, and R. Waser,
Erase initiation via potential concentration at tip of electrodeposit
Adpted from R. Waser, MRS Spring Meeting 2009 RRAM Tutorial.
1.3m/sh→ ~ X. Guo, C. Schindler, S. Menzel, and R. Waser, “Understanding the switching-off mechanism in Ag+
migration based resistively switching model systems,” Appl. Phys. Lett., Vol. 91, 133513 (2007).
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Where do the metallic filaments form?
Jaakko AkolaUniversity of Jyväskylä andUniversity of Jyväskylä and Tampere Technological University, Finland
Bob JonesBob JonesJülich Research Center, Germay
Tomas WagnerUniversity of Pardubice CzechUniversity of Pardubice, Czech Republic
Techniques:
Full DFT, 500 atom system
Example: Ag As S
X-ray diffraction, neutronscattering, EXAFS
Cavities comprise 24% of the
46
Example: Ag12As35S53Mostly As-S bonds, Ag-S bondsCavities comprise 24% of the volume of Ag12As35S53, (SiO2 is 32% but cavities are more dispersed?)
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Filament morphology
40 nm
Unrestricted DLA growth40 nm
Full filament may be composed of few to many nanofew to many nano-filaments in parallel.
Rainer WaserRWTH Aachen and Jülich Research Center, Germany
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Resistance in atomic-scale wiresConductance quantized in units of 2e2/h (R = 12.9kΩ)
Pull
PPu
ll
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Quantized conductance in CBRAM
J h J Ad t T h l iJohn Jameson, Adesto Technologies
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Quantized conductance atomic switchK. Terabe,et al., NIMS, Nature, vol. 433, p. 47 (2005).K. Terabe,et al., NIMS, Nature, vol. 433, p. 47 (2005).
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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Array options
Active (1T-1R)Bias BL
VprogVprog Solid electrolyte element
Bias BL
Logic 15-20F2
DRAM 6 8F2
Vprog VprogSelect
WL
DRAM 6-8F2
progWL
Vprog is above or below transistor drain voltage to program or erase selected cell programming current viacell, programming current via bit line (BL)
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1T-1R array fabrication and performance
Via 23
Metal 2
Storage Cell
Standard Foundry Logic Process
WLi+1
SLi+1
BLj+1BLjBLj‐1
Metal 2
Metal 1
Via 12WLi
WL
SLi
ContactPoly Gate
WLi‐1
SLi‐1
Anode (Active Electrode)Cathode (Inert Electrode)
BL
~50ns
~20nsWL
Program Operation (SET)20 ns
Erase Operation (RESET)50 ns
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Multi-level cell (MLC) write
Three transistors are used to createare used to create three discrete current levels to set ON resistance (gives 4 resistance states = 2 bits).states 2 bits).
N E Gilbert and M N Kozicki “An EmbeddableN.E. Gilbert and M.N. Kozicki, An Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE Journal of Solid-state Circuits, vol. 42, no.
6, pp 1383-1391, June 2007
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MLC readCurrent comparatorsused to sense device current
N.E. Gilbert and M.N. Kozicki, “An Embeddable Multilevel Cell Solid
00011011Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE
Journal of Solid-state Circuits, vol. 42, no. 6, pp 1383-1391, June 2007
Fig. 3. Read circuit for multi-bit per cell implementations.
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MLC array operationArrayRow Decode
Bias
00 01 10 11
Column Decode
Write WriteReadWrite WriteEraseErase
N E Gilb t d M N K i ki “A E b dd bl M ltil l C ll S lid El t l t M A ” IEEEN.E. Gilbert and M.N. Kozicki, “An Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE Journal of Solid-state Circuits, vol. 42, no. 6, pp 1383-1391, June 2007
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Benefits of passive arrays
-/+ VT/2
Memory element
T
4F2
+/- VT/24F2
Stackable!Stackable!
1F2
<1F2 with MLC
Selected cell has +/-half threshold voltage on / f frow and -/+half on column for write or erase
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Example of multi-layer approachp y pp
1st device layer
2nd device layer
Example (from Matrix Semiconductor)
y
p ( )showing diode isolation in a passive array of OTP structures
Solid electrolyte devices are compatible with such 3-D approaches although passive arrays require unipolar
M. Johnson et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Antifuse
approaches, although passive arrays require unipolarprogramming or Zener diode isolation
M. Johnson et al., 512 Mb PROM With a Three Dimensional Array of Diode/Antifuse Memory Cells,” IEEE Journal of Solid-state Circuits, vol. 11, no. 38, 1920-1928, 2003
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Discrete diode isolation
Zener diode in series with Ag-Ge-S device
<10 nA leakage at 1 5 V<10 nA leakage at -1.5 V
Memoryturn onTurn off
Data from Sarath C. Puthen Thermadam, ASUSee also H. Toda (Toshiba), US Patent #7,606,059, October 20, 2009
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Integrated diode isolation - writeCu top electrode - 35 nm
Cu doped SiO2 - 15 nm
n+ Sin+ SiAl - 200 nm
Dielectric
Data from Sarath C. Puthen Thermadam, ASU
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Integrated diode isolation - eraseCu top electrode - 35 nm
Cu doped SiO2 - 15 nm
n+ Sin+ SiAl - 200 nm
Dielectric
Data from Sarath C. Puthen Thermadam, ASU
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion
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Ionic memoryEnergy Ionic memory gained a formal place in the ITRS in
Energy efficiency
the 2007 Edition
Operational reliabilityOperational reliability
Operational reliability is still a concern for most RRAM contenders but energy efficiencymost RRAM contenders but energy efficiencylooks promising for ionic memory
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130nm (Cu BEOL) integration
BLVSL
Storage
WL
Storage Dielectric
Access Transistor
Salient Features:• 1Mb EEPROM/Flash Macro on Standard Foundry 130nm• Programmable elements requires 2 non critical masksin BEOL flow
• Cell size determined by access device• Cell size determined by access device,core cell will scale with CMOS
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It’s alive!
Image downloaded and stored on the
Image stored and read back on Adestoand stored on the
hard driveread back on Adesto serial device
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Th k fThank you for tt ti !your attention!
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• No exponential is forever…• The need for new memory• The contender - resistive memory• Introduction to ionic memory• Device characteristics and models• Device characteristics and models• Materials at the nanoscale• Active and passive arrays• Real stuff• Questions and discussion