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ATAN0144
ATA8520D Reference Design
APPLICATION NOTE
Features
• Reference design for SIGFOX application with ATA8520 transmitter orATA8520D transceiver device
• Compatible with uplink only or uplink/downlink operation• In compliance with SIGFOX certification, i.e., class levels regarding TX
output power and RX sensitivity• In compliance with CE/ETSI certification• Compatible with discreet solutions and solutions with front-end
modules (FEM)• Includes schematic, layout and BOM
Description
This application note describes the reference design to develop andcomplete a PCB layout for a system using the ATA8520 transmitter (uplinkonly) [1] or ATA8520D transceiver (uplink/downlink) [2]. The recommendeddesign is used in the SIGFOX- and CE-certified ATA8520-EK1-E evaluationkit.
In the development of a PCB, various requirements must be taken intoaccount:
• SIGFOX certification [3]• ETSI/CE certification [4]• BOM-optimized system design
In addition to the above requirements, the following specifications must beconsidered:
• SIGFOX classification for uplink operation, i.e., range definition• Selection of operating mode, i.e., uplink only or uplink and downlink
operation• Current consumption and power supply, i.e., battery operation• Antenna selection, i.e., antenna gain and size• BOM cost
Atmel-9407A-ATAN0144_Application Note-11/2015
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Table of Contents
Features.......................................................................................................................... 1
Description.......................................................................................................................1
1. Block Diagram of the ATAB0101A-Rev3.1 PCB........................................................ 3
2. RF Design..................................................................................................................6
3. Digital Design...........................................................................................................12
4. Digital and RF Layout.............................................................................................. 13
5. End-Of-Line Testing.................................................................................................18
6. References.............................................................................................................. 19
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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1. Block Diagram of the ATAB0101A-Rev3.1 PCBThe ATA8520-EK1-E evaluation kit and the ATA8520-EK2-E/-EK3-E extension boards use the same PCBATAB0101A-Rev3.x with a different bill of material (BOM). Figure 1-1 shows the block diagram of the PCBATAB0101A-V3.1 for the ATA8520-EK1-E kit with the schematic and layout referenced in [5].
The PCB ATAB0101A-Rev3.2 for the ATA8520-EK2-E kit and ATAB0101A-Rev3.3 for the ATA8520-EK3-E kit are not shown, but use the same RF front end with a different digital section.
Figure 1-1 Block Diagram of ATA8520-EK1-E Kit for Uplink and Downlink Operation
32.768kHz
24.305MHz
SPI bus
ATAB0101A-Rev3.1 PCB
dire
ctio
n pow
er
TWI bus
power
eventresetpower-on
Host MCUATmega328P
RX SAW869.5MHz
Temperature sensorAT30TS75A
RF TransceiverATA8520D
RF SwitchBGS12AL7-4
SMA 50ΩAntenna
3Vsupply
LNA ~10dBBFR360F
TX SAW868.3MHz
The PCB includes the following functional blocks:
1. Host MCUThe Host MCU is an ATmega328P MCU for the ATA8520-EK1-E and ATA8520-EK2-E kit, and aSAM (Cortex-M) device for the ATA8520-EK3-E. The host MCU runs the target application andcontrols the ATA8520D RF transceiver and AT30TS75A temperature sensor. For the ATA8520-EK2-E and -EK3-E extension boards the MCU is located on the development kit attached to the boardand must be ordered separately.
2. RF transceiverThe ATA8520D RF transceiver operates as an RF modem device, including the SIGFOX protocolstack, firmware and RF transmit and receive functions. If only the transmit function is required, theATA8520 device can be used instead. The devices ATA8520 and ATA8520D are pin-to-pincompatible.
3. Temperature sensorThe AT30TS75A is a temperature sensor with a digital TWI interface (I2C compatible). The supplypower for the sensor is controlled by the host MCU.
4. RX SAW filter
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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The RX SAW filter is recommended for receive operation and has an RF blocking function for out-of-band RF signals. The RF RX frequency range is 869.525MHz +-96kHz as defined by SIGFOX.
5. TX SAW filterThe TX SAW filter is recommended for suppressing spurious out-of-band emissions, i.e., 2nd and3rd harmonics of the RF TX frequency 868.13MHz ±96kHz. This filter must be capable of supportingRF power levels up to 15dBm.
6. LNAThe RF LNA is required to achieve the final RX sensitivity level of −126dBm as defined by SIGFOX.The ATA8520D transceiver has a typical RX sensitivity level of −121dBm and the LNA mustadditionally compensate for RX SAW filter loss. This results in a total gain of ~10dB. The LNA isswitched ON/OFF by the RF transceiver.
7. RF switchThe RF switch selects the RX or TX signal to be routed to the external antenna. The direction iscontrolled by the RF transceiver. An external switch of the transceiver is used instead of its internalswitch to facilitate the PCB layout and avoid any instabilities and spurious emissions due tocrosstalk in combination with the TX SAW filter.
If the downlink (receive) operation is not required, the design can be simplified as shown in Figure 1-2.
Figure 1-2 Block Diagram for ATA8520-EK1-E Kit for Uplink Only Operation
32.768kHz
24.305MHz
SPI bus
ATAB0101A-Rev3.1 PCB
TWI bus
power
eventresetpower-on
Host MCUATmega328P
Temperature sensorAT30TS75A
RF TransmitterATA8520
SMA 50ΩAntenna
3Vsupply
TX SAW868.3MHz
In this application, the RX path with LNA and RX SAW is removed together with the external RF switch.The key parameters for these applications are listed in Table 1-1.
Table 1-1 Key Parameters for Figure 1-1 and Figure 1-2
Parameters Uplink/Downlink (Figure 1-1) Uplink Only (Figure 1-2)
TX frequency 868.13MHz ±96kHz
TX RF power conducted at 25°C,868.13MHz
~10dBm ~11dBm
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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Parameters Uplink/Downlink (Figure 1-1) Uplink Only (Figure 1-2)
TX SAW filter 868.3MHz
Pass band: 868.0MHz to 868.6MHz
Attenuation: ~3dB
Max. source power: 15dBm at 50Ω
RX frequency 869.525MHz ±96kHz --
RX sensitivity conducted at 25°C,869.525MHz
−126dBm --
RX SAW filter 869.6MHz
Pass band: 868.6MHz to870.6MHz
Attenuation: ~3dB
Max. source power: 10dBm at50Ω
--
LNA Frequency range: 800MHz to900MHz
Gain: ~10dB
Noise figure: 2dB
--
RF switch Frequency range: 800MHz to900MHz
Attenuation: ~0.5dB
--
The above mentioned power levels are for typical environment conditions and power supply values:• At 24-25°C environmental temperature• For 3.0V supply voltage in 3V supply mode (see data sheets [1] and [2])• Including crystal offset calibration at 868.13MHz and 24-25°C (see application notes [11] and [12]).
Any changes in the above conditions will have an impact on the output power levels (see datasheets [1] and [2]) and the spurious emission which is also related to the antenna characteristicschosen for the final system.
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2. RF DesignRF design is a critical aspect of PCB development because it requires correct 50Ω matching of the RFtransceiver and SAW filters. Atmel recommends following the application notes and datasheets for the:
• RF transmitter [1] or transceiver [2] device (summarized in the following section)• TX and RX SAW filter [6], [7]• LNA [8]
Figure 2-1 shows the RF section of the schematic for the ATAB0101A-Rev3.x PCB. All parts not mountedare indicated and the 50Ω matching tracks are highlighted in bold. The RF section includes the followingmain components:
• U2 - ATA8520 RF transmitter or ATA8520D RF transceiver device• XTAL1 - 24.305MHz crystal for ATA8520/ATA8520D device (see [9])• SAW2 - B3744 TX SAW filter
The following is also required for downlink operation with the ATA8520D:• Q2 - BSS84 power switch transistor for LNA• Q3 - BFR360F LNA RF transistor• SAW1 - TA1457A RX SAW filter• U9 - BGS12AS7-4 RF antenna switch
Figure 2-1 lists information about some critical RF components used in this design which are used andtested with the PCB ATAB0101A-V3.1.
Table 2-1 RF Components
Component Value Part no. / Manufacturer
XTAL1 24.305MHz KDS: DSX321G, 1C324305AB0B
NDK: NX3225SA, EXS00A-CS08559
NX2016SA, EXS00A-CS08560
SAW1 869.6MHz
~ 3dBi insertion loss
TaiSaw: TA1457A
SAW2 868.3MHz
~ 3dBi insertion loss 15dBmsource power
TDK/EPCOS: B3744
U9 – RF Switch 800 to 900MHz
~ 0.4dBi insertion loss
Infineon: BGS12AS7-4
Q3 - LNA 800 to 900MHz
>10dB gain
< 2dB noise figure at 3V supply
Infineon: BFR360F
C RF components
±0.25pF or ±5%
Murata, Kemet, TDK
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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Component Value Part no. / Manufacturer
L RF components
±2% or ±5%
Murata, Taiyo Yuden, Coilcraft, Abracon,Johanson Technology
L2 Choke Murata
Figure 2-1 RF Section for Up- and Downlink Operation
32 31 30 29 28 27 26 25
RPB
7R
F_EV
ENT
RF_
NSS
9 10 11 12 13 14 15 16
NC
NC
AGN
D
PB7
PB6
PB5
PB4
PB3
NC
XTAL
1
XTAL
2
AVC
C
VS PC0
PC1
PC2
NC
RFIN
SPDT_RX
SPDT_TX
RF_OUT
VS_PA
SPDT_ANT
NC
U2ATA8520D
PB2
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
1
2
3
4
5
6
7
8
24 MOSI
RF_PWRON
RF_NSS
RF_EVENT
MISO
CTRL
SCK
RPC5
RPC2
RPC1
RF_NRES
RPC4
RPC3
RPB023
22
21
20
19
18
17
GND
GND
GND
C32
100nF
C21
22nF
C1
100pF
47pF
3.3V
U9BGS12AL7-4
SAW2B3744
RF_Transmitter
SAW1
TA1457A
C31
100nF
GNDGND
C27
2.2pF
C27
2.2pF
C25
1pF
GND
GND
RF
GND CTRL
C30
47pF
GND
GND
GND GND
XTAL1
24.305MHz
C24
0.068µF
C23
220nF
GND
C22
2.2µF
GND
C7
100pF
C6
5.6pF
C9b
1pF
4
45
1
1
2
3
2
21
2
1
35
6
3
6
3
2
1
VDD
RFIN
GND
GND
GN
D
OU
T
IN GN
D
CTRL
RF1
GND
RF2
4
5
6
3
2
1
GND
IN/OUT
GND
GND
OUT/IN
GND
R27
47kΩ
BR11
0Ω
BR6
0Ω
50ohms
50ohms
50ohms Controlled Impedance
50ohms
50ohms
RPB7Q2
BSS84LT1G
R2810Ω
GND
GND
GND GND
GND GND
GND
BR9L10
2.7nH
L7
27nH
GND
RPB0
GND
RF_PWRON
GND
C33
5.6pF
C28
220pFC29
C9
1pF
GND
3.3V
3.3V
3.3V
3.3V
3.3V
2
3
7
1
L6
27nH
L2BLM15HG102SN1D
XAnt1LTT-SASF56GT L9
8.2nHL818nH
L318nH
L3b18nH
Q3BFR360F
BR130Ω
BR12 0Ω
R60Ω
R2447kΩ
R2510kΩ
R2636Ω
0Ω
BR10
0Ω
BR7
BR9: insert jumper for 3V supply only!
50ohms
L1GND
12nH
If uplink only operation is required the ATA8520 or ATA8520D can be used with the SAW2 filterimplemented for TX operation. The antenna switch U9 can be replaced with a 0Ω resistor between pin1and pin5 of the switch footprint and the pins 1, 2, 3, 4 and 6 of the device U2 have to be connected toGND.
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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Figure 2-2 RF Section for Uplink only Operation
32 31 30 29 28 27 26 25
RPB
7R
F_EV
ENT
RF_
NSS
9 10 11 12 13 14 15 16
NC
NC
AGN
D
PB7
PB6
PB5
PB4
PB3
NC
XTAL
1
XTAL
2
AVC
C
VS PC0
PC1
PC2
NC
RFIN
SPDT_RX
SPDT_TX
RF_OUT
VS_PA
SPDT_ANT
NC
U2ATA8520D
PB2
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
1
2
3
4
5
6
7
8
24 MOSI
RF_PWRON
RF_NSS
RF_EVENT
MISO
SCK
RPC5
RPC2
RPC1
RF_NRES
RPC4
RPC3
RPB023
22
21
20
19
18
17
C21
22nF
C1
100pF
SAW2B3744
RF-Transmitter
GND
RF
GND
GND
GND
GND GND
XTAL1
24.305MHz
C24
0.068µF
C23
220nF
GND
C22
2.2µF
GND
C7
100pF
C6
5.6pF
C9b
1pF
45
1
1
2
3
2
21
2
1
3
6
3
GND
GND
GN
D
OU
T
IN GN
D
50ohms
GND
GND
BR9L10
2.7nH
GND
RPB0
GND
C9
1pF
3.3V
3.3V
XAnt1LTT-SASF56GT
L318nH
L3b18nH
R60Ω
R2510kΩ
BR9: insert jumper for 3V supply only!
50ohms
50ohms
50ohms
For the connection to the host MCU the following signals have to be used as shown in Figure 2-3:
• SPI connections:– PB3 / MISO data signal– PB2 / MOSI data signal– PB1 / SCK clock signal– PB5 / NSS chip select signal
• PB6 / Event signal IRQ• PC1 or PC2 or PC3 or PC4 or PC5 / NPWRONx wake-up signal or PB4 / PWRON wake-up signal• PC0 / NRESET chip reset signal (optional)
For the device wake-up only one signal is necessary while the NPWRONx signals have to be connectedto GND for wake-up and the PWRON signal has to be connected to VDD for wake-up. If PWRON is notused it has to be connected to GND. If the NPWRONx signals are not used they can be left open as theyhave an internal pull-up resistor.
The reset signal PC0 / NRESET can be used but is not required to reset the device. The device has apower-up reset and a SPI command for the reset operation. The pin PC0 has an internal pull-up resistorand can be left open if not used.
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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Figure 2-3 Connections to Host MCU
NC
IRQ
NSSMISO
MOSI
SCK
VDD
RF_IN
AGN
D
PB7
PB6
PB5
PB4
PB3
PC2
PC1
PC0
VSAVC
C
XTAL
2
XTAL
1
SPDT_RX
SPDT_ANT
NC
SPDT_TX
RF_OUT
VS_PA
PB2
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
VS = 5VQ1 C3 C4
C5Microcontroller
AtmelATA8520D
Wake/Monitor
NC
NC
NC
To save a pin connection there is an alternative way to connect the host MCU as shown in Figure 2-4.The wake-up pin PB4 / PWRON can be used together with the chip-select signal NSS to wake-up thedevice and the NPWRONx signals are not used. This requires that the signal NSS has to be kept at lowlevel when performing the SPI command “OFF mode” (0x05) to keep the device in OFF mode. Whenpulling the signal NSS high the device will wake-up and stay wake-up until performing a reset or an “OFFmode” command.
Figure 2-4 Alternative Connections to Host MCU
NC
IRQ
NSSMISO
MOSI
SCK
VDD
RF_IN
AGN
D
PB7
PB6
PB5
PB4
PB3
PC2
PC1
PC0
VSAVC
C
XTAL
2
XTAL
1
SPDT_RX
SPDT_ANT
NC
SPDT_TX
RF_OUT
VS_PA
PB2
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
PB1
PB0
DGND
DVCC
PC5
PC4
PC3
VS = 5VQ1 C3 C4
C5Microcontroller
AtmelATA8520D
NC
NC
NC
The following guidelines must be considered for RF design:
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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ATA8520 and ATA8520D (U2) Guidelines:
1. The decoupling capacitor of AVCC, C23 must be placed as close to pin 12 as possible becauseotherwise the series inductance would be too high and supply bypassing no longer effective at highfrequencies.
2. The decoupling capacitor of DVCC, C21 must be placed as close to pin 20 as possible. Thisdecoupling capacitor should be connected directly to the DGND pin and ground layer using vias.Otherwise the sensitivity of the receiver or the spurious performance of the transmitter may sufferdue to spurious clock emission by the integrated AVR.
3. The decoupling capacitor of VS_PA, C24 must be placed as close to pin 8 as possible becauseotherwise the series inductance would be too high and the power amplifier might not work correctly.An extra capacitor placed close to pin 8 (VS_PA) and another capacitor close to pin 13 (VS) is thusnecessary even in a 3V application.
4. The decoupling capacitor of VS, C22 must be placed as close to pin 13 as possible becauseotherwise the series inductance would be too high and supply bypassing no longer effective at highfrequencies.
5. Direct connection of the DGND pin to the exposed die pad must be avoided and at least four viasplaced under the exposed die pad. Failure to do this causes isolation of the integrated AVR from RFfront end to be worse. The exposed die pad is also the RF ground for receive and transmitoperation. Reduced sensitivity or lower output power may result from bad ground connection on theexposed die pad.
6. The crystal must be placed as close to the IC as possible to avoid extra capacitance on XTAL1 andXTAL2.
7. It is advisable to design the lines carrying the RF signal to be as short as possible and place theelements of the matching networks as close to the IC as possible.
8. Pin 5 must remain open.9. Avoid routing XTAL, AVCC and VS lines in parallel and close to each other over long distances;
doing so reduces the coupling of the XTO signals to the supply voltage. Failure to do so may causespurious receiver or transmitter emissions.
10. Avoid routing XTAL1 and XTAL2 lines in parallel and close to each other over long distances so thatthe XTO oscillation margin is not reduced.
11. Pin 1 should be connected to GND.12. If the internal SPDT switch is not used, connect pins 3, 4 and 6 to GND.13. The internal SPDT switch is controlled by the ATA8520D firmware and used to select the antenna
direction with the U9 external switch. To facilitate this, SPDT_RX pin 3 and SPDT_TX pin 6 areconnected to the logical level required for the RF switch control pin 6, which is connected to theSPDT_ANT pin 4 of the transceiver.
14. PB7 pin 29 controls LNA power switch during receive operation.
SAW Filter Guidelines:
1. The TX SAW filter SAW2 should be selected to operate at up to 15dBm of source power and with50Ω matching elements.
2. The RX SAW filter SAW1 should be used with 50Ω matching elements.3. The typical insertion loss of an SAW filter is ~3dB.
LNA Guidelines:
1. The LNA is placed between the antenna and SAW filter.2. The required gain is ~10dB with a noise figure of ~2dB.
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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3. Typical current consumption is ~5mA at 3V supply.4. An L2 choke is used for suppressing noise from the supply voltage.
RF Switch Guidelines:
1. The RF switch is used for 50Ω RF signals.2. The supply voltage can be derived from PB0 pin 22, which controls the power for a front-end
module (FEM). It can alternatively be connected directly to a 3V supply due to the low currentconsumption (as shown in Figure 2-1), or the RF_PWRON signal applied for switching on the RFdevice can be used.
3. The direction is controlled by the internal SPDT switch (as shown in Figure 2-1) or by using the PB7pin 29 of the transceiver.
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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3. Digital DesignThe MCU and sensor-related blocks are designed as specified in their datasheet and following theguidelines given there."The maximum clock frequency is ~8MHz, which is not critical for the design andlayout.
Figure 3-1 shows the digital section of the schematic for the ATAB0101A-Rev3.1 PCB and includes thefollowing main components:
• U1 - ATmega328P MCU (alternative ATmega168PA or ATmega88PA can also be used instead asthey are pin-to-pin compatible)
• XTAL2 - 32.768kHz crystal to operate at low power, i.e., for internal timer 2 operation• U3 - AT30TS75A temperature sensor with a TWI (I2C) digital interface• Q1 - BSS84 sensor power switch transistor• LD1 - Sensor power LED (green)• LD2 - General purpose LED (red)• SW1 - General purpose button
All other sensor components on the PCB are not mounted, but the footprint is provided for futureenhancements. The MCU I/Os are also available on connector pins for prototyping. The power supplyattached to connector X1 should be 2.9V to 3.1V, in compliance with the transmitter/transceiver supplyand sensor supply. The max. MCU clock for 3V supply is ~10MHz (see [10]).
Figure 3-1 Digital Section
3233 31 30 29 28 27 26 25
RF
EVEN
TLE
D
BTN
RF_
PWR
ON
RF_
NR
ES
MO
SI
MIS
O
SNS_
PWR
RPB
0
RF_
NSS
PD1
PD0
MC
U N
RES
SCL
SDA
PC3
PC2
SCK
9 10 11 12 13 14 15 16
(INT0
) PD
2
GN
D P
AD
(TXD
) PD
1
(RXD
) PD
0
(RES
ET) P
C6
(SC
L/AD
C5)
PC
5
(SD
A/AD
C4)
PC
4
(AD
C3)
PC
3
(AD
C2)
PC
2
PD5
(T1/
OC
0A)
PD6
(AIN
0/O
C0A
)
PD7
(AIN
1)
PB0
(ICP1
/CLK
O)
PB1
(OC
1A)
PB2
(OC
1B/S
S)
PB3
(MO
SI/O
C2A
)
PB4
(MIS
O)
PD3 (INT1/OC2B)
PD4 (T0/XCK)
U1ATmega328P-MU
GND3
VCC4
GND5
VCC6
PB6 (TOSC1/XTAL1)
PB6 (TOSC2/XTAL2)
(ADC1) PC1
(ADC0) PC0
ADC7
GND21
AREF
ADC6
AVCC
(SCK) PB5
1
1
2
1
3
5
1
12
SDA
LED
SCL 2
3
4
8
7
6
5
2
4
6
2
3
4
5
6
7
8
24 PC1
MISO
SDA
SCL
SCK MOSI
MCU_NRES
PC023
22
21
20
19
18
17
GND
GND
GND
GND
LD1R1
1kΩ
C64
100nF
GND
XTAL2
3.3V3.3V
3.3V 3.3V
3Vsens
3.3V
3.3V
3Vsens
Power switch for sensors
3Vsens
X1 XISP1MCU ISP
T-SensorU3
AT30TS75
ext. Power
C12
100nF
C11
100nF
GND
GND
C13
100nF
GND
GNDGND
32.768kHz
GND
Q1
GND
C5
100pF
GND
SNS_PWR
PD4
ALERT
GND
VCC
A0
A1
A2
12LD2
SML-310MTT86N
R2
1kΩGND
BTN 1
3
2
2
3
4
SW1
SML-LX0603SRW-TR
SKRAALE010
BSS84LT1G
R4
300Ω
R310kΩ
GND
ATAB0101A-V3.1 (Standalone Kit):
R6110kΩ
3Vsens
R6210kΩ3Vsens
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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4. Digital and RF LayoutThe PCB layout is described in the following section and follows the guidelines given above. Figure 4-1shows the top layer of the PCB where all RF signals are routed. The critical sections are:
• The RX signal path with LNA and RX SAW filter• The TX signal path with TX SAW filter• The crystal connections to the ATA8520 or ATA8520D device
Figure 4-1 Signal and RF Signal Layout
Figure 4-2 shows the second layer, i.e., the GND layer. The cut in the middle of the PCB isolates thecritical LNA section and RF signals from the digital area. This improves the noise level for the LNA, whichoperates at very low signal levels of −126dBm. The second area is to isolate the crystal and to improvethe temperature drift behavior of the crystal.
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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Figure 4-2 Ground Plane Layout
Figure 4-3 shows the third layer, i.e., the supply layer with the same structure as shown in Figure 4-2. Theareas for the 5V supply (used for the ATA8520-EK2-E kit only) and the 3V sensor supply are also shown.
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Figure 4-3 5V/3V Supply Plane Layout
The fourth layer used for signal routing is not shown here; however it is included in the PCB data [5].
To change the PCB for uplink only operation the modifications shown in Figure 2-2 have to be applied tothe top layer signal plane. This is shown in Figure 4-4. It is not required to do these changes for uplinkonly operation but can be used for PCB testing.
Atmel ATA8520D Reference Design [APPLICATION NOTE]Atmel-9407A-ATAN0144_Application Note-11/2015
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Figure 4-4 Layout Changes for Uplink only Operation
Figure 4-5 shows the PCB stack layer composition. For 50Ω signal matching, it is important to have thematerial and setup of layer LY-Top and layer LY-2 as shown in Figure 4-5.
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Figure 4-5 PCB stack layer
The manufacturing data for the PCB is as follows:
• PCB material: IT-180A, 1.57mm thick• Layers: 4• Finish: ENIG• Minimum via hole size: 0.4mm• Minimum via pad size: 0.7mm• Minimum track width: 0.2mm (7.87mils)• Minimum spacing: 0.254mm (10mils)• Internal power plane (negative) – mid-layer 1, GND• Internal power plane (negative) – mid-layer 2, PWR (split plane)• Controlled impedance: 50Ω
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5. End-Of-Line TestingThe final PCB should be tested end-of-line as described in [11]. An important step is the required RFfrequency calibration due to the crystal frequency offset as well as the PCB capacitance for the crystalsignal connections to the ATA8520D transceiver device. This additional capacitance is not compensatedfor by the internal capacitors and requires an offset correction. The ATA8520 and ATA8520D devices canstore the crystal compensation values given by the crystal manufacturer in an internal EEPROM. DuringEOL testing, these crystal parameters are corrected with the actual crystal offset and the additional PCBoffset characteristic and programmed into the internal EEPROM..
This calibration ensures the SIGFOX operation with the remaining temperature drift for the crystalfrequency.
Additional calibration at a second temperature is required depending on the temperature range for theoperation of the final SIGFOX node product. This is described in [12] and is mandatory for CE compliantoperation and testing (see [13]). For SIGFOX compliant operation this step is not required as the crystaltemperature drift is already taken into account for the RF frequency selection during up- and downlinkoperation.
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6. References[1] ATA8520 transmitter datasheet
[2] ATA8520D transceiver datasheet
[3] SIGFOX RF module qualification Atmel, M_000C_6D5A_02, October 5, 2015
[4] CE Certification E817418C-CC, October 27, 2015
[5] ATAB0101A-V3.1_design_documentation.pdf
[6] EPCOS/TDK SAW Filter B3744, B39871B3744H110
[7] TAI-SAW SAW Filter TA1457A
[8] Infineon, Application Note No. 150, Rev. 1.2, “900 MHz Low-Noise Amplifier Using the BFR360FTransistor in TSFP-3 Package”
[9] NDK NX3225SA 24.305MHz, EXS00A-CS08551 / EXS00A-CS08559 or KDS DSX321G 24.305MHz,1C324305AB0B
[10] ATmega328P datasheet
[11] ATAN0136 - ATA8520D Production and EOL Testing
[12] ATAN0142 - ATA8520D Crystal Calibration
[13] ATAN0140 - ATA8520D CE Conformance Testing and SIGFOX Certification
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FeaturesDescriptionTable of Contents1. Block Diagram of the ATAB0101A-Rev3.1 PCB2. RF Design3. Digital Design4. Digital and RF Layout5. End-Of-Line Testing6. References