Download - Assemblers 3
-
7/31/2019 Assemblers 3
1/46
-
7/31/2019 Assemblers 3
2/46
-
7/31/2019 Assemblers 3
3/46
[Label] [,..]
[..] optional part
[+][()]
Examples :
AREA
AREA+5
AREA(4)
AREA+5(4)
-
7/31/2019 Assemblers 3
4/46
First operand is register and
AREG,BREG,CREG , DREG
Second operand is memory word (symbolic
name and optional displacement)
-
7/31/2019 Assemblers 3
5/46
Instruction opcode Assemblymnemonic
Remarks
00 STOP Stop execution
01 ADD
02 SUB
03 MULT
04 MOVER Reg mem move
05 MOVEM Mem Reg move
06 COMP Sets condition code
07 BC Branch on condition
08 DIV
09 READ First operand not used
10 PRINT
-
7/31/2019 Assemblers 3
6/46
BC Instruction Format
BC
Codes Number
1 LT
2 LE
3 EQ
4 GT
5 GE
6 ANY
-
7/31/2019 Assemblers 3
7/46
opcode Reg Opnd Mem.Opnd
xczx
c
zxcz
xc
zxcz
xc
zxcz
xc
zxcz
xc
zxcz
xc
START 101
READ N 101) 09 0 113
MOVER BREG, ONE 102) 04 2 115
MOVEM BREG,TERM 103) 05 2 116
AGAIN MULT BREG,TERM 104) 03 2 116
MOVER CREG, TERM 105) 04 3 116
ADD CREG,ONE 106) 01 3 115
MOVEM CREG,TERM 107) 05 3 116
COMP CREG,N 108) 06 3 113
BC LE, AGAIN 109) 07 2 104
MOVEM BREG, RESULT 110) 05 2 114
PRINT RESULT 111) 10 0 114
STOP 112) 00 0 000
N DS 1 113)
RESULT DS 1 114)
ONE DC 1 115) 00 0 001
TERM DS 1 116)END
-
7/31/2019 Assemblers 3
8/46
Imperative Statements
Declaration Statements
Assembler Directives
-
7/31/2019 Assemblers 3
9/46
ADDAREG,FIVE
FIVEDC 5
OR
ADD AREG, = 5
-
7/31/2019 Assemblers 3
10/46
MNEMONIC
OPCODE LENGTH
ADD 01 1
SUB 02 1
Symbol Address
AGAIN 104
N 113
Analysis phaseSynthesis
phase
SOURCE
PROGRAMTARGET
PROGRAM
Mnemonic table
Symbol table
-
7/31/2019 Assemblers 3
11/46
1. Isolate the label, mnemonic opcode and
operand fields of a statement
2. If a label is present, enter the pair
(symbol,) in a new entry of
symbol table.
3. Check validity of the mnemonic opcodethrough a look-up in the Mnemonics table.
4. Perform LC processing
-
7/31/2019 Assemblers 3
12/46
1. Obtain the machine opcode corresponding
to the mnemoic from the mnemonic table
2. Obtain the address of a memory oprand
from the symbol table
3. Synthesis a machine instruction or
machine form of a constant, as the casemay be
-
7/31/2019 Assemblers 3
13/46
1. Two Pass Instruction
2. Single Pass Instruction
-
7/31/2019 Assemblers 3
14/46
Pass I
1. Separate symbol, mnemonic opcode andoperand fields,
2. Build the symbol table
3. Perform LC processing
4. Construct intermediate representation
Pass IISynthesis the target program
-
7/31/2019 Assemblers 3
15/46
START
STOP
END
ORIGIN
EQULTORG
-
7/31/2019 Assemblers 3
16/46
Mnemonic field
(statement class, code)
STATEMENT CLASS IS, DL and ADDeclaration Statements Assembler Directives
DC 01 START 01
DS 02 END 02
ORIGIN 03
EQU 04
LTORG 05
-
7/31/2019 Assemblers 3
17/46
Operand class Variant I
(operand class, code)
START 200 (AD,01) (C,200)
READ A (IS, 09) (S,01)
LOOP MOVER AREG,A (IS,04) (1) (S,01).
.
SUB AREG, =1 (IS,02) (1) (L,01)
BC GT,LOOP (IS,07) (4) (S,02)
STOP (IS,00)
A DS 1 (DL,02) (C,1)
LTORG (DL,05) .
-
7/31/2019 Assemblers 3
18/46
Operand class Variant II
(operand class, code)
START 200 (AD,01) (C,200)
READ A (IS, 09) A
LOOP MOVER AREG,A (IS,04) (1) AREG,A.
.
SUB AREG, =1 (IS,02) AREG, (L,01)
BC GT,LOOP (IS,07) GT,LOOP
STOP (IS,00)
A DS 1 (DL,02) (C,1)
LTORG (DL,05) .
-
7/31/2019 Assemblers 3
19/46
Comparison of two variants
Variant I
Work in PASS I
is more as
operand field is
completely
processed
IC In PASS I
takes more
memory
Variant II
Processing in
PASS I is simple
Reduces the
work of PASS I
Memory
requirement is
balanced
-
7/31/2019 Assemblers 3
20/46
ORIGIN
ORIGIN LOOP+2
EQU
BACK EQU LOOP
LTORG
-
7/31/2019 Assemblers 3
21/46
1 START 200
2 MOVER AREG,=5 200) 04 1 211
3 MOVEM AREG, A 201) 05 1 2174 LOOP MOVER AREG, A 202) 04 1 217
5 MOVER CREG, B 203) 05 3 218
6 ADD CREG,=1 204) 01 3 212
7 ..
12 BC ANY,NEXT 210) 07 6 214
13 LTORG
= 5 211) 00 0 005
= 1 212) 00 0 001
14 ..
15 NEXT SUB AREG,=1 214) 02 1 219
16 BC LT,BACK 215) 07 1 202
17 LAST STOP 216) 00 0 000
18 ORIGIN LOOP+2
19 MULT CREG, B 204) 03 3 218
20 ORIGIN LAST+1
21 A DS 1 217)
22 BACK EQU LOOP
23 B DS 1 218)
24 END25 =1 219) 00 0 001
-
7/31/2019 Assemblers 3
22/46
Data Structure of Pass I
Mnemonic
opcode
Class Mnemonic
info
MOVER IS (04,1)
DS DL R#7
START AD R#11
Symbol Address Length
LOOP 202 1
NEXT 214 1
LAST 216 1
A 217 1
BACK 202 1
B 218 1
Sl No Literal Address1 =5
2 =1
3 =1
Literal
#1
#3
-------
OPTAB SYMTAB
LITTAB
POOLTAB
-
7/31/2019 Assemblers 3
23/46
1. loc_cntr := 0; (default vale)
pooltab_ptr := 1 ; POOLTAB[1] := 1;littab_ptr := 1;
2. While next statement is not an END statement
(a) If label is present then
this_label := symbol in the label field;Enter (this_label,loc_cntr) in SYMTAB
-
7/31/2019 Assemblers 3
24/46
(b) If an LTORG statement then(i) Process literal LITTAB [POOLTAB[pooltab_ptr]]
LITTAB[littab_ptr-1] to allocate memory and put the
address in the address field. Update loc_cntr
accordingly.(ii) pooltab_ptr := pooltab_ptr + 1;
(iii) POOLTAB[pooltab_ptr] := littab_ptr;
( c) if a START or ORIGIN statement then
loc_cntr := value specified in the operand field;( d) if an EQU statement then
(i) this_addr := value of
(ii) Correct the symbol entry for this label to
(this_label, this_addr)
-
7/31/2019 Assemblers 3
25/46
(e) If a declaration statement then(i) code := code of the declaration statement
(ii) size:=size of memory area required by
DC/DS(iii) loc_cntr:= loc_cntr + size;
(iv) Generate IC (DL,code)..
-
7/31/2019 Assemblers 3
26/46
(f) If an imperative statement then
(i) code := machine code from OPTAB;(ii) loc_cntr : loc_cntr + instruction length from OPTAB
(iii) If Operand is a literal then
this_literal := literal in operand field;
LITTAB[littab_ptr]:=this_literal;littab_ptr := littab_ptr + 1;
else
(ie operand is symbol)
this_entry := SYMTAB entry number of operand;
Generate IC (IS.code) (S,this_entry);
-
7/31/2019 Assemblers 3
27/46
3. Processing of END statement(a) Perform step 2(b).
(b) Generate IC (AD,02).
(C) Go to Pass II.
-
7/31/2019 Assemblers 3
28/46
DC 5, 3, -7
By series of (DL,01) units can be put in the LC.
Processing of LTORG: two methods
1. Tables are created in Pass I and code is
created in Pass II2. Code is created in Pass I only
-
7/31/2019 Assemblers 3
29/46
Method II
START 200 (AD,01) (C,200)
MOVER AREG,=5 (IS,04) (1) (L,01)
MOVEM AREG,A (IS,05) (1) (S,01)
LOOP MOVER AREG,A (IS,04) (1) (S,01)
.
BC ANY, NEXT (IS,07) (6)(S,04)
LTORG (DL,01) (C,5)
-
7/31/2019 Assemblers 3
30/46
Pass II (Algorithm)
1.code_area_addressm := address of code area;
pooltab_ptr := 1;
loc_cntr := 0;
2. While next statement is not END statement(a) Clear machine_code_buffer;
(b) if an LTORG statement
(i) Process literals inLITTAB[POOLTAB[pooltab_ptr]]LITTAB[
POOLTAB[pooltab_ptr+1]-1] assemble the
literal in machine_codebuffer.
-
7/31/2019 Assemblers 3
31/46
Pass II (Algorithm)(ii) size:=size of memory area required for literals;
(iii) pooltab_ptr := pooltab_prt + 1;
(c) If a START or ORIGIN statement then
(i)loc_cntr:= value specified in operand field
(ii) size := 0;
(d) If a declaration statement
(i) if a DC statement then
Assemble the constant inmachine_code_buffer.
(ii) size:= size of memory area required by
DC/DS
-
7/31/2019 Assemblers 3
32/46
Pass II (Algorithm)
(e) If an imperative statement(i) get operand address from SYMTAB or
LITTAB
(ii) Assemble instruction inmachine_code_buffer.
(iii) size := size of insruction.
(f) If size 0 then(i) move contents of machine_code_buffer to
the address code_area_address+loc_cntr;
(ii) loc_cntr:=loc_cntr+size;
-
7/31/2019 Assemblers 3
33/46
Pass II (Algorithm)
3. (Processing of END statement)(a) Perform steps 2(b) and 2(f)
(b) Write code_area into output file.
-
7/31/2019 Assemblers 3
34/46
Error reportingIn Pass I In Pass II
1.Source Program need not be
preserved till PASS II
1. Source program need to be
preserved
2.Conserves memory and
avoids some amount of
duplicate processing
2. All errors against the
erroneous statement can be
reported
3.Can report only certain
errors such as syntax errors
3.Error report as well as target
code can be printed
4. Difficult to locate the targetcode corresponding to source
program
4. Debugging is easy
5. Debugging Difficult
-
7/31/2019 Assemblers 3
35/46
Organizational Issues
OPTABSYMTAB LITTAB
Pass I Pass II
Target
Program
Program
Listing
Source
program
Intermediatecode
Sourceprogram
SYMTAB always in memory
LITTAB partially in memoryOPTAB in memory during
pass I
-
7/31/2019 Assemblers 3
36/46
Loaders and Linkers
Schematic of program execution:
Translator Linker LoaderBinary
Program
Source
Program
Data
Results
Object
modulesBinary
programs Data
Flow
Control
Flow
-
7/31/2019 Assemblers 3
37/46
Various address
1. Translation time address
2. Linked address
3. Load time address
-
7/31/2019 Assemblers 3
38/46
Relocation
rf = lorgtorg 1
tsym = torg + dsym 2
lsym = lorg + dsym 3
lsym = torg + rf+dsym
= tsym + rf
-
7/31/2019 Assemblers 3
39/46
EXTRN and ENTRY statementsSTART 500
ENRTY TOTALEXTRN MAX,ALPHA
READ A 500) 09 0 540
LOOP 501)
.
.
MOVER AREG, ALPHA 518) 04 1 000
BC ANY,MAX 519) 06 6 000
.
BC LT,LOOP 538) 06 1 501
STOP 539) 00 0 000
A DS 1 540)
TOTAL DS 1 541)
END
-
7/31/2019 Assemblers 3
40/46
START 200
ENTRY ALPHA------
------
ALPHA DS 25 231) 00 0 025
END
Obj t d l
-
7/31/2019 Assemblers 3
41/46
Object module1. Header translated origin, size,exec start address
2. Program m/c lan program3. Relocation table: translated address of an address
sensitive instruction.
4. Linking table:
symbol symbolic name
Type PD/EXT public def./ext. ref
Translated address memory word , first word
allocated to symbol / required to contain the address
of a symbole
-
7/31/2019 Assemblers 3
42/46
ExampleSTART 500ENRTY TOTALEXTRN MAX,ALPHA
READ A 500) 09 0 540
LOOP 501)
.
.
MOVER AREG, ALPHA 518) 04 1 000
BC ANY,MAX 519) 06 6 000
.
BC LT,LOOP 538) 06 1 501
STOP 539) 00 0 000
A DS 1 540)
TOTAL DS 1 541)
END
-
7/31/2019 Assemblers 3
43/46
Example
1. Header torg 500, size = 42, esa = 500
2. Program as shown in the fig.
3. Relocation table
4. Linking table
500
538
ALPHA
MAX
TOTAL
EXT
EXT
PD
518
519
540
-
7/31/2019 Assemblers 3
44/46
RELOCATION ALGORITHM
1. program_linked_origin := from
linker command;
2. For each object module
a) t_origin := tran. Org. of the object module
OM_size := size of the object module;
b) relocation_factor := program_linked_origin
t_origin
c) Read the m/c program in work area
d) Read RELOCTAB of the object module
-
7/31/2019 Assemblers 3
45/46
(e) For each entry in RELOCTAB
(i) translated_addr := address in the
RELOCTAB entry;(ii) address_in_work_area := address of
work_area + translated_addresst_origin;
(iii) Add relocation_factor to the operandaddress in the word with the address
address_in_work_area.
(f) program_linked_origin :=program_linked_origin + OM_size.
E l
-
7/31/2019 Assemblers 3
46/46
ExampleLet l_org = 900
t_org = 500rf = 400
address of work area = 300
For the first entry in IRR
address_in_work_area = 300+500-500=300
(address of READ A)
address of operand is 400+540 = 940
For the second entry
address_in_work_area = 300+538-500= 338 (
operand is relocated by adding 400)