e·MMC v4.41 and v4.5 Architecture for High Speed Architecture for High Speed
Functions and Features
Victor TsaiMicron Technology, Inc.
Flash Storage Summits 2010Flash Storage Summits 2010
Agenda
• e·MMC Market Trend
• e MMC Versions• e·MMC Versions
• e·MMC v4.41 New Features
for High-Performance Mobile Handset Platform
• e·MMC v4.5 Preview
• In Conclusion
Flash Storage Summits 2010 2
e·MMC Market Trend
Flash Storage Summits 2010 3
e·MMC Share of Total Flash Market (% of total Gbytes)
16.0%18.0%20.0%
6 0%8.0%
10.0%12.0%14.0%
0.0%2.0%4.0%6.0%
20092010
20112012
2013
Flash Storage Summits 2010
Source: Micron Marketing
4
e·MMC Density Trend
80%
90%
100%
nit
s
40%
50%
60%
70%
nta
ge o
f U
n
128GB
64GB
32GB
16GB
0%
10%
20%
30%
40%
Perc
en 8GB
4GB
2GB
1GB
0%
20092010
20112012
20132014
Flash Storage Summits 2010
Source: Micron Marketing
5
Mobile Handset Booting Architecture
80%
90%
100%
nit
s
MLC-based eMMC
SLC-based eMMC
40%
50%
60%
70%
nta
ge o
f U
n
MLC-based Raw/Error Free NAND SLC NAND
10%
20%
30%
40%
Perc
en
OneNAND
NOR
0%
2009 20102011
20122013
2014
Flash Storage Summits 2010
2014
Source: Micron Marketing
6
e·MMC Versions
Flash Storage Summits 2010 7
• e·MMC v4.41– JEDEC document JESD84-A441, published in March
2010– Replaces e·MMC v4 4Replaces e MMC v4.4– Incorporates all e·MMC v4.4 features, plus new
features
• e·MMC v4.4– JEDEC document JESD84-A44, published in March
2009– Considered to be obsolete– Replaced by e·MMC v4.41
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ep aced by e C
8
e·MMC v4.41 New Featuresfor High-Performance Mobile for High Performance Mobile Handset Platform
Flash Storage Summits 2010 9
New Features for Demand Pagingg g
• e MMC v4.41 specification introduces 2 new features for Demand Paging code execution features for Demand Paging code execution strategies:– Background Operation– High Priority Interrupt (HPI)
• The features are complementary in improving Write Throughput performance as well as Write Throughput performance as well as Paging request latencies on the non-volatile memory solution
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Background OperationMMC f i i t l b k d ti • e·MMC may perform various internal background operations
necessary for internal maintenance purposes during run-time, independent from the normal operations initiated by the Host
• In order to reduce latencies during time-critical operations such as R d d W it d i i i t ll d ti b Read and Write, and minimize uncontrolled power consumption by e·MMC during Idle time, this feature gives the Host the capability to delay Device background operations until the Host explicitly initiates Device background operation in a controlled manner
• How it works– Device indicates to the Host the criticality of its need for internal
background maintenance operation by the value in the BKOPS_STATUS (ECSD[246]) registerWhen Host can allocates an extended period of inactivity it initiates Device – When Host can allocates an extended period of inactivity, it initiates Device background operation by writing any value to BKOP_START (ECSD[164]) register
• i.e. CMD6 with argument = (0x 03A4 FF00)
– Host may use high priority interrupt command to stop the background
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y g p y p p goperation
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Background Operation Benefits
BO Enabled
BO Disabled
User write request latency Foreground Time Consuming OperationsMinimized number of time consuming operations
WriteLatencyAverage
TimeForeground User write requestsUser is not accessing the memory
• Most time-consuming operations are due to e MMC internal Flash Data management (Garbage • Most time consuming operations are due to e MMC internal Flash Data management (Garbage
collection, wear leveling, bad block management, …)
• By enabling the Background Operation feature:
▶ The OS can check the e MMC internal state and ask to perform time consuming operations in
background -- i.e. when the user applications are not accessing the non-volatile memory
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▶ The e MMC usage is optimized to be in the best internal state during Foreground operations
▶ The number of Foreground time consuming operations is reduced and average throughput
improved 12
High Priority Interrupt (HPI)D i th ti f l lti l bl k W it E • During the execution of a large multiple-block Write or Erase operation, BUSY time can be long and unpredictable
• Due to this limitation, it is difficult to utilize e·MMC in system use cases such as Demand Paging, where data must be retrieved from the e·MMC with minimal latency
• e·MMC 4.41 introduced a mechanism to interrupt a busy condition in a controlled manner within a well-defined timeout, without compromising data integrityp g g y
• How it works– During a large multiple-block Write operation, data transfer can be terminated by a Stop
command (CMD12), but there may still be an extended period of BUSY time necessary to complete the Write operation on the data already transferredHPI i t t thi d t th D i t T t t h th t th H t – HPI interrupts this process and returns the Device to Trans state such that the Host can send a Read command to retrieve high-priority data
– The CORRECTLY_PRG_SECTORS_NUM field (EXT_CSD bytes [245:242]) indicates the number of 512B sectors successfully written to the e·MMC when the Write operation is interrupted by HPI -- Host can restart the Write operation with the correct address offset based on this information
Flash Storage Summits 2010
offset based on this information
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HPI Function
System
CMD
Write Read
e·MMC v4.4
Host may have to wait long time to issue the read command
ReadWrite stopCMD
DAT
CMD25
DATA Device Busy
CMD18CMD12
DATA
System Write Read
e·MMC v4.41
Arg[0]=“1”
Host can interrupt the long busy
Host can restart the rest of the write operation if needed
ReadWrite WritestopCMD
DAT
CMD25
DATA-0 Device Busy
CMD12 CMD12 CMD18
DATA
CMD25
DATA-1 DATA-2Device Busy
p
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HPI Benefits
Paging latency Foreground Time Consuming Operations
Reduced time to interrupt a time consuming operation
HPI Enabled
HPI Disabled
• Time consuming operations can dramatically reduce Paging efficiency resulting in OS freeze
Paging requests Time
PagingLatencyAverage
• Time consuming operations can dramatically reduce Paging efficiency, resulting in OS freeze
• By enabling the HPI feature:
▶ The OS is able to suspend on-going operations (generated by user applications or background
operation) to execute first the higher priority Paging operations
▶ The suspended operation can be resumed by the e MMC media driver as soon as the Paging
Flash Storage Summits 2010
▶ The suspended operation can be resumed by the e MMC media driver as soon as the Paging
operation is terminated
▶ Paging performances are homogeneous even during Foreground time consuming operations
15
Combined Effects of Background Operation and HPI
Paging latency
Minimized number of time consuming operationsReduced time to interrupt a time consuming operation
Foreground Time Consuming Operations
BO+HPI Enabled
BO+HPI Disabled
Paging requestsTime
PagingLatencyAverage
• By enabling both Background Operations and HPI features:
▶ Average e MMC Write throughput is improved for better user experience
▶ Homogeneous paging latencies allows to configure easier the Paging Algorithm and avoids
Paging requests
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System freezing
▶ On-going background operations can be postponed to process Foreground requests from user
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DDR Mode (52Mhz Max.)T f d d t l d b th l k d (DDR) b t • Transferred user data are sampled on both clock edge (DDR), but CMD line remains sampled clock rising edge (SDR) – The rising edge of the clock always capture odd numbered byte.– The falling edge of the clock always capture even numbered byte.– Block length is fixed as 512B.– Two CRC16 are computed per data line
• (one for even bits and the other for odd bits)
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Security and Data Integritye MMC v4.41/v4.4 specification introduces several new features that address the security and data integrity needs f hi h f h d l fof high-performance handset platforms
• Addition of hardware RESET pin and signal definition• Partition features to enable segregation of data• Replay Protected Memory Block (RPMB)• Multiple Write Protection definitions• Secure Trim, Secure Erase• Data Reliability definition• Enhanced Reliable Write definition
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Different Types of RESETH d R t• Hard Reset– Power Cycle or triggered by
H/W RESET (RSTN) signalW ite p otection is emo ed in CMD0 (0xF0F0F0F0)
Power Cycle or RSTNPOR
– Write protection is removed in memory regions protected by Power-On WP
• Soft Reset
CMD0 (0xF0F0F0F0)
Boot Sequences
Pre-Idle state
• Soft Reset– CMD0 arg=0x00000000 --
device moves to Idle state– CMD0 arg=0xF0F0F0F0 --
CMD0 (0x00000000)q
Idle state
CMD0 arg 0xF0F0F0F0 device moves to Pre-Idle state
– Write protection in memory regions protected by Power-On
Identification Sequences
Stand by
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WP is maintained Stand-by state
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Partition FeatureH t fi titi i MMC d i i • Host can configure partition in e·MMC device using extended CSD register– Independent addressable space
P titi i i lti l f WP i– Partition size is multiple of a WP group size– Configuration is one time program
• Each partition can be configured with two types of tt ib t attribute – Enhanced attribute (faster read/write access, better data
integrity) D f lt tt ib t ( l t )– Default attribute (normal mass storage memory)
– User may create enhanced area in the user area
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Host configures max 4 partitions allowing system to separate code from user storage area
General partition 1 Enhanced attribute0x000000x00000
code from user storage area
U d t
General partition 1
General partition 2
General partition 3
Standard attribute
Standard attribute
0x00000
0x00000
0x00000User data area General partition 3
General partition 4
Standard attribute
Standard attribute
Standard attribute
0x00000
0x00000User data area Standard attribute
Enhanced attribute
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Use Case Example
Boot partition1,2
Partitioninge·MMC Physical LayoutBoot partition1,2
EBOOT
XLOAD
Code Layout
Partition 1(Enhanced)
EBOOT
IPL
Logo
Partition 2(Enhanced)
User Area(Default)
Partitioning
MBR
ULDR
NKCopying
image data
Partition 3(Enhanced) User area
( h d )
NK
OS (Image FS)
EXTFAT
image data
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(High density ) EXTFAT
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Replay Protected Memory Block (RPMB)
Thi f ti id f th t t t d t t • This function provides means for the system to store data to the specific memory area in an authenticated and replay protected manner
• RPMB operation is a separate self-contained security • RPMB operation is a separate self contained security command protocol that has its own command opcodes (message types) and well-defined data structure
• This feature is designed to fulfill the security requirements below– EICTA CCIG Doc Ref: Eicta Doc: 04cc100– GSMA Doc Ref: Security Principles Related to Handset Theft 3.0.0
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RPMB Requirements (Device Side)Th R l P t t d M Bl k (RPMB) i • The Replay Protected Memory Block (RPMB) is defined as a separate partition in the e·MMC memory space– Partition size = multiples of 128KByte
Boot partition 1
Boot partition 2
• Secure storage of Authentication Key– An Authentication Key is written to the RPMB at
host system manufacturing time and is used as shared secret to authenticate subsequent RPMB t ansactions bet een the Host and De ice
RPMB
transactions between the Host and Device
• Transaction Authentication– Transactions (messages) are authenticated by the
Message Authentication Code (MAC) which is a hash value generated by the Authentication Key a
User data areavalue generated by the Authentication Key, a random number provided by the Host and the message itself using HMAC SHA-256
• [HMAC-SHA] Eastlake, D. and T. Hansen, "US Secure Hash Algorithms (SHA and HMAC-SHA)", RFC 4634,
Flash Storage Summits 2010
July 2006.
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Write Protect FeatureP t W it P t t• Permanent Write Protect– Once the Permanent Write Protect is set, the protected memory
region becomes read-only
• Power-On Write Protect (Volatile Write Protect)Power On Write Protect (Volatile Write Protect)– Once the Power-on Write Protect is set, it is persistent until the
next power cycle or H/W RESET– Host needs to re-set the Power-On Write Protect to memory
i th t it t t l thi t f it t ti h regions that it wants to apply this type of write protection each time after power cycle or H/W RESET
• For boot partitions, Write Protect is applied to an entire boot partitionp
• For User Area Partition and General Partitions, Write Protect is applied to memory regions defined by multiples of Write Protect Group Size
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Use Case ExampleCode Layout WP settings
Permanent WP
Power-On WP (4MB)
PartitioningBoot partition1,2
EBOOT
XLOAD
Power-On WP (4MB)
Power-On WP (4MB)
Partition 1(Enhanced)
MBR
IPL
Logo
Power-On WP (4MB)
Power-On WP (4MB)
Power-On WP (8MB)
Partition 2(Enhanced)
MBR
ULDR
NK Power On WP (8MB)
Power-On WP (256MB)
Unprotected
Partition 3(Enhanced) User area
(High density )
OS (Image FS)
EXTFAT
Flash Storage Summits 2010
* Assuming minimum write protect group size is 4MB
26
Secure Trim/Secure EraseS E• Secure Erase– When a Secure Erase command is sent, data in the
specified memory addresses must be purged from the physical memory arrayphysical memory array
– “Logical” memory erase is not acceptable
• Secure TrimFor cases where smaller amounts of data might be spread – For cases where smaller amounts of data might be spread through multiple erase groups, a force garbage collect command is added
– This allows the same function as Secure Erase to be This allows the same function as Secure Erase to be performed on write blocks (Sectors) instead of erase groups
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Secure EraseS E d • Secure Erase command sequences– CMD35 – Specify start address of erase groups– CMD36 - Specify end address of erase groups– CMD38 (with arg=0x80000000) – Erase operationCMD38 (with arg=0x80000000) Erase operation
User data area
Erase group ACMD35 (arg=A+1)
User data area
Erase group A+1
Erase group A+2
CMD35 (arg A+1)CMD36 (arg=A+3)CMD38 (arg=0x80000000) Physical
Memory Erase
Erase group A+3
Erase group A+4
Erase
Flash Storage Summits 2010
Erase group A+4
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Secure TrimS T i d
CMD35 (arg=A)CMD36 (arg=A+2)• Secure Trim command
sequences• Step1:
– CMD35 – Specify start address f it bl k t b d
CMD36 (arg=A+2)CMD38 (arg=0x80000001)
CMD35 (arg=B)CMD36 (arg=B+4)CMD38
of write blocks to be erased– CMD36 - Specify end address
of write blocks to be erased– CMD38 (with
arg=0x80000001) - Keep it bl k dd t b
User data area
Sector ASector A+2
(arg=0x80000001)
CMD35 (arg=C)CMD36 (arg=C)CMD38 (arg=0x80000001)
CMD35 (arg=xx)
User data area
write block address to be erased.
– Host can repeat Step 1 sequence until all memory blocks to be erased is identified
Sector B
Sector B+4
CMD35 (arg=xx)CMD36 (arg=xx)CMD38 (arg=0x80008000)
• Step2:– CMD35– CMD36– CMD38 (with
arg=0x80008000) - Erase
Sector C
PhysicalMemoryErase
Flash Storage Summits 2010
arg=0x80008000) Erase operation for the write blocks.
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Secure Bad Block Management• Allow the user to specify that bad blocks cannot contain any
user data when they are retired• When blocks are discarded, all “good” bits must be purged
before discarding.• ECSD register [134] need to be set to execute this feature
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Data ReliabilityD t R li bilit i d fi d f ll d• Data Reliability is defined as followed– High data reliability: once a Device indicates to the Host that a
write has successfully completed, the data that was written, along with all previous data written, cannot be corrupted by other
i h h i i i d ll i i i d id l operations that are host initiated, controller initiated or accidental (such as power interruption)
– Normal data reliability: there is some risk that previously written data may be corrupted for unforeseen events such as power i t tiinterruption
• Device indicates implementation of this feature in the ECSD registers– WR_REL_PARAM [166]: to indicate whether the Device supports
this feature– WR_REL_SET [167]: to set High Data Reliability per partition
• Performance implication– Write performance may be impacted when high data reliability is
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p y p g yset
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Enhanced Reliable WriteAll bl k 512B ( t ) i l th h t b i • All blocks are 512B (sector) in length; each sector being modified by the write is atomic
• If a power loss occurs during a Reliable Write, sectors may either contain old data or new data; all sectors being modified either contain old data or new data; all sectors being modified by the write operation may be in one of the following states: – All sectors contain new data– All sectors contain old data– Some sectors contain new data and some sectors contain old data
• REL_WR_SEC_C parameter has no meaning• Device defines which type (legacy or new) is supported
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e·MMC v4.5 Preview
Flash Storage Summits 2010 33
e·MMC v4.5 Primary Objectives
• Embedded-only specification• Performance improvement/optimization• Clarification of v4.41 functions and features
Flash Storage Summits 2010 34
Some New Features under ConsiderationE t di P titi Att ib t• Extending Partition Attributes– Adding attribute registers to clearly define and distinguish the behaviors of
individual partitions• Data Tag
– Providing information on the type and access frequency of the data being Providing information on the type and access frequency of the data being written
• Real-Time Clock– Adding a capability for the e·MMC device to receive real-time clock
information from the Host such that certain time-sensitive operations internal to the e·MMC device may be improved
• Power-Off Notification– Adding a capability for the Host to notify the e·MMC of an impending power
shutdown• Dynamic Device Capacity• Dynamic Device Capacity
– Extending the useful life of the e·MMC device by adding the capability of Host-initiated reduction of Device storage capacity in order to free up spare memory space to enable the e·MMC device to continue to function
• Discard Command
Flash Storage Summits 2010
– A variant of the TRIM command that is more memory technology friendly
35
In Conclusion
Flash Storage Summits 2010 36
• e·MMC has established to be the dominant • e MMC has established to be the dominant standard of managed, embedded mass-storage solution for Mobile
• New e·MMC v4.41 features address many advanced requirements in high-performance advanced requirements in high performance handset architecture
• v4.5 Preview – a peek into the future of the e·MMC Standard
Flash Storage Summits 2010 37
Thank You
Flash Storage Summits 2010 38