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Antelope Progress
• MMU and Cache->Datapath interfaces almost complete
• Datapath moving slowly, control issues keep surfacing
• Hazard Detection/Prevention coming along• IRQ/Exception handler is somewhat complete• Instruction Sequencer built, helps with multicycle
instructions and IRQ/Exception sequences
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Main Memory
• Controlled by State Machine
• Successfully simulated with delays
• Left to do: Cache<-> Memory interface– State machine
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Memory FSM
• Signals In:– Instruction read, Data read, Data write– Reset
• Signals out:– DataAddr, InstrAddr– select, r_w– valid, done
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Memory Delay
• Gen_lib component: delay– Rise delay = 80 ns– Fall delay = 0 ns
• State Machine sets signal high and then waits for the signal to propagate through
• Loops in wait state
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8 bit Cache Blocks(to enable byte transfer)
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Cache <-> Memory
• Signals out:– Pipeline hold– LoadMem (cache write)
• Signals in:– Data write, Data read, Instruction read– Valid, Done– Dirty, hit
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Instruction Sequencer
• Found that many multicycle instructions can be broken into a sequence of single cycle instructions.
• Wanted a way to trigger a sequence of instructions to run through the pipeline.
• Example: LDR/STR -> load the sequencer rom with an add/sub instruction and a custom ldr/str instruction. Activate the sequencer whenever LDR/STR runs through pipe.
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Sequencer Logic
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Sequencer Integration
• Sequencer is just placed in the fetch stage in parallel with the instruction cache.
• The sequencer determines whether or not it is in control of the datapath.
• If a sequence is requested, the PC is held at it’s current value (though I may have to decrement it…), and the sequencer inserts instructions into the datapath until it is done.
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Datapath
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Hazard Checking Logic
Checks to see if Rd (destination register) is read from in next 2
commands
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Original Design
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Overview
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Block Data Transfer
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Interrupt Handler
Component must handle the following seven cases:1. Reset (Highest Priority)
2. Data Abort
3. FIQ
4. IRQ
5. Prefetch Abort
6. Undefined Instruction
7. Software Interrupt (SWI) (Lowest Priority)
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Implementation
• One ROM file handles memory addresses.
• 3-bit input leads to 32-bit address for PC.
• Second ROM file handles CPSR alterations.
• 4-bit input leads to lower 8 bits of CPSR.
• Priorities of the interrupts are handled with CLZ functionality.
• Lastly, no interrupts leads to “Active = 0”.
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To do:
• Finish everything.