Analog Mixed Signal Reference Design Flow
(V1.0)
July 31, 2013
1/16
CONTENTS
1
Design Flow
3
Detailed AMS Design Flow 4
Library Preparation
2
Analog Mixed Signal Design
5
Block Implementation 6
Why need Analog Mixed Design Flow?
TOP Integration 7
Simulation Control 8
Analog Mixed Signal Simulation 9
Layout – Chip Assembly 10
Physical Verification 11
Full Chip Level Post Layout Simulation 12
2/16
Why need Analog Mixed Design Flow?
Mixed signal designs have both analog and digital subsections.
The design environment of analog and digital are very different.
Operation of the system relies on both functionality of each section, and interoperation between the analog and digital subsections.
Design Flow is required to consider analog and digital together
Digital Digital Analog Analog
Analog / Digital Approach
Analog Mixed Design Approach
3/16
Design Flow – Analog Design Flow
System level partition
Checking for
feasibility & testability
Spice Simulation
Schematic Entry Netlist
Verilog - A
Physical Design Connectivity Driven
Full Custom
Physical Verification (DRC / LVS)
Design spec.
PDK
(Symbol)
Spice netlist
waveform
PDK
(Pcell) GDSII
RC Extraction
Post Simulation (Back-annotation)
SPF
waveform
GDS
SPF
waveform
Chip Assembly
Placement & Route
Sub Sub Sub
RC Extraction
Full-chip Verification (DRC / LVS)
Full-chip Simulation (Back-annotation)
Tape-out & Fabrication Tape-out & Fabrication
SPEF SPEF DSPF DSPF Ext.View
4/16
Design Flow – Digital Design Flow
Synthesis
Insert DFT logic - Scan chain
- Boundary scan chain
- Memory BIST
Delay Calc., STA
RTL
Pre-layout Simulation
ATPG
Power Analysis
Cell library
Gate level
netlist(.v)
Gate level
netlist(.v)
Test pattern
SDF file
(.sdf)
Power model
(.db)
Timing model
(.db)
waveform
Power report
Design Spec.
P&R
RC Extraction
IR-drop & EM Analysis
Physical Verification (DRC/LVS)
Equivalence check
Delay Calculation, STA
Post-layout Simulation
Crosstalk Analysis
Tape out &
Fabrication
Power Analysis
Cell library
(Milkyway
&LEF)
DEF
SPF
SDF
Power model
Wave form
GDS
VCD
SPF
Power report
IR-drop report
Noise report
5/16
Design Flow – Analog Mixed Signal Design Flow
Digital Flow (Block)
Synthesis
Pre logic simulation
RTL
P&R
Physical Verification
Analog Flow (Block)
Schematic Entry
Physical Design
Analog specification
Physical Verification
Mixed Flow (Top)
AMS Post Layout Simulation
Mixed mode verification
AMS simulation
Analog Solver
Digital simulator
Connectio
n
model
Connectio
n
model
Gate level netlist
DEF, GDS
SPF
Delay calculation SDF
Pre Spice Simulation
GDS
Tr level netlist
Post logic simulation
RC Extraction
SDF STA/
Delay Calculation
RC Extraction
Post Spice Simulation
SPF
Chip Assembly
Physical verification
6/16
Design Flow – Recommend EDA Tool Version
Function EDA Tool Version
Schematic Cadence (Virtuoso) IC 5.10.41_USR6 or later IC6.1.4.500.12 or later
Circuit Simulator
Cadence (Spectre) MMSIM10.1 or later
Synopsys (HSpice) F-2011.09-SP1 or later
Mentor (Eldo) 2008.1 or later
Cadence (Ultrasim) MMSIM10.1 or later
Synopsys (Hsim) Z-2007.03-SP2 or later
Synopsys (NanoSim) A-2007.12 or later
Synopsys (FineSim-Pro) 2011.04.01 or later
Layout Editor Cadence (Virtuoso)
IC 5.10.41_USR6 or later IC6.1.4.500.12 or later
Synopsys (Laker) 32v4a or later
DRC/LVS Checker
Mentor (CalibreDRC) 2007.3_49.36 or later
Cadence (Assura) 4.1 USR2_HF9 or later
Synopsys (Hercules) Y-2006.12-SP1 or later
Parasitic Extractor
Mentor (CalibreXRC) 2009.3_24.19 or later
Cadence (Assura QRC) v9.1.4003 or later
Synopsys (Star-RCXT) F-2011.12 or later
Function EDA Tool Version
Synthesis Synopsys(Design Compiler) C-2009.06-SP3 or later
DFT (Design For Test)
Synopsys(DFT-Compiler) C-2009.06-SP3 or later
Synopsys (TetraMAX) C-2009.06-SP3 or later
Mentor (Tessent Memory BIST)
Tessent 9.2 or later
Mentor (FastScan) Tessent 9.2 or later
Logic Simulator Cadence(IES) IES 9.20.038 or later
P&R
Cadence(EDI) SOCE 81USR1 or later
Synopsys(ICC) F-2011.09-SP5 or later
Synopsys(Astro) Z-2007.03-SP6 or later
Synopsys(Talus Vortex) Talus1.0.87 or later
Power Analysis Sequence (PowerTheater) 2008.1 or later
Static Timing Analysis
Synopsys (PrimeTime) C-2009.06-SP3 or later
Equivalence Check Synopsys (Formality) C-2009.06-SP3 or later
7/16
Analog Mixed Signal Design
Analog Mixed Design Environment
DESIGN TEST BENCH
Verilo
g A
MS C
onnectio
n m
odel
(settin
g in
AD
E)
Imported Verilog Gate level netlist
DBH DK Symbol View
Verilog View (for Digital Simulation)
Schematic View
(for Analog Simulation)
Verilo
g A
MS C
onnectio
n m
odel
(settin
g in
AD
E)
DBH Analog IP Symbol View SPICE Netlist VerilogA view
Analog Block
DBH PDK Pcell
Symbol view Spectre view
Analog PWL
Stimulus
Verilog Behavioral TESTBENCH
Voltage Sources
ANALOG DIGITAL
ANALOG
Connection model is used for Converting Digital signal into Analog signal and vice versa
8/16
Detailed AMS Design Flow
Library Preparation
Library/IP STD, IO, Memory, Analog IP and so on Include schematic, layout view in DK Generate verilog view of each cell using
verilog model Make veriloga view of Analog IP
PDK Include PDK
Block implementation
Digital Block Generate gate level netlist by Synthesis
Analog Block Schematic based implementation
Top integration
Schematic Entry Digital Block: import verilog netlist and
make symbol Analog Block: make symbol Connect each block in TOP schematic
Simulation Control Make test input for AMS simulation Set simulation view each instance in HED Set connection module in ADE
Pre layout Simulation
Select simulation method in ADE AMS simulation ( Logic Simulator + Spice simulator)
Layout
Block layout Digital Block: P&R Analog Block: Custom layout
TOP layout Import gds file of digital block Connect each block Make iso ring
Post layout simulation
Parasitic Extraction and Delay Calculation • Analog: spef file by LPE Tool • Digital: sdf file by Delay Calculation Tool
Annotation • Spef and sdf file
Other procedure is same as Pre layout simulation
Physical Verification
DRC/LVS Use rule deck in PDK
9/16
PDK Symbol, spectre,
hspiceD, auCdl view
Library Preparation
Make Cadence Library (OA) for each DK and PDK
OA DB (Library Manager)
schematic
layout symbol verilog veriloga
spectre hspiceD auCdl
IO cell Schematic, Symbol
Verilog view
STD cell Schematic, Symbol
view
Import
verilog, Veriloga
symbol, verilog, veriloga
view
Verilog view creation
verilog view
verilog view
STD, IO
verilog model
IP
Verilog, veriloga model
IP
Circuit netlist Make symbol symbol
view
DBH Data
User Data
10/16
Block Implementation
Synthesis
RTL
Gate level netlist
Digital Block PDK
Import verilog
Make Symbol
Schematic Design
Make Symbol
Circuit Simulation LIBRARY(OA)
Analog Block
verilog view
schematic view
DK
Library Preparation
Liberty
verilog view
schematic view
reference
Logic Simulation
verilog model
symbol view
Spice model
LIBRARY(OA) symbol view
spectre view
spectre view
schematic view
Library Preparation
Top Integration
Top Integration
Virtuoso
Virtuoso
11/16
TOP Integration
OA (Library Manager)
NET LIST Verilog AMS
Spectre netlist HSPICE netlist
Simulation Control
ADE HED
Simulator Spectre Ultrasim NC sim Block1
Gate level netlist
Block3 schematic
IP(MEM) Verilog
behavioral model
Block3 schematic
IP(Analog) veriloga
Block2 RTL
Analog Block Digital Block
Verilog behavioral TESTBENCH
TOP Integration Virtuoso
AMS simulation
Analog stimuls Voltage source
Test Bench
AMS Design
Environment
12/16
Simulation Control
Hierarchy Editor (HED)
Analog Design Environment
(ADE)
TOP
Digital TOP
Analog TOP
IO block
Logic STD cells
Memory
Analog block
Analog IP
IOs
nmos
pmos
verilog verilog
verilog
verilog
verilog
verilog
schematic schematic
veriloga
sepectre
sepectre
schematic
Connection Module Setting
Simulator Selecting (spectre, Ultrasim, ams)
Simulator Option Control
Spice Model Including
View Binding (verilog,schematic,spectre,veriloga)
13/16
Analog Mixed Signal Simulation
Setup 1
2
3
4
Analysis
Outputs
Simulation
AMS Simulator
Model Libraries
Connect Rules
Analysis method
Output node
Spice or fast spice
Netlist and Run Options
Netlist and Run
The Procedure of AMS Simulation
Waveform
14/16
Layout – Chip Assembly
LOGIC
Analog Mux
DAC
ROSC
ADC ADC
DAC
LOGIC
ROSC Analog Mux
Custom layout
P&R
Stream in
Extract
gds file
15/16
Physical Verification
Rules
Inputs
Outputs
GDS
DRC
report
Design Rule Check
Review Report file
DRC rule deck
Setting to run
Outputs Run DRC
Rules
Inputs
Outputs
GDS
LVS
report
Layout Vs. Schematic
Review Report file
LVS
rule deck
Setting to run
Outputs Run LVS
CDL
16/16
Full Chip Level Post Layout Simulation
Post layout simulation
Other procedures are same as Pre layout simulation except annotation of SPF and SDF file.
Analog block: SPF annotation
Digital block: SDF annotation
P&R
RC Extraction
Delay Calculation, STA
DEF
SPEF
SDF
SDF generation Physical Design Connectivity Driven
Full Custom
Physical Verification (LVS)
cdl
GDSII
RC Extraction SPF
svdb
Schematic Entry
SPF generation
ADE
AMS Simulation Procedure
SPF and SDF files are annotated through ADE during AMS simulation