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An Industrial Perspective on Challenges in Nanoelectronics
Ralph K. Cavin, IIISemiconductor Research CorporationNovember 19, 2002U. CAL - Santa Barbara
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Outline
Technology Roadmap on SemiconductorsFundamentals of information processing, Fundamental limits to scaling
Message: We suggest that the benefits fromnanoelectronics research may, in the --Short term lie more with the invention of new structures, materials and processes that extend the CMOS technology platformLong term enable invention of entirely new information processing technologies
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A Bit about SRCFormed in 1982 by the SIAConducts university research on behalf of its membersOver 3000 graduates since inception
currently support ~ 800 graduate studentsMany impressive contributions to the industry technology base across a wide spectrum of areas.Significant emphasis on technology/knowledge transfer
Web site emphasizes content and is quite deepVery competitive research selection process
~ 10% of offerings are fundedOver 200 industry technical advisors participate in the planning selection and evaluation of research
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More about the SRCSRC products are research results, graduates, university infrastructure, and industry networkingSRC revenues are tied to the market performance of membersA highly qualified and experienced technical management team, about half of whom are on assignment from member companiesMembers have royalty-free internal use of IP resulting from SRC research
Licenses are negotiated as needed for background IP required to practice foreground
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International Technology Roadmap on Semiconductors
A very detailed industrial perspective on the future requirements for micro/nano electronic technologies
Goal is to continue exponential gains in performance/price for the next fifteen years
Built on worldwide consensus of leading industrial, government, and academic technologistsProvides guidance for the semiconductor industry and for academic research worldwide Content: critical requirements and judgment of status Projects that by 2016, half-pitch spacing of metal lines will be 22 nanometers and device gate lengths will be 9 nanometers
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Carver Mead’s revelation (1968) “…Gordon Moore (then at Fairchild) asked me … how small we could make transistors in an integrated circuit…In 1968, I was invited to give a talk at a workshop on semiconductor devices… I had been thinking about Gordon Moore’squestion, and decided to make it the subject of my talk. As I prepared for this event, I began to have serious doubts about my sanity. My calculations were telling me that, contrary to all the current lore in the field, we could scale down the technology such that everything got better: The circuits got more complex, they ran faster, and they took less power –WOW! That’s a violation of Murphy’s law that won’t quit! But the more I looked at the problem, the more I was convinced that the result was correct, so I went ahead and gave the talk, to hell with the Murphy! That talk provoked considerable debate, and at the time most people didn’t believe the results.”
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Chapters of ITRS 2001Glossary
ORTC
12 ITWGs : Design to Modeling & Simulation- Scope- Difficult Challenges- Technology Requirement- Potential Solutions
System Drivers
Difficult Challenges
Grand Challenges
Introduction
http://public.itrs.net
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Factory Integration
Yield Enhancement
QFP PGABGA
Printed Wiring Board
Assembly Test
Wells
Source / Drain - ExtensionIsolation
Channel Contacts
FEPLithography PIDS
Metrology Modeling
Starting Material
InterconnectDesign
ESH
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MOS Transistor Scaling(1974 to present)
S=0.7[0.5x per 2 nodes]
Pitch Gate
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Source: 2002 ITRS - Exec. Summary, ORTC
2002 ITRS Update=2001 ITRS
10
100
1000
1995 1998 2001 2004 2007 2010 2013 2016
Year of Production
Tech
nolo
gy N
ode
-DR
AM
Hal
f-Pitc
h (n
m)
2002 DRAM ½ Pitch2002 MPU/ASIC ½ Pitch
1999 ITRS DRAM Half-Pitch
2-year Node Cycle 3-year Node
Cycle
Welcome to the age of Nanotechnology
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Source: 2002 ITRS - Exec. Summary, ORTC
10
100
1000
1995 1998 2001 2004 2007 2010 2013 2016
Year of Production
Tech
nolo
gy N
ode
-DR
AM
Hal
f-Pitc
h (n
m)
2002 MPU Printed Gate Length2002 MPU Physical Gate Length
1999 ITRS MPU Gate-Length
2-year Cycle
3-year Cycle
2002 ITRS Update=2001 ITRS
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Tables’ Color Scheme
A new category has been introduced starting with 2002ITRS Update
Solutions Exist
White
YellowSolutions Being Pursued
No Known Solutions
Red
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Manufacturable Solutions Exist, and Are Being OptimizedManufacturable Solutions are Known
Manufacturable Solutions are NOT KnownInterim Solutions are Known
ITRS Technology Requirements Table Legend
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Table 2a High Performance Logic Technology Requirements—2001 ITRSCALENDAR YEAR 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016
TECHNOLOGY NODE (NM0 130 90 65 45 32 22MPU GATE LENGTH 65 53 45 37 32 30 25 18 13 9Gate Dielectric EquivalentOxide Thickness (EOT) (nm)[1]
1.45 1.35 1.35 1.15 1.05 0.95 0.85 0.65 0.50 0.45
Electrical ThicknessAdjustment Factor(Gate Depletion and QuantumEffects) (nm) [2]
0.8 0.8 0.8 0.8 0.8 0.8 0.5 0.5 0.5 0.5
Tox Electrical Equivalent(nm) [3]
2.25 2.15 2.15 1.95 1.85 1.75 1.35 1.15 1.00 0.95
Vdd (V) [4] 1.2 1.2 1.1 1.0 0.9 0.9 0.8 0.6 0.5 0.4
CMOS Scaling Challenges
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Moore’s Law I: Transistors per chip
Motivation: ↑densityspeed ↑
functionality↑
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Moore’s Law: Minimum Feature Size
500
350
250
180
130
100
70
50
35
25‘95 ‘05 ‘10‘00
1994
Min
imum
Fea
ture
Siz
e (n
m)
19971998
1999
2000
1.00E+001.00E+031.00E+061.00E+091.00E+121.00E+151.00E+181.00E+211.00E+241.00E+27
-60 -50 -40 -30 -20 -10 0 10 20 30 40
Years from 2000
Atom
s pe
r Bit IC and bio-based device
densities convergeMolecular devices
IC and BioIC and Bio--based device based device density convergedensity converge
Molecular Molecular DevicesDevices
Devices will soon be on theDevices will soon be on the“molecular” or “atomistic” scale“molecular” or “atomistic” scale
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Evolution of Electronics
Analog: TV, radio, communications...
Digital: Computation
DIGITAL INFORMATION PROCESSING
General Purpose Computer (GPC) accepts arbitrary types of data and sets of instructions to perform arbitrary tasks of transmission, processing, and storing the information
Parameters of GPC:Number of components (integration density/functional complexity)SpeedEnergy consumption
Controllable resistor
Switch
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What is Information?Information is…
…Measure of distinguishability…A function of an apriori probability of a given state or outcome among the universe of possible statesConstituents of the Information Theory
• Sender and recipient• Symbols (microstates) as elementary units of information
Information carriers
Information is physical!
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The Abacus, an ancient digital calculating device
Information is represented in digital form
Each column denotes a decimal digit
Binary representation: two possible positions for each bead
A bead in the abacus is a memory device, not a logic gate
Source: IBM
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Particle Location is an Indicator of State
1 1 0 0 1 0
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Two-well bit
a
a
Eb
Eb
w w
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Example: Field Effect Transistor
Long Channel Short Channel
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A physical system as a computing medium
We need to create a bit first. Information processing always requires physical carrier, which are material particles.
First requirement to physical realization of a bit implies creating distinguishable states within a system of such material particles.
The second requirement is conditional change of state.
The properties of distinguishability and conditional change of state are two fundamental properties of a material subsystem to represent information. These properties can be obtained by creating energy barriers in a material system.
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Designers and Users want:Highest possible integration density (n)
To keep chips size small and increase yieldsTo increase functionality
Highest possible speed (f=1/t)Speed sells!
Lowest possible power consumption (P)Decrease demands for energyThe generation of too much heat means costly cooling systems
Ideal von Neumann’s Computer
2814®®
Power density will increase
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
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Energetics of Computation
sw
bit
tnEP =
Requirements to an ideal computer:
(integration density) n=max
(switching time) tsw=min
(power) P=min
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Lowest Barrier: Distinguishability Barrier
a
a
Eb
Eb
Distinguishability D implies low probability Π of spontaneous transitions between two wells (error probability)
D=max, Π=0 D=0, Π=0.5 (50%)
Classic distinguishability:)exp(
TkE
B
bclassic −=Π
Minimum distinguishable barrier: П=0.5
)exp(21
TkE
B
b−= Eb=kTln2Shannon - von Neumann - Landauer limit
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Smallest Size: The Heisenberg Barrier
h
h
≥∆∆≥∆∆
tEpx
b
bcrit
Et
mEa
h
h
=
=
min
2
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Classic and Quantum Distinguishability @ Π=0.5
2ln
)exp(
min TkE
TkE
Bb
B
bclassic
=
−=Π
2
22min
82ln
)22exp(
maE
Eam
b
bquantum
h
h
=
−=Π
aEb
aEb
aEb
aEb
WKB: (Tunneling)
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Total Distinguishability @ Π=0.5
Generalized expression for the minimum energy barrier to create a bit
2
22min
8)2(ln2ln
makTEb
h+≈
)22
exp()22exp()exp(kT
mEakTEEam
kTE bb
bb
quantumclassicquantumclassicerror
h
h
h
+−−−+−=
=ΠΠ−Π+Π=Π
0.60.70.80.9
11.11.2
0 5 10 15 20
a, nmE b/k
T
kTln2
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Least Energy Computer
)300(5.12ln2min Knm
mkTax ===
h
)300(102.12ln2
13 KskT
htst−×==
213
2min
106.41cmgate
xn ×==
1) Minimum distance between two distinguishable states (Heisenberg)
2) Minimum state switching time (Heisenberg)
3) Maximum gate density
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Total Power Consumption at Minimal Energy per bit
2)2ln(22ln kTht
kTtEP
scsc
bbit === bitchip nPP =
261074.4
cmWPchip ×= T=300 K
The circuit would vaporize when it is turned on!
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How much heat a solid system can tolerate?
ITRS 2001 projects 93 W/cm2 for MPU in 2016
We believe that several hundred W/cm2 is close to physical limits of heat removal from a 2-dimensional solid material structure with Tmax =125°C
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Inflexion of ITRS vectors?
l is the “cell size”:
I=n-1/2
lmin=a
lMPU=(11-15)a
300 K
1.00E-13
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1 10 100 1000
l, nm
t, s
Memory
Logic
l
Heisenberg barrier
Heisenberg barrier
P=100 W/cm2
1
2
4
3
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‘Ultimate” and “Optimum” parameters
Switch size Switching time Integration density Frequency 1.5 nm 1 ns 5x1013 cm-2 1 GHz 54 nm 1 ps 3.4x1010 cm-2 1 THz “Optimum” parameters: ITRS vector for logic intercepting the energy barrier 35 nm 2 ps 8x1010 cm-2 500 GHz “Optimum” parameters: ITRS vector for memory intercepting the energy barrier 6 nm 0.1 ns 2.7x1012 cm-2 10 GHz
12
3
4
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Implications for Nanoelectronics
Scaling to molecular dimensions may not yield performance increases
We will be forced to trade-off between speed and density
Optimal dimensions (depending on speed/density trade-offs) for electronic switches should range between 5 and 50 nm, and this may be achievable with silicon technology
Within the scope of ITRS projections
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Fundamentals of Heat Removal
A quote from anonymous scientists working at the frontiers of nanoelectronics: “ Heat removal is not an issue. Simply, engineers must invent better technologies for heat removal and cooling ”.
Three fundamentals of heat removal:
1)The Newton's Law of Cooling: q=h(Th-Ta) (h-heat transfer coefficient)
2) The Ambient: Ta=300 K !!!
3) The Carnot’s theorem: −−= Q
TTTW
c
cacool
Heat to be removed
Work to be done
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Carnot’s Refrigerator and Cryogenic Computation
−−= Q
TTTW
c
cacool
Min. total power needed to run a 100 W chip:
at 77 K - 300 W
at 4.2 K - 7 kW
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Energetics of Computation II
In 1999, computers and the Internet consumed approximately 8% of the world’s electric power. Current forecasts suggest that these sectors will consume up to 50% of the world’s electric power by 2009. (May be overstated but a concern none-the-less!)
(H. Sasaki, Chairman of the Board, NEC Corp.), “Future Platform for Mobile Communication”, ISQED March 27, 2001 )
0% 20% 40% 60% 80% 100%
2009
1999
0% 20% 40% 60% 80% 100%
ServersPCsRoutersOthers
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A question – What to do?
Substrate
Gate
Source Drain
IBM CNTFET
Silicon MOSFET
Bell Labs Molecular FET?
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Emerging Research DevicesEvaluation Criteria
Performance - will the technology extend the performance of microelectronics by 100X beyond the 32 nm node?Scalability – how many generations will a chosen technology survive?Universality - does a chosen technology have the potential to build a new platform?Manufacturability - will the technology sustain the cost per function curve reducing the cost/function per year?Impact on Infrastructure - will a chosen technology require drastic changes in existing infrastructure?Compatibility with CMOS (design & manufacturing)
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What to do? (Cont’d)
Quantum Computer
Cellular Non Linear NetworkIBM CNFET
Bell Labs Molecular FET
Conventional von Neumann Architecture
New Information Processing Architectures
?
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Neuromorphic ComputingImplies computational schemes and systems resembling operation of human brains.
The potential capabilities of neuromorphic computers could be close to those of the brain, thus enabling e.g. artificial intelligence
Properties of brain:Mass – 1.5 kgVolume – 1.5 lEnergy consumption – ~10 WInformation stored – 1e14 bits1e13 bits/s
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A Question: What to do?
What is the best direction to pursue for alternate information processing technologies (e.g., carbon nanotubes, molecular electronics, etc.)?
Replicate CMOS technology with new switches, gates, etc., directly one for one sustaining the von Neumann architecture?
OrEventually invent and develop a completely new information processing technology and systems architecture?We think that a two-faceted approach makes sense
Develop new nano-engineered materials and processes for the CMOS technology platform to push CMOS scaling as far as possibleBegin explorations for new device paradigms based on principles other than particle position/transfer
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Thesis
Basic Research in Solid State Materials in the 1930’s and 1940’s created the foundation for the Electronic CenturyWe have successfully utilized this research investment to create much of modern information technologyWe need to replenish the knowledge base because the end of evolution in solid state electronics is foreseeableWe are significantly under-investing in the physical sciences that support the semiconductor industry
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Central Breakthroughs:
•Band structure concept
•Minute amounts of impurities control properties
•Advances in purification and high quality crystal growth of Si and Ge
Government funded research in solid state physics in 1930’s and 40’s laid the foundation
Beginning about 1946, we began to utilize this knowledge base
Bipolar transistor 1948
Field effect transistor 1953
LED 1955
Tunnel diode 1957
IC 1959
Laser 1960
Most basic semiconductor devices were demonstrated within 12 years
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For about four decades now we have exploited (mined) our investment in materials and we have continuously evolved the devices based on this understanding
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2002 - Semiconductor industry is pumping down last resources
Possible to discover new well?
To get from today to the end of CMOS, we must overcome many problems in science where new understanding is needed
We need to be about the process of creating a new science basis for the devices beyond evolution
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Old and New resources: What are the parallels in basic physical concepts needed?
1952 AchievementsBulk band structure of solids
Doping
Crystal growth
2002 Needsgeometry dependent energetic structure of nanostructures
precise location of atoms
self organization of matter in complex structures
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What should our research address? Examples
Spin Measurements, e.g. quantum Hall effect
Geometry related quantum effects, e.g. quantum wedge
Precise location of atoms
Rs →r
P+ P+
B-
Si
Source Drain
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Example Research Questions for Functional Materials
Intelligent machines, e.g. molecular networksComplex nanostructures: Synthesis and properties, e.g.
quantum wedge, spin devicesQuantum mechanics and Quantum electrostatics, e.g.
Quantum EntanglementCorrelated tunnel transitions
Mechanical properties of materials at nanoscale
NeuromorphicInformation Processing
Quantum Information Technologies
NEMS
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ConclusionsThe first impacts from nano-engineered materials are likely to be in the area of improving the performance of CMOS devices and interconnectsFundamental considerations suggest that the potential benefits from replacing CMOS devices with new types of electron transport devices may be limitedThe exploration of alternative approaches to von Neumann type computing, such as brain or Reversible/Quantum Computation, is becoming a strategic imperative.
We need a concerted effort in this area because of the long lead times for the introduction of radically new technologies
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Back-Up Slides
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NanoFloating gate memory
SiO2
n+ n+
memory node
Si
GateBefore filling
After filling
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Si nanocrystals memory
Formation of Si nanocrystals in SiO2 through spontaneous decomposition during CVD deposition of SiO2
Size of Si nanocrystals ~5 nm
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Nanocrystals MemoryLow write voltage
Field enhancement at nanodots
Improved enduranceWrite current density is uniformly distributed along the nanodotsWrite current per nanodot is self-limited by Coulomb blockade
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Nanocrystals Memory
Read time: <80 ns
Write time: 100 ns
Retention: >1 week
Erase/Write cycles: 109
