Download - Al2ed chapter12
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MIPS Processor
Chapter 12
S. Dandamudi
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 2
Outline
• Introduction
• Evolution of CISC Processors
• RISC Design Principles
• MIPS Architecture
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 3
Introduction
• CISC Complex instruction set
» Pentium is the most popular example
• RISC Simple instructions
» Reduced complexity
Modern processors use this design philosophy» PowerPC, MIPS, SPARC, Intel Itanium
– Borrow some features from CISC
No precise definition» We can identify some common characteristics
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 4
Evolution of CISC Processors
• Motivation to efficiently use expensive resources Processor Memory
• High density code Complex instructions
» Hardware complexity is handled by microprogramming
» Microprogramming is also helpful to
– Reduce the impact of memory access latency
– Offers flexibilityLow-cost members of the same family
Tailored to high-level language constructs
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 5
Evolution of CISC Designs (cont’d)
CISC RISC
VAX 11/780
Intel 486 MIPS R4000
# instructions 303 235 94
Addr. modes 22 11 1
Inst. size (bytes) 2-57 1-12 4
GP registers 16 8 32
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 6
Evolution of CISC Designs (cont’d)
Example Autoincrement addressing mode of VAX
» Performs the following actions:
(R2) = (R2) + R3; R2 = R2 + 1
RISC equivalent
R4 = (R2)
R4 = R4 + R3
(R2) = R4
R2 = R2 + 1
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 7
Why RISC?
• Simple instructions Complex instructions are mostly ignored by compilers
» Due to semantic gap
• Few data types Complex data structures are used relatively infrequently Better to support a few simple data types efficiently
» Synthesize complex ones
• Simple addressing modes Complex addressing modes lead to variable length
instructions» Lead to inefficient instruction decoding and scheduling
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 8
Why RISC? (cont’d)
• Large register set Efficient support for procedure calls and returns
» Patterson and Sequin’s study
– Procedure call/return: 1215% of HLL statementsConstitute 3133% of machine language instructionsGenerate nearly half (45%) of memory references
Small activation record» Tanenbaum’s study
– Only 1.25% of the calls have more than 6 arguments
– More than 93% have less than 6 local scalar variables
– Large register set can avoid memory references
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 9
RISC Design Principles
• Simple operations Simple instructions that can execute in one cycle
» Operations can be hardwired (see next figure)
• Register-to-register operations Only load and store operations access memory Rest of the operations on a register-to-register basis
• Simple addressing modes A few addressing modes (1 or 2)
• Large number of registers Needed to support register-to-register operations Minimize the procedure call and return overhead
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 10
RISC Design Principles (cont’d)
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 11
RISC Design Principles (cont’d)
• Fixed-length instructions Facilitates efficient instruction execution
• Simple instruction format Fixed boundaries for various fields
» opcode, source operands,…
• Other features Tend to use Harvard architecture Pipelining is visible at the architecture level
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 12
MIPS Architecture
• Registers 32 general-purpose
» Identified as $0, $1, …,$31
» Register $0 is hardwired to zero
– Used when zero operand is needed
» Register $31 is used as the link register
– Used to store the return address of a procedure
A Program counter (PC) 2 special-purpose
» HI and LO registers
– Used in multiply and divide operations
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 13
MIPS Architecture (cont’d)
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 14
MIPS Architecture (cont’d)
MIPS registers and their conventional usage
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 15
MIPS Architecture (cont’d)
MIPS addressing modes Bare machine supports only a single addressing mode
disp(Rx)
Virtual machine provides several additional addressing modes
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2005
To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer, 2005.
S. Dandamudi Chapter 12: Page 16
Memory Usage
Placement of segments allows sharing of unused memory by both data and stack segments
Last slide