Ben-Gurion University of the Negev
Faculty of Engineering Science Dept. of Electrical and Computer Engineering
ADVANCED COMPUTER LABORATORTY
4693 - 1- 361
FPGA–FINAL PROJECT
MATH TEACHINGSIMPLE
Supervisor: Alex Reisenson
Students: Bar-or Sagi 031424013 Nitzani Nir 040312738
2
Abstract............................................................................................................................... 3
Section 1: the design operation ......................................................................................... 4
The modules structure:.................................................................................................... 4 SYSTEM:.................................................................................................................... 4 RESULTS: .................................................................................................................. 4 LCD: ........................................................................................................................... 4 LCD_DataToLine1: .................................................................................................... 4 LCD_DataToLine2: .................................................................................................... 4 NumTo7Seg: ............................................................................................................... 4 SevenSegInterface: ..................................................................................................... 4
Section 2: The design modules .......................................................................................... 7
Module: SYSTEM .......................................................................................................... 7 Module: Counter2Bit .................................................................................................... 11 Module: SwitchControl................................................................................................. 11 Module: TrueIndicator .................................................................................................. 12 Module: Reset_Delay.................................................................................................... 12 Module: SevenSegInterface .......................................................................................... 13 Module: NumTo7Seg.................................................................................................... 16 Module: AnswerTo7Seg_LSB...................................................................................... 17 Module: AnswerTo7Seg_MSB..................................................................................... 18 Module: Results ............................................................................................................ 19 Module: counter1 .......................................................................................................... 21 Module: counter2 .......................................................................................................... 21 Module: counter3 .......................................................................................................... 22 Module: counter4 .......................................................................................................... 22 Module: XOR6Bit......................................................................................................... 23 Module: decoder2_4 ..................................................................................................... 23 Module: MUX12_6....................................................................................................... 24 Module: DelayCounter.................................................................................................. 24 Module: LCD................................................................................................................ 25 Module: LCD_TEST .................................................................................................... 28 Module: LCD_Controller.............................................................................................. 29 Module: LCD _DataToLine1........................................................................................ 30 Module: LCD _DataToLine2........................................................................................ 32 Module: binary_to_BCD .............................................................................................. 33 Module: SRAM............................................................................................................. 34 Module: Counter5Bit .................................................................................................... 36
Section 3: Snapshots ........................................................................................................ 37
The DE2 components:................................................................................................... 37 Wrong answer ............................................................................................................... 38 Right answer ................................................................................................................. 39 LCD display .................................................................................................................. 40
Section 4: remarks ........................................................................................................... 41
3
Abstract
The goal of this project is to learn FPGA designing by developing a FPGA based game,
for teaching simple math. After examining several different ways of implementation, we
have decided on the following parameters:
1. A simple math question will be displayed at the upper line of the LCD.
2. 4 different answers will be displayed at the lower line of the LCD.
3. The user will select one of the answers by pressing one of the four push bottons.
4. If the answer is correct - the word "good" will be displayed on the 7-segment
display, and the green LEDs will light for 3 seconds.
5. No matter what the user selected, the question on the upper line of the LCD will
update to the next question, and the correct answer will be displayed on the 7-
Segment display.
6. After the user has answered all the questions in the memory, the game will start
from the beginning. This time the position of the correct answer (in any question)
will be different from the previous instance.
4
Section 1: the design operation
The modules structure:
The design is modular: several "big" modules which include several "small" modules.
SYSTEM: • MAIN SECTION: SwitchControl, Counter2Bit, TrueIndicator
• RESULTS SECTION: Results
• LCD SECTION: Reset_Delay, LCD, DelayCounter
• 7-SEGMENT INTERFACE SECTION: SevenSegInterface
• SRAM INTERFACE SECTION: Counter5Bit, SRAM
RESULTS: • counter1, counter2, counter3, counter4, XOR6Bit, decoder2_4, MUX12_6
, DelayCounter
LCD: • LCD_TEST, LCD_DataToLine1, LCD_DataToLine2
LCD_DataToLine1: • binary_to_BCD
LCD_DataToLine2: • binary_to_BCD
NumTo7Seg: • binary_to_BCD
SevenSegInterface: • AnswerTo7Seg_LSB
• AnswerTo7Seg_MSB
• NumTo7Seg
• TrueIndicator
5
The design operation:
After programming the FPGA or executing reset, the system is ready to start. In this
stage, any press on one of the four push bottoms will generate random position to the
correct answer. This is made the Counter2Bit. The position of the correct answer is saved
in special register so the Results module will be able to use it.
The Results module generates four different answers, depending on the correct one. Four
different counters inside the Results module generate four different values. Those values
goes through a XOR gate together with the correct answer so four different answer are
generated. By using the position value from the Counter2Bit output, the correct answer is
displayed along with three false ones.
In this stage, the system waits for a input from the user. When the user select an answer,
the SwitchControl module starts to operate and generate indication pulse (whether the
answer is correct or not). This pulse is the basic of the feedback display.
If the correct answer has been chosen, the user will see the correct answer at the left side
of 7- Segment display, the word "good" at the right side of 7- Segment display and the
green LEDs lights up.
If the answer is not correct, the user will only see the correct answer at the left side of 7-
Segment display.
After selecting an answer, and no matter what the user has selected, the system will
display the next question.
The SRAM contains the question and the true answer. In this game we used 32 words,
each of 32 Bits (32 different questions). The question and answer is selected by a 5 bits
counter, triggered by the user press – every press of the push bottoms increases the
counter's value. On overflow, the count starts all over again and the first question will be
displayed, so the game starts from the beginning. As described earlier, when the game
starts from the beginning, if by an overflow or due to a reset, the incorrect answers will
be displayed at a different location on the LCD display and they will be different from
those of the other instance.
6The design flow chart:
Figure 1.1: the design flow chart
Init: Press any key to start
The LCD displays a question and four different answers. The user
select one of them.
Is the answer correct?
A positive feedback will be displayed to the user.
The correct answer will appear on the 7-Segment display
yes no
7
Section 2: The design modules
Module: SYSTEM
The main module. Bundles the modules and interface with the peripherals devices (the
LCD display, the 7-segment display, the LEDs, the push buttons, the switches and the
clock).
SYSTEM
clockclock
resetreset
press[3..0]press[3..0]
GreenLeds[8..0]GreenLeds[8..0]
RedLEDS[17..0]RedLEDS[17..0]
sev en_seg0[6..0]sev en_seg0[6..0]
sev en_seg1[6..0]sev en_seg1[6..0]
sev en_seg2[6..0]sev en_seg2[6..0]
sev en_seg3[6..0]sev en_seg3[6..0]
sev en_seg4[6..0]sev en_seg4[6..0]
sev en_seg5[6..0]sev en_seg5[6..0]
sev en_seg6[6..0]sev en_seg6[6..0]
sev en_seg7[6..0]sev en_seg7[6..0]
LCD_ONLCD_ON
LCD_BLONLCD_BLON
LCD_RWLCD_RW
LCD_ENLCD_EN
LCD_RSLCD_RS
LCD_DATA[7..0]LCD_DATA[7..0]
. Figure 2.0: SYSTEM I/O diagram
8
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Connected to the right switch
Input Press 4 Connected to the push buttons
Output GreenLeds 9 Connected to the green LEDs
Output RedLeds 9 Connected to the green LEDs
Output seven_seg0 7 Connected to the 7-Segment display
Output seven_seg1 7 Connected to the 7-Segment display
Output seven_seg2 7 Connected to the 7-Segment display
Output seven_seg3 7 Connected to the 7-Segment display
Output seven_seg4 7 Connected to the 7-Segment display
Output seven_seg5 7 Connected to the 7-Segment display
Output seven_seg6 7 Connected to the 7-Segment display
Output seven_seg7 7 Connected to the 7-Segment display
Output LCD_ON 1 LCD Power ON/OFF
Output LCD_BLON 1 LCD Back Light ON/OFF
Output LCD_RW 1 LCD Read/Write Select
Output LCD_EN 1 LCD Enable
Output LCD_RS 1 LCD Command/Data Select
Inout LCD_DATA 8 LCD Data bus 8 bits
Table 2.1: SYSTEM I/O ports
9
VCC
cloc
kIN
PUT
VCC
rese
tIN
PUT
VCC
pres
s[3:
0]IN
PUT
seve
n_se
g7O
UTP
UT
seve
n_se
g6O
UTP
UT
seve
n_se
g5O
UTP
UT
seve
n_se
g4O
UTP
UT
seve
n_se
g3O
UTP
UT
seve
n_se
g2O
UTP
UT
seve
n_se
g1O
UTP
UT
seve
n_se
g0O
UTP
UT
LCD
_ON
OU
TPU
T
LCD
_BLO
NO
UTP
UT
LCD
_RW
OU
TPU
T
LCD
_EN
OU
TPU
T
LCD
_RS
OU
TPU
T
Red
LED
s[17
:0]
OU
TPU
T
Gre
enLe
ds[8
:0]
OU
TPU
T
VCC
LCD
_DAT
ABI
DIR
clock
reset
en
sel[1..0]
res[5..0]
out[31..0]
Results
inst6
clock
reset
out
TrueIndicator
inst5
iCLK
iRESET
reset
oRESET
Reset_Delay
inst7
key s[3..0]
counter2bit[1..0]
out
SwitchControl
inst4
clock
reset
en
out[1..0]
Counter2Bit
inst3
NAND4
inst
clock
en
out
Delay Counter
inst8
data0x[8..0]
data1x[8..0]
sel
result[8..0]
MUX9Bit
.
CLOCK_50
LINE1[31..0]
IN3[7..0]
IN2[7..0]
IN1[7..0]
IN0[7..0]
reset
LCD_ON
LCD_BLON
LCD_RW
LCD_EN
LCD_RS
LCD_DATA[7..0]
LCD
inst9
clock
enable
location[1..0]
numbers[31..0]
TrueAnswer
reset
sev en_seg0[6..0]
sev en_seg1[6..0]
sev en_seg2[6..0]
sev en_seg3[6..0]
sev en_seg4[6..0]
sev en_seg5[6..0]
sev en_seg6[6..0]
sev en_seg7[6..0]
Sev enSegInterf ace
inst10
clock
reset
out[4..0]
Counter5Bit
inst11
address[4..0]
clock
q[31..0]
SRAM
inst12
OR2
inst13
press[0]
press[1]
press[2]
press[3]
ResultOut[31:24]ResultOut[23:16]ResultOut[15:8]ResultOut[7:0]
<<R
esul
tOut
[31:
0]>>
dela
yToL
CD
oreset
enable
EnableOrRESET
<<SRAM_out[31:0]>>
SRAM_out[13:8]
'000000000'
'011111111'
Tru
eOrF
alse
'0'
Figure 2.1a: detailed SYSTEM block diagram
10
Figure 2.1b: simple SYSTEM block diagram
Results
Generates random results in addition to
the correct one
SRAM
Holds the questions and the correct
answer
Push buttons
7-Segment interface
To 7-Seg display
LCD interface
To LCD
Create Enable, correct answer location, correct
answer indication, the time to display the
correct answer
To Green LEDs
Switch buttons
SW0
rese
t
11
Module: Counter2Bit
A 2 bit counter, used for choosing the location of the right answer on the LCD
Counter2Bit
clockclock
resetreset
enen
out[1..0]out[1..0]
. Figure 2.3 Counter2Bit I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Initialize to 0
Input en 1 when drops to 0, capture the counted
number and send to output
Output out 2 Module output
Table 2.2: Counter2Bit I/O ports
Module: SwitchControl
Compares the Counter2Bit result with the Users answer and outputs ‘1’ if it match.
SwitchControl
key s[3..0]key s[3..0]
counter2bit[1..0]counter2bit[1..0]
outout
. Figure 2.4: SwitchControl I/O diagram
I/O Name Size [bits] Remarks
Input keys 4 The push buttons
Input counter2bit 2 The location where the right answer is
Output out 1
Table 2.3: SwitchControl I/O ports
12
Module: TrueIndicator
Outputs a pulse of ‘1’ for several seconds when reset is received.
TrueIndicator
clockclock
resetreset
outout
. Figure 2.5: TrueIndicator I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Starts the pulse
Output out 1
Table 2.4: TrueIndicator I/O ports
Module: Reset_Delay
When iRESET or reset are received, a ‘0’ pulse is generated for several clocks
Reset_Delay
iCLKiCLK
iRESETiRESET
resetreset
oRESEToRESET
. Figure 2.6: Reset_Delay I/O diagram
I/O Name Size [bits] Remarks
Input iCLK 1 Module clock
Input iRESET 1
Input reset 1
Output oRESET 1 ‘0’ pulse
Table 2.5: Reset_Delay I/O ports
13
Module: SevenSegInterface
If the right answer is pressed, the word “good” is shown on the 7-segment display, as
well as the right answer. If the wrong answer is selected, only the right answer is shown
on the 7-segment display.
The answers vector is received from results module, as well as the location of the right
answer. Then the right answer goes through a binary to 7-segment conversion using the
NumTo7Seg module. The new 7-segment number is then displayed on the display using
the AnswerTo7Seg_MSB module.
When the right answer is pressed, the input “TrueAnswer” activate the
AnswerTo7Seg_MSB module, which displays “good” on the display.
Sev enSegInterf ace
clockclock
enableenable
location[1..0]location[1..0]
numbers[31..0]numbers[31..0]
TrueAnswerTrueAnswer
resetreset
sev en_seg0[6..0]sev en_seg0[6..0]
sev en_seg1[6..0]sev en_seg1[6..0]
sev en_seg2[6..0]sev en_seg2[6..0]
sev en_seg3[6..0]sev en_seg3[6..0]
sev en_seg4[6..0]sev en_seg4[6..0]
sev en_seg5[6..0]sev en_seg5[6..0]
sev en_seg6[6..0]sev en_seg6[6..0]
sev en_seg7[6..0]sev en_seg7[6..0]
. Figure 2.7: SevenSegInterface I/O diagram
14
I/O Name Size [bits] Remarks
Input clock 1
Input enable 1
Input location 2 Location of the right answer
Input numbers 32 Answers vector
Input TrueAnswer 1 Indicate when the right answer was pressed
Input Reset 1
Output seven_seg0 7 A 7-Segment digit
Output seven_seg1 7 A 7-Segment digit
Output seven_seg2 7 A 7-Segment digit
Output seven_seg3 7 A 7-Segment digit
Output seven_seg4 7 A 7-Segment digit
Output seven_seg5 7 A 7-Segment digit
Output seven_seg6 7 A 7-Segment digit
Output seven_seg7 7 A 7-Segment digit
Table 2.6: SevenSegInterface I/O ports
15
VCC
rese
tIN
PUT
VCC
cloc
kIN
PUT
VCC
num
bers
[31:
0]IN
PUT
VCC
loca
tion[
1:0]
INPU
T
VCC
Tru
eAns
wer
INPU
T
VCC
enab
leIN
PUT
seve
n-se
g0O
UTP
UT
seve
n-se
g1O
UTP
UT
seve
n-se
g2O
UTP
UT
seve
n-se
g3O
UTP
UT
seve
n-se
g4O
UTP
UT
seve
n-se
g5O
UTP
UT
seve
n-se
g6O
UTP
UT
seve
n-se
g7O
UTP
UT
inou
t0[6
..0]
out1
[6..
0]
out2
[6..
0]
out3
[6..
0]
Ans
wer
To7
Seg
_LS
B
seve
nSeg
LSBin
Dis
p7[6
..0]
Dis
p6[6
..0]
out4
[6..
0]
out5
[6..
0]
out6
[6..
0]
out7
[6..
0]
Ans
wer
To7
Seg
_MS
B
seve
nSeg
MS
B
Location[1..0]
in[31..0]
ONES[6..0]
TENS[6..0]
NumTo7Seg
numTo7
clock
reset
out
TrueIndicator
true7seg
clock
data[5..0]
q[5..0]
FF
inst
clock
data[5..0]
q[5..0]
FF
inst1
Figure 2.8: SevenSegInterface block diagram
16
Module: NumTo7Seg
Receives the answers vector, and the location of the right answer. It then converts the
right answer from a binary mode into a two digits BCD number, follows a conversion
into 7-Segment digits.
NumTo7Seg
Location[1..0]Location[1..0]
in[31..0]in[31..0]
ONES[6..0]ONES[6..0]
TENS[6..0]TENS[6..0]
. Figure 2.9: NumTo7Seg I/O diagram
I/O Name Size [bits] Remarks
Input location 2 Location of the right answer
Output In 32 The answers vector
Output ONES 7 The unity digit
Output TENS 7 The tens digit
Table 2.7: NumTo7Seg I/O ports
17
VCC
Loca
tion
INPU
T
VCC
in[3
1:0]
INPU
T
TE
NS[
7:0]
OU
TPU
T
ON
ES[7
:0]
OU
TPU
T
data3x[7..0]data2x[7..0]data1x[7..0]data0x[7..0]
sel[1..0]
result[7..0]
lpm_mux0
mux
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
inst1
data[3..0]
eq0eq1eq2eq3eq4eq5eq6eq7eq8eq9eq10
lpm_decode0
ONES
data[3..0]
eq0eq1eq2eq3eq4eq5eq6eq7eq8eq9eq10
lpm_decode0
TENS
in[7:0]
in[15:8]
in[23:16]
in[31:24]
Figure 2.10: NumTo7Seg block diagram
Module: AnswerTo7Seg_LSB
Shows a “good” message when the right answer is selected
AnswerTo7Seg_LSB
inin out0[6..0]out0[6..0]
out1[6..0]out1[6..0]
out2[6..0]out2[6..0]
out3[6..0]out3[6..0]
. Figure 2.11: AnswerTo7Seg_LSB I/O diagram
18I/O Name Size [bits] Remarks
Input in 1 Indicate when the right answer was pressed
Output out0 7 The LSB digit on the 7-Seg display
Output out1 7 Digit 1 on the 7-Seg display
Output out2 7 Digit 2 on the 7-Seg display
Output out2 7 Digit 3 on the 7-Seg display
Table 2.8: AnswerTo7Seg_LSB I/O ports
Module: AnswerTo7Seg_MSB
Shows the right answer when any answer is pressed.
AnswerTo7Seg_MSB
inin
Disp7[6..0]Disp7[6..0]
Disp6[6..0]Disp6[6..0]
out4[6..0]out4[6..0]
out5[6..0]out5[6..0]
out6[6..0]out6[6..0]
out7[6..0]out7[6..0]
. Figure 2.12: AnswerTo7Seg_MSB I/O diagram
I/O Name Size [bits] Remarks
Input in 1 Indicate when an answer was pressed
Input Disp7 7 A 7-Seg digit to display
Input Disp6 7 A 7-Seg digit to display
Output out0 7 The LSB digit on the 7-Seg display
Output out1 7 Digit 1 on the 7-Seg display
Output out2 7 Digit 2 on the 7-Seg display
Output out2 7 Digit 3 on the 7-Seg display
Table 2.9: AnswerTo7Seg_MSB I/O ports
19
Module: Results
The right answer is received from the memory, together with a location in which to
shows the answer on the LCD display (from counter2Bit). 4 different random numbers
are generated, using 4 different counters. The answer is placed in its location. The other 3
locations are filled with random numbers, generated by using a XOR operation on the
answer and on the results from the corresponding counters. Each counter counts in a
different range, thus the 3 random numbers are different from each other and from the
answer. At the end of the process the 4 results are stored in the output register.
Results
clockclock
resetreset
enen
sel[1..0]sel[1..0]
res[5..0]res[5..0]
out[31..0]out[31..0]
. Figure 2.13: Results I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1
Input en 1
Input sel 2 Chose the answer location
Input res 6 The right answer
Output out 32 Module output
Table 2.10: Result I/O ports
20
VCC
cloc
kIN
PUT
VCC
enIN
PUT
VCC
rese
tIN
PUT
VCC
res
INPU
T
VCC
sel
INPU
T
out
OU
TPU
Tclock
reset
en
out[5..0]
counter1
inst
clock
reset
en
out[5..0]
counter2
inst1
clock
reset
en
out[5..0]
counter3
inst2
clock
reset
en
out[5..0]
counter4
inst3
in1[5..0]
in2[5..0]
out[5..0]
XOR6Bit
inst4
in1[5..0]
in2[5..0]
out[5..0]
XOR6Bit
inst5
in1[5..0]
in2[5..0]
out[5..0]
XOR6Bit
inst6
in1[5..0]
in2[5..0]
out[5..0]
XOR6Bit
inst7
in1[5..0]
MEM_in[5..0]
sel
out[5..0]
MUX12_6
inst8
in1[5..0]
MEM_in[5..0]
sel
out[5..0]
MUX12_6
inst9
in1[5..0]
MEM_in[5..0]
sel
out[5..0]
MUX12_6
inst10
in1[5..0]
MEM_in[5..0]
sel
out[5..0]
MUX12_6
inst11
clock
en
out
Delay Counter
inst13
in[1..0]out[3..0]
decoder2_4
inst12
OR2
or
clock
data[31..0]
q[31..0]
FF32
inst21
3
2
1
0
res
<<de
c_ou
t[3:0
]>>
<<se
l>>
en cloc
k
rese
t
Figure 2.14: Results block diagram
21
Module: counter1
A 1 to 15, 6 bit counter. Used for generating a random answer.
counter1
clockclock
resetreset
enen
out[5..0]out[5..0]
. Figure 2.15: counter1 I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Initialize to 1
Input en 1 when en=1, capture the counted
number and send to output
Output out 6 Module output
Table 2.11: counter1 I/O ports
Module: counter2
A 16 to 31, 6 bit counter. Used for generating a random answer.
counter2
clockclock
resetreset
enen
out[5..0]out[5..0]
. Figure 2.16: counter2 I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Initialize to 16
Input en 1 when en=1, capture the counted
number and send to output
Output out 6 Module output
Table 2.12: counter2 I/O ports
22
Module: counter3
A 32 to 47, 6 bit counter. Used for generating a random answer.
counter3
clockclock
resetreset
enen
out[5..0]out[5..0]
. Figure 2.17: counter3 I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Initialize to 32
Input en 1 when en=1, capture the counted
number and send to output
Output out 6 Module output
Table 2.13: counter3 I/O ports
Module: counter4
A 48 to 63, 6 bit counter. Used for generating a random answer.
counter4
clockclock
resetreset
enen
out[5..0]out[5..0]
. Figure 2.18: counter4 I/O diagram
I/O Name Size [bits] Remarks
Input clock 1 Module clock
Input reset 1 Initialize to 48
Input en 1 when en=1, capture the counted
number and send to output
Output out 6 Module output
Table 2.14: counter4 I/O ports
23
Module: XOR6Bit
Bit wise, 6 bit XOR
XOR6Bit
in1[5..0]in1[5..0]
in2[5..0]in2[5..0]
out[5..0]out[5..0]
. Figure 2.19: XOR6Bit I/O diagram
I/O Name Size [bits]
Input In1 6
Input In2 6
Output out 6
Table 2.15: XOR6Bit I/O ports
Module: decoder2_4
2 bit to 4 bit decoder. Used in the Results module for converting the counter2Bit binary
result into a location in which to place the answer.
decoder2_4
in[1..0]in[1..0] out[3..0]out[3..0]
. Figure 2.20: decoder2_4 I/O diagram
in out
00 0001
01 0010
10 0100
11 1000
Table 2.16: decoder2_4 true table
24
Module: MUX12_6
A 6 bit MUX.
MUX12_6
in1[5..0]in1[5..0]
MEM_in[5..0]MEM_in[5..0]
selsel
out[5..0]out[5..0]
. Figure 2.21: MUX 12_6 I/O diagram
I/O Name Size [bits] Remarks
Input in1 6
Input MEM_in 6
Input sel 6 Select which input is directed to the output
Output out 6
Table 2.17: XOR6Bit I/O ports
Module: DelayCounter
Outputs a pulse of 1 clock length with a delay of 6 clocks after ‘en’ was received
Delay Counter
clockclock
enen
outout
. Figure 2.22: DelayCounter I/O diagram
I/O Name Size [bits]
Input clock 1
Input en 1
Output out 1
Table 2.18: DelayCounter I/O ports
25
Module: LCD
This module, together with LCD_TEST module and LCD_Controller module are based
on the DE2 development and Education Board default program, given with the boards
“DE2 System” CD, on “..\DE2_demonstrations\DE2_Default” library. The given design
triggers the LCD display so a constant massage is shown, unlike this design where the
display is constantly changing.
The main module of the LCD interface. Bundles all the LCD corresponding modules, and
interface with the LCD display. The numbers of the exercise, along with the operand are
received from the memory (SRAM) module. Those parameters are sent to the first line of
the display by using the LCD_DataToLine1 module, which displays them as: “ (num1)
(operand) (num2) = ? “. The 4 answers from the Results module are sent to the second
line of the display, by using the LCD_DataToLine2 module.
LCD
CLOCK_50CLOCK_50
LINE1[31..0]LINE1[31..0]
IN3[7..0]IN3[7..0]
IN2[7..0]IN2[7..0]
IN1[7..0]IN1[7..0]
IN0[7..0]IN0[7..0]
resetreset
LCD_ONLCD_ON
LCD_BLONLCD_BLON
LCD_RWLCD_RW
LCD_ENLCD_EN
LCD_RSLCD_RS
LCD_DATA[7..0]LCD_DATA[7..0]
. Figure 2.25: LCD I/O diagram
26
I/O Name Size [bits] Remarks
Input CLOCK_50 1 System clock
Input LINE1 32 First line of LCD
Input IN0 8 Input data of first answer
Input IN1 8 Input data of second answer
Input IN2 8 Input data of third answer
Input IN3 8 Input data of fourth answer
Input reset 1
Output LCD_ON 1 Power on LCD
Output LCD_BLON 1 Power on back light of LCD
Output LCD_DATA 8 Output data to LCD controller
Output LCD_RW 1 Read / Write to LCD controller
Output LCD_EN 1 Enable to LCD controller
Output LCD_RS 1 Reset to LCD controller
Table 2.21: LCD I/O ports
27
iCLK
iRST_N
NUM1_1[8..0]
NUM1_0[8..0]
NUM2_1[8..0]
NUM2_0[8..0]
OPERAND[8..0]
ANS3_1[8..0]
ANS3_0[8..0]
ANS2_1[8..0]
ANS2_0[8..0]
ANS1_1[8..0]
ANS1_0[8..0]
ANS0_1[8..0]
ANS0_0[8..0]
LCD_DATA[7..0]
LCD_RW
LCD_EN
LCD_RS
LCD_TEST
inst2
LCD_INTIAL 0LCD_LINE1 5LCD_CH_LINELCD_LINE2LUT_SIZE
Parameter Value
IN[31..0]NUM3_1[8..0]
NUM3_0[8..0]
NUM2_1[8..0]
NUM2_0[8..0]
NUM1_1[8..0]
NUM1_0[8..0]
NUM0_1[8..0]
NUM0_0[8..0]
LCD_DataToLine2
inst1
IN[31..0]NUM2_1[8..0]
NUM2_0[8..0]
NUM1_1[8..0]
NUM1_0[8..0]
OPERAND[8..0]
LCD_DataToLine1
inst
LCD
_ON
OU
TPU
T
LCD
_BLO
NO
UTP
UT
LCD
_RW
OU
TPU
T
LCD
_EN
OU
TPU
T
LCD
_RS
OU
TPU
T
VCC
LCD
_DAT
ABI
DIR
'1'
'1'
VCC
line1
[31:
0]IN
PUT
VCC
rese
tIN
PUT
VCC
CLO
CK_
50IN
PUT
VCC
IN3[
7:0]
INPU
T
VCC
IN2[
7:0]
INPU
T
VCC
IN1[
7:0]
INPU
T
VCC
IN0[
7:0]
INPU
T
<<{ IN3 , IN2 , IN1 , IN0 }>>
Figure 2.26: LCD block diagram
28
Module: LCD_TEST
Receives the data to display on the LCD display, initialize the LCD parameters and
timing and display the information. This module uses the LCD_Controller module in
order to initialize the display.
LCD_TEST
iCLKiCLK
iRST_NiRST_N
NUM1_1[8..0]NUM1_1[8..0]
NUM1_0[8..0]NUM1_0[8..0]
NUM2_1[8..0]NUM2_1[8..0]
NUM2_0[8..0]NUM2_0[8..0]
OPERAND[8..0]OPERAND[8..0]
ANS3_1[8..0]ANS3_1[8..0]
ANS3_0[8..0]ANS3_0[8..0]
ANS2_1[8..0]ANS2_1[8..0]
ANS2_0[8..0]ANS2_0[8..0]
ANS1_1[8..0]ANS1_1[8..0]
ANS1_0[8..0]ANS1_0[8..0]
ANS0_1[8..0]ANS0_1[8..0]
ANS0_0[8..0]ANS0_0[8..0]
LCD_DATA[7..0]LCD_DATA[7..0]
LCD_RWLCD_RW
LCD_ENLCD_EN
LCD_RSLCD_RS
. Figure 2.23: LCD_TEST I/O diagram
29
I/O Name Size [bits] Remarks
Input iCLK 1 System clock
Input iRST_N 1 reset
Input NUM0_1 9 First digit of number to display
Input NUM0_0 9 Second digit of number to display
Input NUM1_1 9 First digit of number to display
Input NUM1_0 9 Second digit of number to display
Input OPERAND 9 The operand to display
Input ANS0_1 9 First digit of first answer to display
Input ANS0_0 9 Second digit of first answer to display
Input ANS1_1 9 First digit of second answer to display
Input ANS1_0 9 Second digit of second answer to display
Input ANS2_1 9 First digit of first third to display
Input ANS2_0 9 Second digit of first third to display
Input ANS3_1 9 First digit of fourth answer to display
Input ANS3_0 9 Second digit of fourth answer to display
Output LCD_DATA 8 Output data to LCD controller
Output LCD_RW 1 Read / Write to LCD controller
Output LCD_EN 1 Enable to LCD controller
Output LCD_RS 1 Reset to LCD controller
Table 2.19: LCD_TEST I/O ports
Module: LCD_Controller
Initialize the LCD display.
LCD_Controller
iDATA[7..0]iDATA[7..0]
iRSiRS
iStartiStart
iCLKiCLK
iRST_NiRST_N
oDoneoDone
LCD_DATA[7..0]LCD_DATA[7..0]
LCD_RWLCD_RW
LCD_ENLCD_EN
LCD_RSLCD_RS
. Figure 2.24: LCD_Controller I/O diagram
30
I/O Name Size [bits] Remarks
Input iCLK 1 System clock
Input iRST_N 1 reset
Input iStart 1
Input iRS 1
Input iDATA 8
Output oDONE 1
Output LCD_DATA 8 Output data to LCD controller
Output LCD_RW 1 Read / Write to LCD controller
Output LCD_EN 1 Enable to LCD controller
Output LCD_RS 1 Reset to LCD controller
Table 2.20: LCD_Controller I/O ports
Module: LCD _DataToLine1
The numbers of the exercise are converted from a binary mode into 2 BCD digits, using a
binary_to_BCD modules. The operand is converted into the textual sign (+, -, /, *) using
a decoder. The converted numbers and operand are been sent back to the LCD_TEST
module to be displayed in the first line of LCD display.
LCD_DataToLine1
IN[31..0]IN[31..0] NUM2_1[8..0]NUM2_1[8..0]
NUM2_0[8..0]NUM2_0[8..0]
NUM1_1[8..0]NUM1_1[8..0]
NUM1_0[8..0]NUM1_0[8..0]
OPERAND[8..0]OPERAND[8..0]
. Figure 2.27: LCD_DataToLine1 I/O diagram
31
I/O Name Size [bits] Remarks
Input IN 32 First line input to LCD
Output NUM1_1 8 First digit of first argument in question
Output NUM1_0 8 Second digit of first argument in question
Output NUM2_1 8 First digit of second argument in question
Output NUM2_0 8 Second digit of second argument in question
Output ORERAND 8 The operand of the question
Table 2.22: LCD_DataToLine1 I/O ports
VCC
ININ
PUT
NUM1_0 OUTPUT
NUM1_1 OUTPUT
NUM2_0 OUTPUT
NUM2_1 OUTPUT
OPERAND OUTPUT
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
bin1
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
bin2
data[1..0]eq0
eq1
eq2
eq3
AA_DECODE
inst
IN[31:24]
IN[23:16]
<<{10011,ONES[3:0]}>>
<<{10011,TENS[3:0]}>>
<<{10011,ONES[3:0]}>>
<<{10011,TENS[3:0]}>>
IN[31:24]
'10011'
<<IN
[31:
0]>>
Figure 2.28: LCD_DataToLine2 block diagram
32
Module: LCD _DataToLine2
The 4 answers of the exercise are converted from a binary mode into 2 BCD digits, using
a binary_to_BCD modules. The converted numbers are been sent back to the LCD_TEST
module to be displayed in the second line of the LCD display.
LCD_DataToLine2
IN[31..0]IN[31..0] NUM3_1[8..0]NUM3_1[8..0]
NUM3_0[8..0]NUM3_0[8..0]
NUM2_1[8..0]NUM2_1[8..0]
NUM2_0[8..0]NUM2_0[8..0]
NUM1_1[8..0]NUM1_1[8..0]
NUM1_0[8..0]NUM1_0[8..0]
NUM0_1[8..0]NUM0_1[8..0]
NUM0_0[8..0]NUM0_0[8..0]
. Figure 2.29: LCD_DataToLine2 I/O diagram
I/O Name Size [bits] Remarks
Input IN 32 Second line input to LCD
Output NUM0_1 8 First digit of first answer
Output NUM0_0 8 Second digit of first answer
Output NUM1_1 8 First digit of second answer
Output NUM1_0 8 Second digit of second answer
Output NUM2_1 8 First digit of third answer
Output NUM2_0 8 Second digit of third answer
Output NUM3_1 8 First digit of fourth answer
Output NUM3_0 8 Second digit of fourth answer
Table 2.23: LCD_DataToLine2 I/O ports
33
VCC
ININ
PUT
NUM0_0 OUTPUT
NUM0_1 OUTPUT
NUM1_0 OUTPUT
NUM1_1 OUTPUT
NUM2_0 OUTPUT
NUM2_1 OUTPUT
NUM3_0 OUTPUT
NUM3_1 OUTPUT
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
bin0
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
bin1
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
bin2
IN[7..0]ONES[3..0]
TENS[3..0]
binary _to_BCD
bin3
<<IN
[31:
0]>>
IN[31:24]
IN[23:16]
IN[15:8]
IN[7:0]
'10011'
<<{10011,ONES[3:0]}>>
<<{10011,TENS[3:0]}>>
<<{10011,ONES[3:0]}>>
<<{10011,TENS[3:0]}>>
<<{10011,ONES[3:0]}>>
<<{10011,TENS[3:0]}>>
<<{10011,ONES[3:0]}>>
<<{10011,TENS[3:0]}>>
Figure 2.30: LCD_DataToLine2 block diagram
Module: binary_to_BCD
Convert an 8 bit binary number into a BCD number of 2 4 bit digits
binary _to_BCD
IN[7..0]IN[7..0] ONES[3..0]ONES[3..0]
TENS[3..0]TENS[3..0]
. Figure 2.31: binary_to_BCD I/O diagram
34I/O Name Size [bits] Remarks
Input IN 8 Binary number
Input ONES 4 Bcd number (the ones digit)
Input TENS 4 Bcd number (the tens digit)
Table 2.24: binary_to_BCD I/O ports
Module: SRAM
A 32 words SRAM module. Each word is 32 bit long. This module is used as an easy
access to the 512KB SRAM memory on the DE2 board. It is a module generated by the
Mega Wizard option at the Quartus II program. The SRAM is initializes with the values
shown in Table 2.26 and controlled by the Counter5Bit module (the SRAM address) and
the user choice (each choice for a answer triggers the clock, and each reset returns to the
initioal values).
SRAM
address[4..0]address[4..0]
clockclock
q[31..0]q[31..0]
. Figure 2.32: SRAM I/O diagram
I/O Name Size [bits] Remarks
Input Address 5 Read address
Input Clock 1 Clock
Output Q 32 Output data from SRAM
Table 2.25: SRAM I/O ports
35
number 1 number 2 result operand 32 bit HEX value in memory 0 42 3 14 / 2A030E03 1 53 43 10 - 352B0A01 2 41 7 48 + 29073000 3 1 8 9 + 01080900 4 13 2 26 * 0D021A02 5 33 11 3 / 210B0303 6 47 5 42 - 2F052A01 7 7 8 56 * 07083802 8 11 11 1 / 0B0B0103 9 36 6 6 / 24060603 10 22 2 44 * 16022C02 11 8 3 24 * 08031802 12 54 9 6 / 36090603 13 32 11 21 - 200B1501 14 59 4 63 + 3B043F00 15 61 17 44 - 3D112C01 16 60 3 20 / 3C031403 17 41 15 56 + 290F3800 18 21 7 3 / 15070303 19 19 3 57 * 13033902 20 24 6 4 / 18060403 21 18 9 27 + 12091B00 22 17 17 0 - 11110001 23 29 19 48 + 1D133000 24 37 13 24 - 250D1801 25 36 9 4 / 24090403 26 19 2 38 * 13022602 27 9 7 63 * 09073F02 28 15 13 2 - 0F0D0201 29 24 17 7 - 18110701 30 46 6 40 - 2E062801 31 55 9 46 - 00370920
Table 2.26: SRAM values
36
Module: Counter5Bit
A 5 bit counter. The output of the counter holds the address of the SRAM. When the user
chose an answer the counter counts up to the next SRAM address, which holds the next
exercise.
Counter5Bit
clockclock
resetreset
out[4..0]out[4..0]
. Figure 2.33: Counter5Bit I/O diagram
I/O Name Size [bits] Remarks
Input Clock 1 Clock
Input Reset 1 Resset
Output Out 5 Address to SRAM module
Table 2.27: Counter5Bit I/O ports
37
Section 3: Snapshots
The DE2 components:
The marked components are the one used in the design.
Figure 3.1: DE2 board
LCD display ON/OFF Green LEDs 7-Segmen display
Push buttons Switches
38
Wrong answer
Figure 3.2: false answer indication
Current question.
Answer to the previous question.
39
Right answer
Figure 3.3: true answer indication
Answer to the previous question.
Current question.
True answer indicator.
40
LCD display
Figure 3.4 shows the random location of the correct answer and the generated random false answers.
Figure 3.4: different instances of the same question.
Correct answer.
41
Section 4: remarks
During the project we have encountered some issues with the DE2 board:
1. The LCD backlight isn’t working
2. If not connected to any ports or wires, the LEDs (both green and red) started to
light up randomly and with no known reason.
3. If not connected to any ports or wires, the 7-Segment display shows random
numbers with no known reason.