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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 1
EE247Lecture 22
Pipelined ADCs (continued) Effect sub-ADC, gain stage, sub-DAC non-idealities on overall ADCperformance (continued)
Correction for inter-stage gain nonlinearity
Implementation Combining the bits Practical circuits Stage scaling Stage implementation
Circuits Noise budgeting
How many bits per stage?
Algorithmic ADCs utilizing pipeline structure
Advanced background calibration techniques
Time Interleaved Converters
ADC figures of merit
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 2
Pipeline ADCBlock Diagram
Idea: Cascade several low resolution stages to obtain high overall resolution(e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!)
Each stage performs coarse A/D conversion and computes its quantizationerror, or "residue
Stage 1B1 Bits
Digital Output (B1+B2+..Bk) Bits
Vin
MSB....... ...LSB
Vres1 Vres2Stage 2
B2 BitsStage k
Bk Bits
+-DACADC
Align and Combine Data
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 3
Summary So FarPipelined A/D Converters
VinADC2B1eff 2
B2 2B3B2
bitsB1
bits
Cascade of low resolution stages
By adding inter-stage gain= 2Beff
No need to scale down Vref for stages down the pipe
Reduced accuracy requirement for stages coming after stage 1
Addition of Track & Hold function to interstage-gain
Stages can operate concurrently
Throughput increased to as high as one sample per clock cycle
Latency function of number of stages & conversion-per-stage
Correction for circuit non-idealities
Built-in redundancy compensate for sub-ADC inaccuracies such ascomparator offset (interstage gain: G=2Bneff, Bneff < Bn)
Error associated with gain stage and sub-DAC calibrated out
B3
bits2B2eff 2B3eff
VrefVref Vref Vref
T/H+Gain
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 4
Pipelined ADCError Correction/Calibration Summary
VIN1 VRES1
DAC
D1
-
a3V3
+22
ADC
+
VOS
+
+
eADC
+
eDAC
egain
Error Correction/Calibration
eADC, Vos Redundancy either same stage or next stage
egain Digital adjustment
eDAC Either sufficient component matching or digitalcalibration
Inter-stage amplifier non-linearity ?
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 5
Inter-stage Gain Nonlinearity
Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop ResidueAmplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003
Invert gain stage non-linear polynomial
Express error as function of VRES1
Push error compensator into digital domain through backend ADC
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 6
Inter-stage Gain Nonlinearity
Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop ResidueAmplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003
VRES1
a3VX3
+ BackendDB DB,corr
(...)
+-
...D12pD3pDp)p,(D 7B3
25
B2
23
B22B +-+-=e
VX
e(DB, p2)33
32
egain )(2a
p+
=
23
egain
Pre-measured & stored in table look-up form
p2 continuously estimated & updated (account for temp. & other variations)
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 7
Inter-stage Gain Nonlinearity CompensationProof of Concept Evaluation Prototype
Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop ResidueAmplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003
Re-used 14-bit ADC in 0.35mm from Analog Devices [Kelly, ISSCC 2001] Modified only 1st stage with 3-beff open-loop amplifier built with simple diff-pair +
resistive load instead of the conventional feedback around high-gain amp
Conventional 9-beff backend, 2-bit redundancy in 1st stage
Real-time post-processor off-chip (FPGA)
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 8
Measurement Results12-bit ADC w Extra 2-bits for Calibration
0 1000 2000 3000 4000-1
-0.5
0
0.5
1wt ca raton0 1000 2000 3000 4000
-10
0
10
(a) without calibration
Code
INL[LSB]
RNG=0RNG=1
0 1000 2000 3000 4000
-10
0
10
(b) with calibration
Code
INL[LSB
]
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 9
Combining the Bits
Example: Three 2-bit stages, no redundancy
Stage 2Vin Stage 3Stage 1
Dout+ +
2 2 2
6
B1=2B1eff=2
B2=2B2eff=2
B3=2
1/22 1/22
D1 D2 D3
321
321211
16
1
4
122
1
2
1
DDDD
DDDD
out
effBeffBeffBout
++=
++=
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 10
Combining the Bits
Only bit shifts
No arithmeticcircuits needed
D1
XX
D2
XX
D3
XX
------------
Dout
DDDDDD
Stage 2Vin Stage 3Stage 1
Dout[5:0]
B1=2B1eff=2
B2=2B2eff=2
B3=2
MSB LSB
D1
D2
D3
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 11
Combining the BitsIncluding Redundancy
Example: Three 2-bit stages, incorporating 1- bitredundancy in stages 1 and 2
Stage 2Vin Stage 3Stage 1
B1=3B1eff=2
B2=3B2eff=2
B3=2
8 Wires
6 Wires
???
Dout[5:0]
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 12
Combining the Bits Bits overlap
Need adders
D1
XXX
D2
XXX
D3
XX
------------
Dout
DDDDDD
Stage 2Vin Stage 3Stage 1
Dout[5:0]
B1=3B1eff=2
B2=3B2eff=2
B3=2
HADDHADDFADDHADDHADD
D1
D2
D3
321
321211
16
1
4
1
22
1
2
1
DDDD
DDDD
out
effBeffBeffBout
++=
++=
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 13
Combining the BitsExample
D1
001
D2
111
D3
10
------------
Dout
011000
Stage 2Vin Stage 3Stage 1
Dout[5:0]
B1=3B1eff=2
B2=3B2eff=2
B3=2
HADDHADDFADDHADDHADD
D1
D2
D3
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 14
Pipelined ADCStage Implementation
Each stage needs T/H hold function
Track phase: Acquire input/residue from previous stage
Hold phase: sub-ADC decision, compute residue
Stage 1 Stage 2Vin Stage n
acquire
convert
convertacquire
...
...f1 ...
CLK
+-
DACADC
GVresT/H
f2 f1
f1f2
Vin
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 15
Stage Implementation
Usually no dedicated T/H amplifier in each stage(Except first stage in some cases why?)
T/H implicitely contained in stage building blocks
Vin +
-
DACADC
GV
resT/H T/H
T/H
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 16
Stage Implementation
DAC-subtract-gain function can be lumped intoa single switched capacitor circuit
"MDAC"
Vin
+-
DACADC
GV
resT/H
T/H
MDAC
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 17
1.5-Bit Stage Implementation Example
Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis,1999
D1,D0 VDAC
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 18
1.5-Bit Stage ImplementationAcquisition Cycle
Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis,1999
D1,D0 VDAC
Vcf=Vcs=Vi
QCs=CsxViQCf=CfxVi
F1
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 19
1.5-Bit Stage ImplementationConversion Cycle
Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis,1999
D1,D0 VDAC
F2
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 20
1.5-Bit Stage ImplementationConversion Cycle
D1,D0 VDACVi>VR/4 1 1 -V R-VR/4
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 21
1.5 Bit Stage Implementation Example
Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis,1999
Note:Interstage gain set by C ratios Accuracy better than 0.1%Up to 10bit level no need for
gain calibration
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 22
1.5-Bit Stage ImplementationTiming of Stages
VDAC
VDAC
Conversion Acquisition
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 23
Pipelined ADC Stage Power Dissipation & Noise
Typically pipeline ADC noise dominated by inter- stage gain blocks
Sub-ADC comparator noise translates into comparator thresholduncertainty and is compensated for by redundancy
Vin Stage 1 Stage 3Stage 2
Vn2 Vn3Vn1
G1 G2 G3Vin
2 2in 2 n2 n3
noise n1 2 2 2
V VV V .. .
G1 G1 G2= + + +
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 24
Pipelined ADC Stage Scaling
Example: Pipeline using 1-biteff stages
Total input referred noise power:
C1/2
C1
Gm
C2/2
C2
Gm
C3/2
C3
GmVin
Vn2 Vn3Vn1
G1=2 G2=2 G3=2Vin
to t 2 2 21 2 3
to t1 2 3
1 1 1N kT . . .
C G1 C G1 G2 C
1 1 1N kT . . .
C 4C 16C
+ + +
+ + +
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 25
C1/2
C1
Gm
C2/2
C2
Gm
C3/2
C3
GmVin
If all caps made the same size, backend stages contribute verylittle noise
Wasteful power-wise, because:
Power ~ Gm
Speed ~ Gm/C
Fixed speed Gm/C filxed Power ~ C
+++ ...
16
1
4
11
321CCC
kTNtot
Pipelined ADC Stage Scaling
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 26
How about scaling caps down by G2
=22
=4x per stage? Same amount of noise from every stage
All stages contribute significant noise
To keep overall noise the same noise/stage must bereduced
Power ~ Gm ~ C goes up!
C1/2
C1
Gm
C2/2
C2
Gm
C3/2
C3
GmVin
+++ ...
16
1
4
11
321CCC
kTNtot
Pipelined ADC Stage Scaling
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 27
Stage ScalingExample: 2-biteff/stage
Optimum capacitior scaling lies approximately midway between
these two extremesRef: D. W. Cline, P.R. Gray "A power optimized 13-b 5MSamples/s pipelined analog-to-digital
converter in 1.2um CMOS," JSSC 3/1996
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 28
Pipeline ADCStage Scaling
Power minimum is "shallow
Near optimum solution in practice: Scale capacitorsby stage gain
E.g. for effective stage resolution of 1bit (Gain=2):C/2
C
Gm
C/4
C/2
Gm
C/8
C/4
GmVin
1 1 1...
2 4totN kT
C C C
+ + +
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 29
Stage Scaling Example
Ref: D. W. Cline, P.R Gray "A power optimized 13-b 5 MSamples/s pipelined analog-to-digitalconverter in 1.2um CMOS," JSSC 3/1996
Note:Resolutionper stage:2bits
G=4
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 30
How Many Bits Per Stage?
Many possible architectures
E.g. B1eff=3, B2eff=1, ...vs. B1eff=1, B2eff=1, B3eff=1, ...
Complex optimization problem, fortunately optimum tends to beshallow...
Qualitative answer:
Maximum speed for given technology
Use small resolution-per-stage (large feedback factor) Maximum power efficiency for fixed, "low" speed
Try higher resolution stages
Can help alleviate matching & noise requirements in stagesfollowing the 1st stageRef: Singer VLSI 96, Yang, JSSC 12/01 (14bit ADC w/o calibration)
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 31
14 & 12-Bit State-of-the-Art Implementations
Reference Yang(JSSC 12/2001)
0.35m/3V
Loloee(ESSIRC 2002)
0.18m/3V
Bits 14 12
Architecture 3-1-1-1-1-1-1-1-1-3 1-1-1-1-1-1-1-1-1-1-2
SNR/SFDR ~73dB/88dB ~66dB/75dB
Speed 75MS/s 80MS/s
Power 340mW 260mW
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 32
10 & 8-Bit State-of-the-Art Implementations
Reference Yoshioko et al
(ISSCC 2005)
0.18m/1.8V
Kim et al
(ISSCC 2005)
0.18m/1.8V
Bits 10 8
Architecture 1.5bit/stage 2.8 -2.8 - 4
SNR/SFDR ~55dB/66dB ~48dB/56dB
Speed 125MS/s 200MS/s
Power 40mW 30mW
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 33
Algorithmic ADC
Essentially same as pipeline, but a single stage is reused for all partial conversions
For overall Boverall bits need Boverall/Bstage clock cycles per conversion
Small area, slow Trades conversion time for area
T/H sub-ADC(1.6 Bit)
Digital Output
VIN
Residue
DAC
Shift Register& Correction Logicstart of conversion
2B
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 34
Least Mean Square Adaptive Digital BackgroundCalibration of Pipelined Analog-to-Digital Converters
Ref: Y. Chiu, et al, Least Mean Square Adaptive Digital Background Calibration of PipelinedAnalog-to-Digital Converters, IEEE TRANS. CAS, VOL. 51, NO. 1, JANUARY 2004
Slow, but accurate ADC operates in parallel with pipelined (main) ADC
Slow ADC samples input signal at a lower sampling rate (fs/n)
Difference between corresponding samples for two ADCs (e) used to correctfast ADC digital output via an adaptive digital filter (ADF) based onminimizing the Least-Mean-Squared error
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 35
Example: "A 12-bit 20-MS/s pipelined analog-to-digitalconverter with nested digital background calibration"
Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-Msample/s pipelined analog-to-digital converterwith nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799 - 1808, Nov. 2004
Pipelined ADC operates at 20Ms/s @ has 1.5bit/stage
Slow ADC Algorithmic type operating at 20Ms/32=625ks/s
Digital correction accounts for bit redundancy
Digital error estimator minimizes the mean-squared-error
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 36
Algorithmic ADC Used for Calibration ofPipelined ADC (continued from previous page)
Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converterwith nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799 - 1808, Nov. 2004
Uses replica of pipelined ADC stage
Requires extra SHA in front to hold residue
Undergoes a calibration cycle periodically prior to being used to calibratepipelined ADC
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 37
12-bit 20-MS/s Pipelined ADC with DigitalBackground Calibration
Ref: X. Wang, P. J. Hurst, S. H.Lewis, " A 12-bit 20-MS/spipelined analog-to-digitalconverter with nested digital
background calibration,IEEE JSSC, vol. 39, pp.1799 - 1808, Nov. 2004
Sampling capacitors scaled (1Beff/stage): Input SHA: 6pF
Pipelined ADC: 2pF,0.9,0.4,0.2, 0.1,0.1
Algorithmic ADC: 0.2pF
Chip area: 13.2mm2
Does not include digitalcalibration circuitry estimated~1.7mm2
Area of Algorithmic ADC
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 39
Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converterwith nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799 - 1808, Nov. 2004
Measurement Results12-bit 20-MS/s Pipelined ADC with Digital Background Calibration
Nyquist
rate
EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 40
Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converterwith nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799 - 1808, Nov. 2004
Measurement Results12-bit 20-MS/s Pipelined ADC with Digital Background Calibration
Does not includedigital calibrationcircuitry estimated~1.7mm2
Alg. ADC SNDRdominated by noise
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EECS 247 Lecture 22: Data Converters- N yquist Rate ADCs 2010 Page 41
ADC Architectures
Slope type converters Successive approximation
Flash Interpolating & Folding Residue type ADCs
Two-step Flash Pipelined ADCs
Time-interleaved / parallel converter Oversampled ADCs
EECS 247- Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 42
Time Interleaved Converters Example:
4 ADCs operating in parallel atsampling frequencyfs
Each ADC converts on one ofthe 4 possible clock phases
Overall sampling frequency= 4fs Note T/H has to operate at 4fs!
Extremely fast:Typically, limited by speed of T/H
Accuracy limited by mismatchamong individual ADCs (timing,offset, gain, )
T/H
4fs
ADC
fs
ADC
ADC
ADC
Ou
tputCombiner
VIN
D
igitalOutput
fs+Ts/4
fs+2Ts/4
fs+3Ts/4
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EECS 247- Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 43
Time Interleaved ConvertersTiming
Note: Effective sampling rate 4xfs
1/4Ts
Ts=1/fs
1/4Ts
1/4Ts
1/4Ts
Input
signalsampled
EECS 247- Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 44
ADC Figures of Merit
Objective: Establish measure/s to compareperformance of various ADCs
Can use FOM to combine severalperformance metrics to get one singlenumber
What are reasonable FOM for ADCs?
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EECS 247- L ecture 22 Data Converters- Nyquist Rate ADC 2010 Page 45
ADC Figures of Merit
This FOM suggests that adding an extra bitto an ADC is just as hard as doubling itsbandwidth
Is this a good assumption?
ENOB
sfFOM 21 =
Ref: R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE Journalon Selected Areas in Communications, April 1999
EECS 247- Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 46
Survey Data
1bit/Octave
Ref: R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE Journal on SelectedAreas in Communications, April 1999
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EECS 247- Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 47
ADC Figures of Merit
Sometimes inverse of this metric is used
In typical circuits power ~ speed, FOM2captures this tradeoff correctly
How about power vs. ENOB?
One more bit 2x in power?Ref: R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE Journal on Selected
Areas in Communications, April 1999
]/[2
2convJ
f
PowerFOM
ENOB
s =
EECS 247-Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 48
ADC Figures of Merit
One more bit means... 6dB SNR, 4x less noise power, 4x larger C
Power ~ Gm ~ C increases 4x
Even worse: Flash ADC Extra bit means 2x number of comparators
Each of them needs double precision Transistor area 4x, Current 4x to keep same
current density
Net result: Power increases 8x
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EECS 247-Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 49
ADC Figures of Merit
FOM2 seems not entirely appropriate, butsomehow still standard in literature, papers
"Tends to work" because:
Not all power in an ADC is "noise limited
E.g. Digital power, biasing circuits, etc.
Better use FOM2
to compare ADCs withsame resolution!
EECS 247-Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 50
ADC Figures of Merit
Speed
PowerFOM =
3
Compare only power of ADCs withapproximately same ENOB
Useful numbers: 10b (~9 ENOB) ADCs: 1 mW/MSample/sec
Note the ISSCC 05 example: 0.33mW/MS/sec!
12b (~11 ENOB) ADCs: 4 mW/MSample/sec
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EECS 247- Lecture 22 Data Converters -Nyquist Rate ADCs 2010 Page 51
10-Bit ADC Power/Speed
Yoshioko ISSCC 05
EECS 247- Lecture 22 Data Converters- Nyquist Rate ADCs 2010 Page 52
12-Bit ADC Power/Speed
Loloee
(ESSIRC 2002)
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EECS 247- Lecture 22 Pipelined ADCs and More 2010 Page 53
1.0E+09
1.0E+10
1.0E+11
1.0E+12
1985 1990 1995 2000 2005
BandwidthxResolution[Hz-LSB]
Performance Trend
2x/5 years
EECS 247 Lecture 22: Data Converters- N yquist Rate ADCs 2010 Page 54
ADC Architectures
Slope type converters Successive approximation Flash Interpolating & Folding
Residue type ADCs Two-step Flash
Pipelined ADCs
Time-interleaved / parallel converter Oversampled ADCs
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EECS 247- Lecture 22 Oversampled ADCs 2010 Page 55
Analog-to-Digital Converters
Two categories:
Nyquist rate ADCs fsigmax ~ 0.5xfsampling
Maximum achievable signal bandwidth higher comparedto oversampled type
Resolution limited to max. ~14 to 16bits
Oversampled ADCs fsigmax > 1
fs >2B +dFreqB
Signal
narrowtransition
SamplerAA-Filter
NyquistADC
DSP
= M
FreqB
Signal
wide
transition
SamplerAA-Filter
OversampledADC
DSP
fs
fs fN
fs >> fN??
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EECS 247- Lecture 22 Oversampled ADCs 2010 Page 57
Nyquist v.s. Oversampled ConvertersAntialiasing Requirements
|X(f)|
frequency
frequency
frequency
fB
fB 2fs
fB fs
Input Signal
Nyquist Sampling
Oversampling
fS ~2fB
fS >> 2fB
fs
Anti-aliasing Filter
EECS 247- Lecture 22 Oversampled ADCs 2010 Page 58
Oversampling Benefits
Almost no stringent requirements imposed onanalog building blocks
Takes advantage of the availability of low cost,low power digital filtering
Relaxed transition band requirements for
analog anti-aliasing filters
Reduced baseband quantization noise power
Allows trading speed for resolution
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EECS 247- Lecture 22 Oversampled ADCs 2010 Page 59
ADC ConvertersBaseband Noise
For a quantizer with quantization step size D and sampling rate fs:
Quantization noise power distributed uniformly across Nyquist
bandwidth (fs/2)
Power spectral density:
Noise is distributed over the Nyquist band fs/2 to fs/2
2 2
e
s s
e 1N ( f )
f 12 f
D= =
-fB fs/2-fs/2 fB
Ne(f)
NB
EECS 247- Lecture 22 Oversampled ADCs 2010 Page 60
Oversampled ConvertersBaseband Noise
B B
B B
f f 2
B e
f f s
2B
s
B s2
B0
B B0B B0
s
s
B
1S N ( f )df df
12 f
2 f
12 f
w he re f or f f / 2
S
12 2 f SS S
f Mf
w he re M o ve rs am plin g r atio2 f
- -
D= =
D=
=D
=
= =
= =
-fB fs/2-fs/2 fB
Ne(f)
NB
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EECS 247- Lecture 22 Oversampled ADCs 2010 Page 61
Oversampled ConvertersBaseband Noise
2X increase in M
3dB reduction in SB bit increase in resolution/octave oversampling
B B0B B0
s
s
B
2 f SS S
f Mf
w he re M o ve rs am pl in g r at io2 f
= =
= =
To further increase the improvement in resolution:
Embed quantizer in a feedback loop (patented by Cutlerin 1960s!)
Noise shaping (sigma delta modulation)
EECS 247- Lecture 22 Oversampled ADCs 2010 Page 62
Pulse-Count Modulation
Vin=2/8
NyquistADC
t/Ts0 1 2
OversampledADC, M = 8
t/Ts0 1 2
Vin=2/8
Mean of pulse-count signal approximates analog input!
010 010
2/8
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Pulse-Count Output Spectrum
f
Magnitude
Signal band of interest: low frequencies, f < B
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Oversampled ADC
Decimator: Digital (low-pass) filter Removes quantization noise for f > B
Provides anti-alias filtering for DSP
Narrow transition band, high-order (digital filters with high orderconsume significantly smaller power & area compared to analog filters) 1-Bit input, N-Bit output (essentially computes average)
fs=Mf
N
FreqB
Signal
widetransition
SamplerAnalogAA-Filter
E.g.Pulse-CountModulator
Decimatornarrowtransition
fs1
= M fN
DSP
Modulator DigitalAA-Filter
fs2
= fN
+d
1-Bit Digital N-Bit
Digital
EECS 247- Lecture 22 Oversampled ADCs 2010 Page 66
Modulatoror Analog Front End (AFE)
Objectives: Convert analog input to 1-Bit pulse density stream
Move quantization error to high frequencies f >>B
Operates at high frequency fs >> fN M = 8 256 (typical).1024
Since modulator operated at high frequencies need to keep analog circuitry simple
SD = DS Modulator
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Sigma- Delta Modulators
Analog 1-Bit SD modulators convert a continuous timeanalog input vIN into a 1-Bit sequence DOUT
H(z)+
_
VINDOUT
Loop filter 1b Quantizer (comparator)
fs
DAC
EECS 247- Lecture 22 Oversampled ADCs 2010 Page 68
Sigma-Delta Modulators
The loop filter H can be either switched-capacitor or continuous time
Switched-capacitor filters are easier to implement + frequencycharacteristics scale with clock rate
Continuous time filters provide anti-aliasing protection
H(z)
+
_VIN
DOUT
fs
DAC
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Oversampling A/D Conversion
Analog front-end oversampled noise-shaping modulator
Converts original signal to a 1-bit digital output at the high rate of
(2BXM)
Digital back-end
digital filter (decimator) Removes out-of-band quantization noise Provides anti-aliasing to allow re-sampling @ lower sampling rate
1-bit
@ fs
N-bit
@ fs/M
Input Signal Bandwidth
B=fs/2M
Decimation
Filter
OversamplingModulator
(AFE)
fs
fs = sampling rate
M= oversampling ratio
fs /M
EECS 247- Lecture 22 Oversampled ADCs 2010 Page 70
1st Order SD Modulator1st order modulator, simplest loop filter an integrator
+
_VIN
DOUT
H(z) =z-1
1z-1
DAC
Note: Non-linear system with memory difficult toanalyze