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A Novel SEPIC-Cuk Based High Gain Solar
Micro-Inverter for Grid IntegrationArup Ratan Paul, Arghyadip Bhattacharya, and Kishore Chatterjee, Member, IEEE
Abstract—Solar micro-inverters are becoming increasinglypopular as they are modular, and they posses the capabilityof extracting maximum available power from the individualphotovoltaic (PV) modules of a solar array. For realizing micro-inverters single stage transformer-less topologies are preferred as
they offer better power evacuation efficacy. A SEPIC-Cuk basedtransformer-less micro-inverter, having only one high frequencyswitch and four line frequency switches, is proposed in this paper.The proposed converter can be employed to interface a 35 VPV module to a 220 V single phase ac grid. As a very highgain is required to be achieved for the converter, it is made tooperate in discontinuous conduction mode (DCM) for all possibleoperating conditions. Since the ground of the each PV modulesis connected to the ground of the utility, there is no possibility ofleakage current flow between the module and the utility. Detailedsimulation studies are carried out to ascertain the efficacy of theproposed micro-inverter. A laboratory prototype of the inverteris fabricated, and detailed experimental studies are carried outto confirm the viability of the proposed scheme.
Index Terms—Solar PV, Micro-inverter, Cuk converter, SEPIC,DCM, dc-ac Conversion.
I. INTRODUCTION
THOUGH the fossil fuel based power generation remains
to be the dominant source of electrical energy, harvesting
of energy from the renewable sources (solar, wind etc.) are
strongly being encouraged as they are more environment
friendly, and inexhaustible in nature. In India, as the solar
energy is abundant all over the country throughout the year, it
is becoming a viable alternative to the conventional methods
of generation of electrical energy. The Ministry of New &
Renewable Energy, Govt. of India, has set a target of 100 GW
grid connected solar power generation by the year 2021-22
under National Solar Mission, out of which 40 GW should
be from the rooftop installations [1]. The solar modules are
generally interfaced to the utility by employing the following
configurations, (i) central inverter, (ii) string inverter and (iii)
micro-inverter. The major advantages of the micro-inverter
over the central and string inverter are as follows [2],
• capability of individual maximum power point tracking
(MPPT) of the PV modules during non-uniform shading,
• the aspect of modularity bestows it with the flexibility in
future expansion of the plant whenever required,
• the existence of plug and play feature imparts flexibility
in operation and coordination of the system.
Typically, the power rating of a micro-inverter is 250-350 W,
and hence their efficiency remains to be low compared to
that of the schemes based on central and string inverters.
In order to improve the efficiency of micro-inverters, lower
number of power conversion stages are incorporated [3].
In order to accomplish this feature, transformer-less single
stage topologies for micro-inverter are generally preferred [4].
However, in case of transformer-less topologies, there exists
a path for the leakage current to flow through the parasitic
capacitance of the PV module to the grid [5], [6]. The flow of
leakage current deteriorates the life of the modules. Further, it
posses hazard to the working personnel as the potential of the
mountings of the PV module may become high with respect to
the mother earth. Hence, the magnitude of the leakage current
needs to be limited within the standard limit as stipulated by
various regulatory authorities [7].
Generally the MPP voltage of a PV module is 35 V.
However it has to be interfaced to the single phase 110/230 V
grid. Hence, the micro-inverter needs to have a very high gain,
which is one of the main challenges to be addressed.
The requirements pertaining to topological configuration,
and its design can be summarized as follows,
• the magnitude of the leakage current must be within the
limits as specified by various standards,
• the inverter system should have a very high voltage gain
to interface a PV module having a Vmpp of 35 V to a
single phase 110/230 V ac grid,
• the micro-inverter needs to made as compact as possible.
There are several single stage non-isolated topologies re-
ported in the literature [4]. The issue related to the leakage
current has been addressed to by shorting the module ground
with that of the ac grid [8]–[15]. A buck-boost based micro-
inverter topology with only one high frequency switch is
proposed in [8]. In [9], a buck-boost based and in [10], a
Cuk converter based single stage micro-inverter topologies
are reported, wherein the PV module and the ac grid shares
the common ground. In [9], the MPP voltage is chosen to
be 55 V, and the ac grid voltage is considered to be 110 V.
Though the converter is operated in continuous conduction
mode (CCM), the source current is discontinuous thereby
increasing the filtering requirement at the input side. Moreover,
the switches are operated in such a way that, the decoupling of
second order harmonic component is achieved at the terminals
of the PV module. In [10], Cuk derived topology is reported
wherein, 5 high frequency (HF) switches are employed, and
the converter is operated in CCM. A similar power decoupling
strategy, as reported in [9], is incorporated in the topology
presented in [10], and reported in [12]. The designed switching
frequency in all the aforesaid configurations are 50 kHz. In
[11] and [13], a four switch topology with different switching
configurations have been proposed. However, all the switches
of these converters [9]–[11], [13] operate at high frequency.
2
All these converters are designed to be operated in CCM.
This facilitates the inverters to get interfaced to a single
phase voltage level up to 110 V. A modification to the circuit
reported in [10] has been accomplished by adding another
HF switch for controlling the reactive power fed to the grid,
and is presented in [14]. However, the designed switching
frequency is 10 kHz, and hence the size of passive elements are
significantly large. A three switch micro-inverter topology with
common ground is reported in [15] wherein the voltage gain
of the converter can be made both positive and negative, and
therefore it does not require the service of an unfolding circuit
but then it involves three inductors in the main converter.
In India, the ac distribution voltage level is 220 V. How-
ever, all the aforementioned converters are designed to get
interfaced to single phase 110 V system, and hence they are
not suitable for Indian conditions. However in [16] a micro-
inverter topology is presented, which can be interfaced to a
single phase 220 V grid. However, it requires six switches,
out of which, two are required to be high frequency switches.
In view of this an effort has been made in this paper to design a
transformer-less micro-inverter suitable for getting interfaced
to a single phase 220 V grid while utilizing only one high
frequency switch and four line frequency switches in order to
reduce the switch count and reliability of the system.
In order to accomplish these features a SEPIC-Cuk based
micro-inverter topology is proposed in [17] by the authors of
the current paper. The converter is operated in SEPIC mode
during positive half cycle and in Cuk mode during negative
half cycle. By merging SEPIC and Cuk configurations into
one topology, the number of HF switches has been reduced
to one. The designed switching frequency of the system is
100 kHz, hence the size of passive elements have been reduced
considerably. The presence of the common ground between
the module and the grid ensures negligible leakage current
flow. However, the circuit was explored for getting interfaced
to single phase 110 V ac grid. In this paper, an attempt has
been made to get interfaced to a single phase 220 V ac,
which is suitable for Indian distribution network, utilizing the
converter proposed in [17] from a PV module having Vmpp
of 35 V. Detailed simulation studies are carried out on MAT-
LAB/Simulink platform to ascertain the effectiveness of the
proposed converter. A semi-engineered laboratory prototype
of the inverter has been fabricated, and detailed experimental
studies are carried out to confirm the viability of the proposed
scheme.
II. PRINCIPLE OF OPERATION OF THE PROPOSED
TOPOLOGY
The schematic diagram of the proposed SEPIC-Cuk based
micro-inverter is shown in Fig. 1. Four line frequency switches
are utilized to derive the combine effect of SEPIC and Cuk
configuration. In [17] the IGBTs are used to realize the line
frequency switches. In this paper MOSFETs are used instead
of IGBTs to reduce the losses. The diode, D is employed to
block the reverse current flow through the four MOSFETs.
As sinusoidal current is required to be injected to the grid,
the high frequency switch is applied with switching pulses
Fig. 1: Schematic diagram of Cuk-SEPIC based micro-inverter
with dc side filter
which are obtained by comparing the rectified sine wave with
a triangular carrier wave. The instantaneous duty ratio of S1
is determined by multiplying a rectified sine wave with the
peak duty ratio, Dpeak . The switch is operated with Dpeak
when the instantaneous grid voltage is at its peak. The current
through L2 is a rectified sine wave having high frequency
switching harmonics superimposed on it. In order to transform
this rectified current into a sinusoidal waveform the four
switches, S2, S3, S4, and S5 are appropriately switched. The
output capacitor, C2 filters out the high frequency harmonic
components form the output current.
The inductors of the converter can be chosen in such a
way so that the converter can be operated either in CCM or
in DCM. In CCM the voltage gain of both SEPIC and Cuk
converter is d1−d
, wherein d is the duty ratio of the converter.
However, for interfacing the 35 V module to a 220 V ac grid
whose peak voltage is 311 V, the requirement of the duty
ratio at the peak of the ac grid voltage is required to be
maintained at 0.9. Operating the inverter at this high duty ratio,
would reduce the operating efficiency significantly. In order to
overcome this limitation, the proposed topology is operated in
DCM to obtain high voltage gain while maintaining reduced
duty ratio compared to that of CCM operation. In case of
a SEPIC and Cuk converter, current through both L1 and
L2 does not become zero either in CCM or DCM mode of
operation [18], [19]. Further, the DCM operation ensures that
turn on switching loss of S1 is negligible. But this is achieved
at the cost of increased peak current that flows through the
input inductor.
III. MODES OF OPERATION AND ANALYSIS
In order to simplify the analysis of the inverter, a dc source,
Vdc is used instead of a PV module. The convention of voltage
polarity and current direction is shown in Fig. 1. Since the
switching frequency is very high compared to that of the line
frequency, it is assumed that, the output voltage and current
requirement is almost constant throughout the switching time
period (Ts). The ripple in the voltages in the capacitors, C1
and C2 can be considered to be negligible. The average value
of vC1 and vo over a switching time period are assumed to be
VC1 and Vo respectively. The current and voltage waveforms
over a switching cycle is shown in Fig. 4. The switching time
period (Ts) is divided into three time intervals as follows, (i)
T1(= DTs), (ii) T2 and (iii) T3(= D0Ts) respectively. As
T1 + T2 + T3 = Ts, therefore T2 = (1−D −D0)Ts.
3
(a) (b) (c)
Fig. 2: Modes of operation for positive half cycle: (a) Mode-I, (b) Mode-II, and (c) Mode-III
(a) (b) (c)
Fig. 3: Modes of operation for negative half cycle: (a) Mode-I, (b) Mode-II, and (c) Mode-III
A. Positive half cycle (SEPIC mode)
Switch S2 and S3 both are turned on, while S4 and S5
are kept off. At steady state, as the switching time average
voltages across L1 and L2 are zero,
VC1 = Vdc (1)
1) Mode I (0 ≤ t < T1): S1 is turned on and the current
through L1 increases as it flows through the path, Vdc −L1−S1−Vdc as shown in Fig. 2(a). The intermediate capacitor, C1
gets discharged while the current flowing through L2 increases
as it flows through the path, C1 − S1 − S2 − L2 − C1. The
capacitor, C2 supplies power to the grid in this interval. The
diode, D blocks the current through the switch S3 even though
it is receiving the gating pulse. Hence,
Vdc = L1
diL1
dt= L1
IL1p − IL1v
DTs
= L1
∆IL1
DTs
(2)
VC1 = L2
diL2
dt= L2
IL2p − IL2v
DTs
= L2
∆IL2
DTs
(3)
i2 = 0 (4)
where, ∆IL1 = (IL1p − IL1v) and ∆IL2 = (IL2p − IL2v).2) Mode II (T1 ≤ t < (T1 + T2)): S1 is turned off. The
current flows through the path, Vdc − L1 − C1 − D − S3 −Load − Vdc as shown in Fig. 2(b) thereby charging C1. The
energy stored in L2 is transferred to the grid as well as to
C2 through the path, L2 −D − S3 − Load − S2 − L2. This
mode ends when iL1 = −iL2. At the end of this mode, let the
magnitude of the currents through L1 and L2 be IL1m and
IL2m respectively. Therefore,
Vdc − VC1 − Vo = L1
diL1
dt= L1
IL1m − IL1p
(1−D −D0)Ts
(5)
−Vo = L2
diL2
dt= L2
IL2m − IL2p
(1−D −D0)Ts
(6)
i2 = iL1 + iL2. (7)
3) Mode III ((T1 + T2) ≤ t < Ts): This mode starts
when the current through the diode, D becomes zero. The
diode turns off and blocks the current flowing through S3. The
(a) (b)
Fig. 4: Waveform of different converter parameters over a
switching time period: (a) for positive half cycle and (b) for
negative half cycle
current path in this mode is Vdc − S2 − L2 − C1 − L1 − Vdc
as shown in Fig. 2(c). Since VC1 = Vdc, the currents in the
inductors will remain unchanged in this mode. The capacitor
C2 supplies power to the grid in this interval. Hence,
IL1m = IL1v = −IL2m = −IL2v. (8)
Solving (2), (3), (5), (6) and (8), the expression for the
voltage gain can be obtained as,
Vo
Vdc
=D
(1−D −D0). (9)
4
B. Negative half cycle (Cuk Mode):
Switch S4 and S5 both are turned on, while S2 and S3
are kept off. At steady state, as the switching time average
voltages across L1 and L2 are zero,
VC1 = Vdc − Vo. (10)
1) Mode I (0 ≤ t < T1): S1 is turned on and the current
through L1 increases as it flows through the path, Vdc −L1−S1−Vdc as shown in Fig. 3(a). The intermediate capacitor, C1
gets discharged while the current flowing through L2 increases
as it flows through the path, C1−S1−Load−S4−L2−C1.
The diode, D blocks the current through the switch S5 even
though it is receiving the gating pulse. Hence,
Vdc = L1
diL1
dt= L1
IL1p − IL1v
DTs
(11)
VC1 + Vo = L2
diL2
dt= L2
IL2p − IL2v
DTs
. (12)
2) Mode II (T1 ≤ t < (T1 + T2)): S1 is turned OFF. The
current flows through the path, Vdc−L1−C1−D−S5−Vdc
as shown in Fig. 3(b) thereby charging C1. The energy stored
in L2 is transferred to the load as well as to C2 through the
path, L2 −D− S5 −Load− S4 −L2. This mode ends when
iL1 = −iL2. At the end of this mode, let the magnitude of the
currents through L1 and L2 be IL1m and IL2m respectively.
Therefore,
Vdc − VC1 = L1
diL1
dt= L1
IL1m − IL1p
(1−D −D0)Ts
(13)
Vo = L2
diL2
dt= L2
IL2m − IL2p
(1−D −D0)Ts
. (14)
3) Mode III ((T1 + T2) ≤ t < Ts): This mode starts when
the current through the diode, D becomes zero. The diode
turns off and blocks the current flowing through S5. The cur-
rent path in this mode is Vdc−Load−S4−L2−C1−L1−Vdc
as shown in Fig. 3(c). Since VC1 = Vdc − Vo, the currents in
the inductors will remain unchanged in this mode. Hence,
IL1m = IL1v = −IL2m = −IL2v. (15)
Solving (11)–(15), the expression for the voltage gain can be
obtained as,
Vo
Vdc
= −D
(1−D −D0). (16)
C. Combined operation
From (9) and (16) the common expression for the voltage
gain can be written as,
Vo
Vdc
= sgn(Vo)D
(1−D −D0). (17)
From (1) and (10), it can be inferred that, the expression for
VC1 is different in the positive and in the negative half cycle.
By substituting the expression of VC1 from (1) and (10) to
(2), (3), (5), (6), (11), (12), (13) and (14), the model of the
system can be simplified as follows:
L1
∆IL1
DTs
= L2
∆IL2
DTs
= Vdc (18)
L1
∆IL1
(1−D −D0)Ts
= L2
∆IL2
(1 −D −D0)Ts
= |Vo|. (19)
From Fig. 4, in both the half cycles the expression of
switching time average of the dc side current is obtained as,
Idc = IL1v +∆IL1
2(1−D0). (20)
Further, from Fig. 4 it can be observed that in the positive
half cycle the wave shape of i2 in a switching time period is
different from that in the negative half cycle. Let the switching
time average of i2 is I2, and it can be approximated to be equal
to the grid current, io. It can be noted that, this waveform
is exactly negative to that of iL2 in Cuk mode of operation.
Hence, in this mode, I2 is equal to the switching time average
of iL2 but with a negative sign. Therefore,
|I2|Cuk = IL2v +∆IL2
2(1−D0) . (21)
For SEPIC mode, I2 can be expressed as,
|I2|SEPIC =(1−D −D0)
2(IL1p + IL2p)
=(1−D −D0)
2(∆IL1 +∆IL2). (22)
Considering the system to be loss-less,
Idc
|I2|SEPIC
=Vo
Vdc
=D
(1−D −D0). (23)
Using (18), (20) and (22),
(1 −D −D0)DTsVdc
Leq
2IL1v + (1 −D0)DTsVdc
L1
=(1−D −D0)
D(24)
where Leq = L1||L2. Simplifying (24),
IL1v =DTsVdc
2
[
D
L2
−(1−D −D0)
L1
]
. (25)
If, IL1v has to be positive,
L2
L1
<D
1−D −D0
=Vo
Vdc
(26)
needs to be satisfied. However in that case when Vo becomes
zero at the zero crossing instants as per (26), L2 needs to
assume a negative value which is not possible. Hence the value
of L2 is chosen so that, IL1v remains negative for all possible
operating conditions.
In SEPIC mode of operation, the average current through
L2 is given by,
IL2 = IL2v +∆IL2
2(1−D0)
=DTsVdc
2
[
1−D −D0
L1
−D
L2
]
+DTsVdc
2L2
(1−D0)
= (1−D −D0)DTsVdc
2Leq
=(1−D −D0)
2(∆IL1 +∆IL2). (27)
From (22) and (27) it can be inferred that, I2 is equal to IL2
in SEPIC mode of operation as well. Hence in combined op-
eration, IL2= |I2|, which means that, iL2 can be manipulated
to control io. Since the absolute value of the output current
expression is same in both the half cycles it can be inferred
5
that (25) and (26) are also valid for Cuk mode of operation as
well. Therefore the design condition for L2 remains the same
in both the half cycles.
Substituting IL1v in (20),
Idc =DTsVdc
2
[ D
L2
−1−D −D0
L1
]
+DTsVdc
2L1
(1−D0)
=D2TsVdc
2Leq
. (28)
Since the output voltage and current is sinusoidal and they are
in phase with each other,
Idc(t) = 2Ipv sin2 ωt (29)
wherein, Ipv is the average current drawn from PV module.
Further, Vpv = Vdc and D(t) being positive, its expression can
be written as
D(t) = Dpeak| sinωt| where, Dpeak = 2
√
IpvLeq
TsVpv
(30)
Hence D(t) needs to be a rectified sine wave with an amplitude
of Dpeak. The value of Dpeak will be dictated by the irradiance
level experienced by the solar PV module.
IV. CONTROL CONFIGURATION
In the Fig. 5 the schematic of the control block diagram is
shown. The rms value of the output current is measured and
compared with the reference, I∗orms, which is to be generated
by the MPPT controller. The PI controller processes the error
so obtained to determine Dpeak. A rectified sinusoidal signal
having an amplitude of unity is multiplied with Dpeak to
obtain the instantaneous duty ratio, D(t). The reference sine
wave is generated by employing a single phase PLL. Switching
pulses for S1 are obtained by comparing D(t) with a triangular
carrier wave.
Fig. 5: Block diagram of the control configuration
Switches S2 and S3 are turned on during the positive half
cycle of the reference sine wave to operate the circuit in SEPIC
mode, while S4 and S5 are turned on during its negative half
cycle to operate the circuit in Cuk mode.
V. SELECTION OF PARAMETERS
A. Design of input inductor (L1)
At the limiting condition, when the converter operates at
the verge of discontinuous and continuous mode of operation
at the peak of the grid voltage and operating at the rated
condition,
D ≤vo
vo + Vdc
=Vom
Vom + Vpv
(31)
where, Vom is the amplitude of the grid voltage, vo. At this
instant, the switching time average of iL1 is 2Ipv. Hence,
2Ipv =IL1p
2=
DTsVpv
2L1
⇒ L1 =DTsVpv
4Ipv≤
TsVomVpv
4Ipv(Vpv + Vom)(32)
B. Design of intermediate capacitor (C1)
As the average voltage of vC1 is less in SEPIC mode of
operation, the voltage ripple of C1 is much higher in this mode
compared to the operation of the inverter in the Cuk mode.
Hence the design of C1 is carried out considering the operation
of the converter in SEPIC mode which is as follows,
C1 =∆QC1
∆VC1
=(1 −D −D0)TsIL1p
2Vpv(∆VC1
VC1
)=
(DTs)2Vpv
2VoL1(∆VC1
VC1
).
(33)
C. Design of output inductor (L2)
The switching time average current through L2 is the current
fed to the grid during this interval. The current ripple in L2 is
derived and subsequently the design criterion of L2 is obtained
as follows,
∆IL2 =DTsVdc
L2
⇒ L2 =DVpvTs
Io(∆IL2
IL2
). (34)
D. Design of output capacitor (C2)
The output capacitor is chosen so that the cut off frequency,
fc of the L2−C2 filter is way above the grid frequency, fg, and
way below the switching frequency, fs, i.e. fg << fc << fsand the value of C2 is obtained to be,
C2 =1
4π2f2cL2
(35)
VI. SIMULATED PERFORMANCE OF THE PROPOSED
CONVERTER
TABLE I: Simulation Parameters: (a) system parameters and
(b) converter parameters
Parameters Values
Vdc 35 VVo 220 Vfg 50 Hzfs 100 kHzRo 194 Ω
(a)
Parameters Values
L1, rL1 8 µH, 20 mΩ
L2, rL2 100 µH, 0.6 Ω
C1, rC1 0.47 µF, 30 mΩ
C2, rC2 0.47 µF, 30 mΩ
Lg 1 mH
(b)
Detailed simulation studies of the proposed converter have
been carried out on MATLAB/Simulink platform. For simplic-
ity, the grid is replaced by a load resistance while maintaining
the voltage across this resistance to be equal to 220 V ac.
In a realistic grid connected system, reference output current,
I∗rms would be determined by the MPPT controller. However,
in this simplistic system I∗rms is obtained by employing a PI
controller which maintains the terminal voltage of the inverter
at 220 V. The parameters chosen for the simulation model
6
Fig. 6: Output voltage (vo) and current (io) waveform
Fig. 7: Waveform of the duty ratio, d
Fig. 8: Input inductor current (iL1) over two full cycles (0.04 s)
and expanded view of iL1 from 4.98 ms to 5.02 ms
along with the parasitic series resistances of the converter are
shown in Table I.
The proportional gain Kp and integral gain Ki values of
the PI controller used for controlling Irms are chosen to be
0.5 and 60 s−1 respectively. The inverter is operated with the
system parameters as depicted in Table I(a). The steady state
response of the output voltage and current of the proposed
inverter is shown in Fig. 6. It may be noted that the amplitude
of the sinusoidal output voltage vop of the inverter is 311 V.
Fig. 9: Intermediate capacitor voltage (vC1) waveform
Fig. 10: Output inductor current (iL2) waveform
Fig. 11: Estimated efficiency plot of the proposed inverter
From Fig. 7 it can be inferred that the converter is operated
with the peak duty ratio (Dpeak) of 0.8. The THD of the output
voltage is found to be 1.21%.
The steady state response of the input inductor current is
shown in Fig. 8. It can be inferred from the aforementioned
figures that the converter is operating in DCM.
At steady state, the voltage across the intermediate capac-
itor, C1 is shown in Fig. 9. Form this figure it can be noted
that the waveform of vC1 in the positive half cycle is different
from that in the negative half cycle. This difference arises as
the converter operates in SEPIC mode during positive half
cycle, and in Cuk mode during negative half cycle.
The steady state response of output inductor current, iL2
is shown in Fig. 10. It can be inferred that the waveform is
a rectified sine wave having switching frequency harmonic
components.
The plot of the estimated efficiency of the inverter with
7
Fig. 12: Photograph of the experimental prototype
Fig. 13: Experimental performance: waveform of output volt-
age vo and output current io
respect to the power level is shown in Fig. 11. For efficiency
estimation, the MOSFET, IPW60R024P7 is considered for
S1 and MOSFET, IPW60R037P7 is considered for S2 − S5.
Although the inverter is developing 220 V ac from an input
voltage of 35 V dc, the efficiency of the proposed inverter
is comparable with the inverters which are reported in the
literature for developing 110 V ac from 35-50 V dc [10], [12],
[14].
VII. EXPERIMENTAL VALIDATION
In order to confirm the the viability of the proposed inverter,
a 250 W semi-engineered laboratory prototype of the micro-
inverter is fabricated, and detailed experimental studies have
been carried out. The passive components as mentioned in
Table I(b) are used to realize the prototype. In order to
increase the reliability, thin film capacitors are used. Switch
S1 is realized by the MOSFET, IPW60R024P7 while S2−S5
are realized by MOSFET, IPW60R037P7. The controller of
the inverter is realized by utilising DSP, TMS320F28355. A
1.5 kW programmable power supply (EPS power supply PSI
9360-15) is used as the input dc source. The photograph of
the prototype is shown in Fig. 12.
Fig. 14: Experimental performance: FFT of output voltage
waveform
Fig. 15: Experimental performance: waveform of input induc-
tor current iL1
The measured performance of the inverter is shown Fig. 13
wherein the input voltage is maintained at 35 V dc and
the load resistance of 660 Ω is connected across its output
terminals. It can be noted that the peak of the output voltage
developed across the load resistance is 311 V rms. In Fig. 15
the measured waveform of iL1 is depicted which indicates
that at light load condition the circuit operates in DCM. The
operating efficiency of the inverter while it is made to deliver
73 W is found to be 89.5%. The THD in the output voltage is
3.84% (Fig. 14) which is well within the stipulated standards.
The measured voltage across C1 while the inverter is
operating at steady state is shown in Fig. 16 which resembles
the simulated waveform of Fig. 9. Since in the positive half
cycle, VC1 = Vdc, it can be inferred from Fig. 16 that the input
voltage is maintained at 35 V. In negative half cycle the peak
value of the waveform is around 350 V since it is the sum of
the input voltage and peak of the sinusoidal output voltage,
vo.
The measured steady state current through L2 is shown in
Fig 17. It may be noted that it is polluted with high frequency
switching harmonics. It also shows that for this operating
condition IL2v remains to be positive. However after getting
manipulated by the the unfolding and filtering circuits the
8
Fig. 16: Experimental performance: voltage waveform across
intermediate capacitor C1
Fig. 17: Experimental performance: waveform of output in-
ductor current iL2
output current, io becomes almost sinusoidal current (Fig. 13)
having a THD of 3.84%.
VIII. CONCLUSION
A combined SEPIC-Cuk based micro-inverter topology has
been proposed in this paper. The salient features of the
proposed inverter are as follows,
• it operates in SEPIC mode for positive half cycle and in
Cuk mode for negative half cycle
• the inverter is realized by using single high frequency
switch thereby improving its reliability and cost
• four line frequency switches are employed to interchange
the modes between SEPIC and Cuk mode, and the switch-
ing losses associated with these switches are negligible
• in order to obtain high gain the inverter is made to
operated in DCM. The DCM operation also ensures that
the turn on loss of the high frequency switch is negligible
• the neutral of the PV module is shorted with that of the
grid thereby eliminating the flow of leakage current
The operating principle, detailed mathematical modelling of
the system, design guidelines for the passive elements, control
strategy are presented in the paper. The viability of the micro-
inverter is validated by carrying out detailed simulation and
experimental studies.
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