A multi-chip board for X-ray imaging in build-up technology
Alessandro Fornaini, NIKHEF, Amsterdam4th International Workshop on Radiation Imaging Detectors
Alessandro Fornaini, Ton Boerkamp, Jan Visschers - NIKHEF
Rui de Oliveira - CERN
Hybrid Pixel detectors
Xray
Bumps
Single photon counting
Semiconductor sensorHigh purity, single
crystal (Si, GaAs, ..)
CMOS electronics
Pixel diode
Single pixelRead Out cell
300 - 600 m
55 m
1
Hybrid Pixel detectors (2)
Problem: size limitations!
Sensor size: not a problem (~15 cm diam. high res. Si)
CMOS chip size: max. 25 x 25 mm2 due to reticle size of wafer stepper (Medipix2: 0.25m technology, area 14 x 16 mm2)
Non-standard production techniques (“stitching”) to circumvent this but:1) Expensive2) Yield inversely proportional to chip area! (due to density of point defects and contaminations)
2
Our solution: tiled array of chips
Medipix2 setup:
Muros23.3V
PC with Medisoft4and NI DIO card
Muros2 interface
Chipboard with 2 X 4 tiled ASICchips Medipix2
512 x 1024 Pixels
Si sensor,28 x 56 mm2
Bump bonded
Bias
3
Other tiled arrays
System Pixel size [m2]
Circuit size [mm2]
Sensor area [mm2]
Array (circuits per sensor)
Pixels per circuit
Total # of pixels
Omega3 / LHC1
50 x 500 6.4 x 8.0 307 1x6 2048 12 k
Alladin
RAL-UK
150 x 150 9.6 x 9.6 645 1x7 4096 29 k
Atlas
CERN
50 x 400 7.2 x 8.0 990 2x8 2880 47 k
LHCb
CERN
50 x 425 12.8 x 13.6 984 1x7 8192 57 k
Medipix2 55 x 55 14.1 x 14.1 1590 2x4 65536 524 k
4
Medipix2 setup
8 Medipix2 ASIC chips, 14 X 16 mm2
1 High Res. Si sensor, 28 X 56 mm2
Chipboard in Chip-on-Board technology
Interface card to PCI DIO card (Muros2)
Sensor bias voltage supply (commercial)
PC with HS DIO board (commercial)
Medipix2 Interconnectivity
Medipix2 chip #N
Medipix2 chip #N+1
Common single-ended CMOS bus: shutter, mode control, reset,polarity and analog signals (test input, DAC output)
Serial Daisy ChainToken passing protocol (LVDS)160 Mhz CLK1 Mbit data per chip160 Mhz 160/Ntot frames/sec
LVDS (Low Voltage Differential Signal)Reduce: noise generation, noise sensitivity, interconnectivityBetter performance for large arrays
DATA
CLK
ENABLE
5
Routing
Top layer metal 1, 2:Vdd, Gnd and LVDStoken ring 160 Mhz!
Layers 3, 4, 5 metal:Common CMOSbus 1
36
8
7 2
5 4
Connector
Pitch of wirebonds = 120 m, NO FANOUTInterconnection: High Density Interconnect (HDI) technology
Chip-on-Board (COB) technology
6
Interconnections
From: IPC/JPCA-2315Design Guide for High Density Interconnects (HDI)
High Density Interconnect (HDI) Build-up technology
Staggered Micro-Via’s
(photolitographic etching)7
Box
Medipix 2
Pixel Sensor
Capacitor
GND VD
D-L
VD
S
VDD
VD
DA
VbiasBeryllium Foil
Contr
ols
FET switchPeltier Coolercl
ock
data
toke
n
GndGndbusXbusYbusXVDDVDDAVDDLGND
< 6 mm
Multilayer board
9 layers (4 metal, 5 build-up)8
Test Pulse
FET switchDAC 1
DAC 2
to input analog test Medipix2 chip
FPGA
Muros2Muros2
Medipix2 chipboardMedipix2 chipboard
9
Multilayer board (2)
5 built-up layers:
15 m Cu
50 m Kapton
Metal 1: 100 dual tracks for LVDS line
Metal 1,2: Gnd
Metal 3, 4, 5: 50 tracks for CMOS bus
4 layers:Standard Printed Wire Board
70 m Cu
350 m Epoxy
Metal 6: Vdd
Metal 7: Vdd-LVDS
Metal 8: Vdda
Metal 9: Gnd
1.6 mm total thickness, area 53 x 110 mm2
10
Via’s and Tracks dimensions
1840 micro-via’s
366 through via’s
80 SMD capacitors
8 CMOS FET’s Width
[m]Clearance
[m]Pitch[m]
CMOS Track 60 50 110
LVDS Track 80 70 150
Micro-via 180 70 250
Through-via 350 150 500
Capacitor
clock
data
toke
n
spare
VD
DA
micro via's& Bond Pads
through via
11
Chipboard layout
Chip bond pads
Decouplingcapacitors
Powerbars
LVDSpairs
FET switch,capacitors Test points
121 cm
Vbias connector
SCSI-5connector
2 x 4 Medipix2 chip array
Chipboard layout
13
1 cm
… and the actual chipboard
SCSI-5connector
Vbias connector
2 x 4 MPix2 chip array
Powerbars
LVDSpairs
141 cm
Powerbars
LVDSpairs
15
1 cm
16
1 cm
Status
16 prototypes boards produced at CERNConnectivity tests performed on 3 boards:
NO DESIGN ERRORS!But: production defects (1 short, 2 connections easily solvable)
Work in progress! Currently:- Evaluating different glues- Gluing and wire bonding- Testing LVDS line with 8 Medipix2 chips (no sensor) mounted on the chipboard
Planning (~ 1 month):Testing connections with MPix2 chipsCritical: communication speed tests (160 Mhz?)
17
Conclusion
16 Medipix2 2 x 4 chipboards have been produced.Testing is still going on but up to now results are very promising
A 2 x 2 sensor will be mounted and tested.We expect to have a 2 x 4 multichipboard running in ~ 6 months
18
Tiled array: chips boundary
Chip separation: 220 m (4 pixels)Sensor: pixels at boundary 55 x 55 m2 55 x 165 m2
55 m 220 m
165 m
NO DEAD AREA but: non uniformity (resolution, overflow)