A Living Roadmap for SemiconductorsA Living Roadmap for Semiconductors
October 4, 2000 SRC Review
Andrew B. KahngUCSD CSE and ECE Departments*
* effective January 1, 2001
SRC Review 001004 abk 2
OutlineOutline
The Design The Design TechnologyTechnology Gap and the GSRC C.A.D. Theme Gap and the GSRC C.A.D. Theme On RoadmapsOn Roadmaps The GSRC Technology Extrapolation (GTX) System: The GSRC Technology Extrapolation (GTX) System:
Toward a Living RoadmapToward a Living Roadmap A Living Roadmap for Semiconductors (and Design)A Living Roadmap for Semiconductors (and Design)
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Motivation: The Design Motivation: The Design TechnologyTechnology Gap Gap
Design Productivity Gap Design Productivity Gap Well-documented, threatens quality and value of designsWell-documented, threatens quality and value of designs huge cost to semiconductor industryhuge cost to semiconductor industry
Most research: change the Design Problem, invent new algorithms... Most research: change the Design Problem, invent new algorithms...
Premise of MARCO GSRC “Calibrating Achievable Design” Theme: Premise of MARCO GSRC “Calibrating Achievable Design” Theme: Design Productivity GapDesign Productivity Gap == == Design Technology Productivity GapDesign Technology Productivity Gap
Problem: Must improve Time-To-Market and Quality-of-Result for Problem: Must improve Time-To-Market and Quality-of-Result for Design Design TechnologyTechnology
Goal: improve CAD Industry Productivity by changing how we Goal: improve CAD Industry Productivity by changing how we specifyspecify, , developdevelop, and , and measuremeasure andand improveimprove Design Technology Design Technology
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Facets of the Design Technology GapFacets of the Design Technology Gap FacetsFacets
No clear industry-wide R&D agendaNo clear industry-wide R&D agenda Time-to-Market: 5-7 years to get a leading-edge algorithm into production EDA Time-to-Market: 5-7 years to get a leading-edge algorithm into production EDA
designers battle today’s design problems with yesterday’s design technologydesigners battle today’s design problems with yesterday’s design technology QOR: difficult to evaluate impact of new tools on overall design process QOR: difficult to evaluate impact of new tools on overall design process QOR: published descriptions insufficient for replication or even comparison of QOR: published descriptions insufficient for replication or even comparison of
algorithmsalgorithms CAD R&D cannot CAD R&D cannot identifyidentify, , evaluateevaluate or or reusereuse the CAD technology leading edge the CAD technology leading edge
research and innovation stallresearch and innovation stall CausesCauses
Lack of clear roadmapping for Design Technology w.r.t. ITRS, application marketsLack of clear roadmapping for Design Technology w.r.t. ITRS, application markets Lack of “Foundation CAD-IP”: Lack of “Foundation CAD-IP”: interoperableinteroperable, , reusablereusable, , commoditycommodity infrastructure infrastructure Lack of resources, and relative over-resourcing of non-strategic, de facto Lack of resources, and relative over-resourcing of non-strategic, de facto
commodity technologycommodity technology Lack of standard metrics, benchmarks for Design TechnologyLack of standard metrics, benchmarks for Design Technology More maturity needed w.r.t. control, strategic-vs-commodity distinction, etc.More maturity needed w.r.t. control, strategic-vs-commodity distinction, etc.
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Goal: Improved Design Goal: Improved Design TechnologyTechnology Productivity Productivity The GSRC C.A.D. Theme promotes mature, coopetitive cultures and shared, The GSRC C.A.D. Theme promotes mature, coopetitive cultures and shared,
open infrastructures that lead to improved open infrastructures that lead to improved creationcreation of design technology of design technology Improved vision and design technology planning (Improved vision and design technology planning (“specify”“specify”): ):
What will the design problem look like? What do we need to solve?What will the design problem look like? What do we need to solve?
Improved execution (Improved execution (“develop”“develop”): ): How can we quickly develop the right design technology (TTM)?How can we quickly develop the right design technology (TTM)?
Improved measurement (Improved measurement (“measure“measure andand improve”improve”):): Did we solve the problem (QOR)? Did the design process improve? Did we Did we solve the problem (QOR)? Did the design process improve? Did we
increase the envelope of achievable design?increase the envelope of achievable design?
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““A Vision of the Future”A Vision of the Future” Improved vision and design technology planning (“specify”): Improved vision and design technology planning (“specify”):
What will the design problem look like? What do we need to solve?What will the design problem look like? What do we need to solve? Accurate roadmapping for Design (and Process) Technology (“Living Roadmap”)Accurate roadmapping for Design (and Process) Technology (“Living Roadmap”)
1.5x more focused R&D resources1.5x more focused R&D resources
Improved execution (“develop”): Improved execution (“develop”): How can we quickly develop the right design technology (TTM)?How can we quickly develop the right design technology (TTM)?
Reusable, commodity, Foundation CAD-IP (+ academic publication standards)Reusable, commodity, Foundation CAD-IP (+ academic publication standards) reduce TTM to 2-3 yrs, 2x better leveraged R&D and academic resources, 2x increase in “searched reduce TTM to 2-3 yrs, 2x better leveraged R&D and academic resources, 2x increase in “searched
solution space” (mix-and-match flow optimizations)solution space” (mix-and-match flow optimizations)
Improved measurement (“measure and improve”):Improved measurement (“measure and improve”): Did we solve the problem (QOR)? Did the design process improve? Did we increase the envelope of Did we solve the problem (QOR)? Did the design process improve? Did we increase the envelope of
achievable design?achievable design? Design tool/process metrics, design process instrumentation and CPIDesign tool/process metrics, design process instrumentation and CPI
1.5x increase in “searched solution space” (flow and process optimizations)1.5x increase in “searched solution space” (flow and process optimizations)
Design Technology Productivity improves Design ProductivityDesign Technology Productivity improves Design Productivity
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OutlineOutline
The Design The Design TechnologyTechnology Gap and the GSRC C.A.D. Theme Gap and the GSRC C.A.D. Theme On RoadmapsOn Roadmaps The GSRC Technology Extrapolation (GTX) System: The GSRC Technology Extrapolation (GTX) System:
Toward a Living RoadmapToward a Living Roadmap A Living Roadmap for Semiconductors (and Design)A Living Roadmap for Semiconductors (and Design)
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What is Roadmapping? (Ideally...)What is Roadmapping? (Ideally...)
““Roadmapping drives development of (e.g., CAD) technology”:Roadmapping drives development of (e.g., CAD) technology”: System architects, designers, CAD managers use roadmaps to determineSystem architects, designers, CAD managers use roadmaps to determine
tough problemstough problems risks, …risks, …
EDA suppliers use roadmaps to determineEDA suppliers use roadmaps to determine R&D investmentR&D investment product pipelineproduct pipeline
Government and consortia use roadmaps to determine levels of investmentGovernment and consortia use roadmaps to determine levels of investment
““Roadmaps serve as a guide to the most promising directions, the Roadmaps serve as a guide to the most promising directions, the most critical problems”most critical problems”
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What is a Roadmap? (In reality...)What is a Roadmap? (In reality...) Self-fulfilling prophecy ?Self-fulfilling prophecy ?
Moore’s Law: (Circuits per chip) = 2(year-1975)/1.5 (Gordon Moore, 1975 IEDM) “More than anything, once something like this gets established, it becomes more or less a self-fulfilling
prophecy. The Semiconductor Industry Association puts out a technology road map, which continues this generation [turnover] every three years. Everyone in the industry recognizes that if you don't stay on essentially that curve they will fall behind. So it sort of drives itself.” (Gordon Moore, 1996)
Always wrong, yet comprised of meta-laws ?Always wrong, yet comprised of meta-laws ? Reasons for Moore’s Law (1975): die size growth, feature size decrease, circuit/device cleverness
Gordon Moore, 1975: "There is no room left to squeeze anything out by being clever. Going forward from here we have to depend on the two size factors - bigger dice and finer dimensions.” (Gordon Moore, 1995)
Geopoliticoeconomic ?Geopoliticoeconomic ? QUIZ: Rank the following four regions by decreasing order of aggressiveness in feature size:
United States, Japan, Europe, East Asia
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What is a Roadmap? (In reality...)What is a Roadmap? (In reality...)
SensitiveSensitive Example 1: Cell Area Factor for memory
Scenario 1: 8x/1999 2.5x/2014 Scenario 2: 8x/1999 4x/2016
Example 2: Litho Field Size Maximum Limit Scenario 1: 4x magnification, 6-inch reticle (800mm2 intro, 400 mm2 production) Scenario 2: 5x magnification, 6-inch reticle (572mm2 intro, 286 mm2 production)
Example 3: L2 Cache Size for High-Perf MPU (baseline of ramp going forward) Scenario 1: 2MB on-chip 6t SRAM 170mm2 core + 280mm2 SRAM = 450mm2 in 1999 Scenario 2: 1MB on-chip 6t SRAM 170mm2 core + 140mm2 SRAM = 310mm2 in 1999
QUIZ: By what factor will the high-performance MPU transistor count at the end of the Roadmap change if we switch between Scenario 1 and Scenario 2 ?
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What is a Roadmap? (In reality...)What is a Roadmap? (In reality...) Always evolvingAlways evolving
In: gate length “in resist” vs. “physical”, CMP dishing, SOC complexity, ...In: gate length “in resist” vs. “physical”, CMP dishing, SOC complexity, ... Out: NRE cost of logic (including design cost!), ...Out: NRE cost of logic (including design cost!), ... In flux : “in volume production”, “no known solution”, “high-perf MPU”, ...In flux : “in volume production”, “no known solution”, “high-perf MPU”, ...
Conflicted between Forecasts vs. Statements of NeedsConflicted between Forecasts vs. Statements of Needs “a statement of technology needs in various areas, driven by a forecast of lithography
capability” (D. Jensen, AMD) “a hybrid of the ‘most realistic aggressive’ targets, balanced by the tension created by the
‘red’ limits of ‘unknown solutions’” (A. Allan, Intel) Paralyzed by dependencies
“who owns #package pins/balls?” Test? Assembly/Packaging? Design? how does one go about changing a number, checking for interactions ?
Law of Roadmaps: If it’s worth roadmapping, it can’t be roadmapped.
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1994
19971998/1999
500
350
250
180
130
100
70
50
35
25
DRAM Half Pitch
MPU/ASIC Gate “Physical”
MPU/ASIC Gate “In Resist”
90
65
45
33
23
~.7x per technology node (.5x per 2 nodes)
Year of Production
and
MPU
/ASI
C G
ate
Leng
th M
inim
um F
eatu
re S
ize
(nm
)
Tech
nolo
gy N
ode
- DR
AM
Hal
f-Pitc
h (n
m)
Technology Node
Minimum Feature
[1.0][1.5][2.0]
Scenarios:
1695 97 99 01 04 07 10 13 16
95 97 99 01 04 07 10 13 16
ITRS AccelerationITRS Acceleration
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What Should a Roadmap Be? (More Practically...)What Should a Roadmap Be? (More Practically...)
Comprehensive and “best possible”Comprehensive and “best possible” RobustRobust Flexible and adaptiveFlexible and adaptive
““A Living Roadmap” ???A Living Roadmap” ???
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OutlineOutline
The Design The Design TechnologyTechnology Gap and the GSRC C.A.D. Theme Gap and the GSRC C.A.D. Theme On RoadmapsOn Roadmaps The GSRC Technology Extrapolation (GTX) System: The GSRC Technology Extrapolation (GTX) System:
Toward a Living RoadmapToward a Living Roadmap A Living Roadmap for Semiconductors (and Design)A Living Roadmap for Semiconductors (and Design)
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Technology ExtrapolationTechnology Extrapolation
Evaluates impact Evaluates impact ofof design technologydesign technology process technologyprocess technology
Evaluates impact Evaluates impact onon achievable designachievable design associated design problemsassociated design problems
What do we need to solve?What do we need to solve?
What will the design problem look like ?What will the design problem look like ?
== Roadmapping to drive Design Technology== Roadmapping to drive Design Technology
How and when do L, SOI, How and when do L, SOI, SER, etc. matter?SER, etc. matter?
What is the most power-efficient noise What is the most power-efficient noise management strategy?management strategy?
Will layout tools need to perform Will layout tools need to perform process simulation to effectively model process simulation to effectively model
cross-die and cross-wafer cross-die and cross-wafer manufacturing variation?manufacturing variation?
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Most commonly used optimal repeater sizing expression Most commonly used optimal repeater sizing expression (Bakoglu)(Bakoglu)
New study:New study: Sweep repeater size for single stage in the chain Sweep repeater size for single stage in the chain Examine both delay and energy-delay productExamine both delay and energy-delay product
Optimal Repeater SizingOptimal Repeater Sizing
in
DCRCRS
int
int
0 100 200 300 400 500
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Bakogluoptimal sizing
Lseg = 2.14 mm W=S=1m W=S=0.5m
Crit
ical
Pat
h D
elay
(ns)
Repeater Size (X min size)
1
2
3
4
5
6
Norm
alized Energy-Delay Product
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Elastic scattering
Diffuse scattering
Effect of Electron ScatteringEffect of 5 nm Barrier• Conformal 5 nm barrier assumed• Even a 5 nm barrier will increase resistivity drastically
• No barrier assumed• Electron scattering increases resistivity• Lowering temperature has a big effect
525320250
95 58 48
280170133
ITRS 1999 Line width (nm)GlobalSemiglobalLocal
source: MARCO IFRC
Cu Resistivity: Effect of Line Width ScalingCu Resistivity: Effect of Line Width Scaling
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Technology Extrapolation TodayTechnology Extrapolation Today
Many RoadmapsMany Roadmaps ITRS, JISSO, STARC, … RoadmapsITRS, JISSO, STARC, … Roadmaps University tools: SUSPENS, GENESYS, RIPE, BACPAC, …University tools: SUSPENS, GENESYS, RIPE, BACPAC, … Industry tools: HIVE/AIM, ...Industry tools: HIVE/AIM, ...
ObservationsObservations everyone predicts “same” parameters but different assumptions, inputs: everyone predicts “same” parameters but different assumptions, inputs:
near-total duplication of effort !!!near-total duplication of effort !!! no documentation or visibility into internal calculationsno documentation or visibility into internal calculations ““hard-wired” hard-wired” cannot easily test other modeling choices cannot easily test other modeling choices missing: models of CAD tools and optimizations (what is really missing: models of CAD tools and optimizations (what is really
“achievable”?)“achievable”?) missing: scope, comprehensive coveragemissing: scope, comprehensive coverage
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FlexibilityFlexibility edit or define new parameters and relations between themedit or define new parameters and relations between them perform specific studies (but different studies at different times)perform specific studies (but different studies at different times)
QualityQuality continuous improvementscontinuous improvements world-wide participation of expertsworld-wide participation of experts
TransparencyTransparency open-source mechanismopen-source mechanism models visible to the usermodels visible to the user
No more redundant effortNo more redundant effort permanent repository of first choicepermanent repository of first choice adoptability and maintainabilityadoptability and maintainability
A A SharedShared Technology Extrapolation System Technology Extrapolation System
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GTX: GSRC Technology Extrapolation SystemGTX: GSRC Technology Extrapolation System GTX = framework for shared technology extrapolationGTX = framework for shared technology extrapolation ““Living Roadmap”: Repository, sanity-checker for 2001 Living Roadmap”: Repository, sanity-checker for 2001
ITRS renewal (via US Design TWG, (inter-) ITWG activity)ITRS renewal (via US Design TWG, (inter-) ITWG activity)
Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/
Parameters (data)
Rules (models)
Rule chain (study)
Knowledge
Engine (derivation)
GUI (presentation)
ImplementationUser inputs
Pre-packaged
GTX
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Knowledge RepresentationKnowledge Representation
Human-readable ASCII grammarHuman-readable ASCII grammar
#rule #rule BACPAC_dl_chipBACPAC_dl_chip#description#description#output#outputdouble {m} dl_chipdouble {m} dl_chip;;
#inputs#inputsdouble {m^2} dA_chipdouble {m^2} dA_chip;;
#body #body sqrt(dA_chip)sqrt(dA_chip)#reference#reference#endrule#endrule
#parameter #parameter dl_chipdl_chip#type #type doubledouble#units {#units {mm}}#default#default1e-21e-2
#description#descriptionchip side lengthchip side length
#reference#reference#endparameter#endparameter
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Knowledge RepresentationKnowledge Representation
Human-readable ASCII grammarHuman-readable ASCII grammar
Benefits:Benefits: Easy creation/sharing of parameters/rules by multiple usersEasy creation/sharing of parameters/rules by multiple users
D. Sylvester and Y. Cao: device and power, SOI modules that “drop in” to GTXD. Sylvester and Y. Cao: device and power, SOI modules that “drop in” to GTX P.K. Nag: Yield modelingP.K. Nag: Yield modeling
Extensible to models of arbitrary complexity (specialized prediction Extensible to models of arbitrary complexity (specialized prediction methods, technology data sets, optimization engines)methods, technology data sets, optimization engines) Avant! Apollo or Cadence SE P&R tool: just another wirelength estimatorAvant! Apollo or Cadence SE P&R tool: just another wirelength estimator
Applies to any domain of work in semiconductors, VLSI CADApplies to any domain of work in semiconductors, VLSI CAD Transistor sizing, single wire optimizations, system-level wiring predictions,…Transistor sizing, single wire optimizations, system-level wiring predictions,…
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ParametersParameters Description of technology, circuit and design attributesDescription of technology, circuit and design attributes Importance of consistent naming cannot be overstatedImportance of consistent naming cannot be overstated
Naming conventions for parametersNaming conventions for parameters[<preposition>] _ <[<preposition>] _ <principalprincipal> _ {[> _ {[qualifierqualifier] _ <] _ <placeplace>} _ {<>} _ {<qualifierqualifier>} _ [<>} _ [<adverbialadverbial>] _ [<>] _ [<indexindex>] _ [<>] _ [<unitunit>]>]
Example:Example: rr__intint__tottot__lyrlyr__pu_dlpu_dlRequirements:Requirements:
Relatively easy to understand parameter from its nameRelatively easy to understand parameter from its name Distinguishable (no two parameters should have the same name)Distinguishable (no two parameters should have the same name)
r_int (interconnect resistance) = r_int (interconnect resistivity) ? Unique (no two names for the same parameter)Unique (no two names for the same parameter)
R_int = R_wire ? Sortable (important literals come first)Sortable (important literals come first)
Software to automatically check parameter namingSoftware to automatically check parameter naming
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RulesRules Methods to derive unknown from known parametersMethods to derive unknown from known parameters ASCII rulesASCII rules
Laws of physics, models of electrical behavior, statistical modelsLaws of physics, models of electrical behavior, statistical models Include closed-form expressions, vector operations, tablesInclude closed-form expressions, vector operations, tables Storing of calibration data (e.g., “technology files”) for known process and design Storing of calibration data (e.g., “technology files”) for known process and design
points in lookup tablespoints in lookup tablesConstraints, uConstraints, used to limit range during “sweeping”sed to limit range during “sweeping”
““External executable” rulesExternal executable” rules Assume a callable executable (e.g., PERL script)Assume a callable executable (e.g., PERL script) Use command-line interface and transfer through filesUse command-line interface and transfer through files Allow complex semantics of a ruleAllow complex semantics of a rule
““Code” rulesCode” rules Implemented in C++ and linked into the inference engineImplemented in C++ and linked into the inference engine
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Rule ChainsRule Chains ““Rule chains” guide inferenceRule chains” guide inference
Acyclic set of rules Acyclic set of rules Interactive specification and comparison of alternative modeling choicesInteractive specification and comparison of alternative modeling choices
StudiesStudies Input values + rules that makeInput values + rules that make
a rule chaina rule chain User-controlled and savableUser-controlled and savable ““Sweeping” of a rule chainSweeping” of a rule chain
Evaluation of all combinationsEvaluation of all combinationsof multi-valued inputsof multi-valued inputs
Example: clock frequency forExample: clock frequency fordifferent Rent exponents anddifferent Rent exponents andvarying logic depth varying logic depth
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GTX EngineGTX Engine
Contains no domain-specific knowledgeContains no domain-specific knowledge Evaluates rules in topological orderEvaluates rules in topological order Performs studiesPerforms studies Multiple values through “sweeping”Multiple values through “sweeping”
Runs on three platforms (Solaris, Windows and Linux)Runs on three platforms (Solaris, Windows and Linux)
URL: http://vlsicad.cs.ucla.edu/GSRC/GTX/URL: http://vlsicad.cs.ucla.edu/GSRC/GTX/
Parameters (data)
Rules (models)
Rule chain (study)
Knowledge
Engine (derivation)
GUI (presentation)
ImplementationUser inputs
Pre-packaged
GTX
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Graphical User Interface (GUI)Graphical User Interface (GUI)
Provides user interactionProvides user interaction
Visualization (plotting, printing, saving to file)Visualization (plotting, printing, saving to file)
4 views:4 views: ParametersParameters RulesRules Rule chainRule chain Values in chainValues in chain
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Change parameter values and observe resulting difference Change parameter values and observe resulting difference in outputsin outputs
Sensitivity Analysis of Cycle-time Models: Sensitivity Analysis of Cycle-time Models: Parameter SensitivityParameter Sensitivity
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Sensitivity Analysis of Cycle-time Models: Model Sensitivity Analysis of Cycle-time Models: Model SensitivitySensitivity Replace rule in a model’s rule chain by another model’s Replace rule in a model’s rule chain by another model’s
rule and observe the difference in outputsrule and observe the difference in outputs
BACPAC BACPAC with rule from Fisher
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Staggered repeatersStaggered repeaters Introduced in [Kahng et al, VLSI Design 99] to reduce delay and noiseIntroduced in [Kahng et al, VLSI Design 99] to reduce delay and noise
Delay Uncertainty StudyDelay Uncertainty Study
SOI (NS)
bulk (NS)SOI (S)
bulk (S)
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OutlineOutline
The Design The Design TechnologyTechnology Gap and the GSRC C.A.D. Theme Gap and the GSRC C.A.D. Theme On RoadmappingOn Roadmapping The GSRC Technology Extrapolation (GTX) System: The GSRC Technology Extrapolation (GTX) System:
Toward a Living RoadmapToward a Living Roadmap A Living Roadmap for Semiconductors (and Design)A Living Roadmap for Semiconductors (and Design)
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GTX StatusGTX Status Recent DevelopmentsRecent Developments
GTX is multi-platform, open-source (MIT license)GTX is multi-platform, open-source (MIT license) many industry downloads; basis of development project at eSilicon (?)many industry downloads; basis of development project at eSilicon (?)
Third release of GTX: September 3, 2000Third release of GTX: September 3, 2000 namespaces, partial rule chain evaluation, vector types, etc.namespaces, partial rule chain evaluation, vector types, etc.
Models/studies implemented: Models/studies implemented: cost/yield (CMU), SOI device/power (Synopsys/Berkeley), RLC interconnect modeling and cost/yield (CMU), SOI device/power (Synopsys/Berkeley), RLC interconnect modeling and
optimization (SGI/UCLA/Synopsys/Berkeley/Sun), routability and layer assignment (UCLA/Ghent)optimization (SGI/UCLA/Synopsys/Berkeley/Sun), routability and layer assignment (UCLA/Ghent) GENESYS, RIPE source code translation into GTXGENESYS, RIPE source code translation into GTX
Near-Term FuturesNear-Term Futures Functionality: annotations, “intelligence”, more direct Roadmap supportFunctionality: annotations, “intelligence”, more direct Roadmap support Models/studies: RLC interconnect noise/delay, manufacturing variability, clock distribution, Models/studies: RLC interconnect noise/delay, manufacturing variability, clock distribution,
DRAM/logic implementation tradeoffs, packaging tradeoffs, device layout density, ...DRAM/logic implementation tradeoffs, packaging tradeoffs, device layout density, ... GTX = repository for ITRS-2001 ORTCs (“transparent, living Roadmap”)GTX = repository for ITRS-2001 ORTCs (“transparent, living Roadmap”)
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Roadmapping ChallengesRoadmapping Challenges Valuation, evaluation of Design and Design Technology
scope and definition of design technology, design processes ?formal metrics for QOR, effectiveness of design technology ?cost measures for design ? (e.g., as part of semiconductor NRE $)
Real linkage between Design, other TWGs in ITRS-2001 effortTest, Interconnect, Litho, PIDS, FEP, Assembly/Packaging, ...goal: consistency and integrity of ITRS
Contributions from across the semiconductor process and design communitiesbest known methods and models; best known data
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The GSRC C.A.D. Theme promotes mature, coopetitive cultures and shared, open The GSRC C.A.D. Theme promotes mature, coopetitive cultures and shared, open infrastructures that lead to improved infrastructures that lead to improved creationcreation of design technology (see: of design technology (see: http://vlsicad.cs.ucla.edu/GSRC/ )http://vlsicad.cs.ucla.edu/GSRC/ )
Improved vision and design technology planning (Improved vision and design technology planning (“specify”“specify”): ): What will the design problem look like? What do we need to solve?What will the design problem look like? What do we need to solve? Answer: “Living Roadmap” (The GSRC Technology Extrapolation (GTX) System)Answer: “Living Roadmap” (The GSRC Technology Extrapolation (GTX) System)
Improved execution (Improved execution (“develop”“develop”): ): How can we quickly develop the right design technology (TTM)?How can we quickly develop the right design technology (TTM)? Answer: CAD-IP Reuse (The GSRC Bookshelf for Fundamental CAD-IP)Answer: CAD-IP Reuse (The GSRC Bookshelf for Fundamental CAD-IP)
Improved measurement (Improved measurement (“measure“measure andand improve”improve”):): Did we solve the problem (QOR)? Did the design process improve? Did we increase the Did we solve the problem (QOR)? Did the design process improve? Did we increase the
envelope of achievable design?envelope of achievable design? Answer: Design Process Instrumentation, Optimization (METRICS)Answer: Design Process Instrumentation, Optimization (METRICS)
Toward Improved Design Toward Improved Design TechnologyTechnology Productivity Productivity
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U.S. Design Technical Working Group for ITRS-2001 renewalU.S. Design Technical Working Group for ITRS-2001 renewalstructure, scope, content, links for Design, System Drivers chaptersstructure, scope, content, links for Design, System Drivers chapters
IEEE DATC Electronic Design Processes SubcommitteeIEEE DATC Electronic Design Processes [email protected] ; EDP Workshop (April, Monterey CA)[email protected] ; EDP Workshop (April, Monterey CA)
MARCO GSRC C.A.D. ThemeMARCO GSRC C.A.D. ThemeBookshelf for CAD-IP Reuse, METRICS InitiativeBookshelf for CAD-IP Reuse, METRICS Initiativehttp://vlsicad.cs.ucla.edu/GSRC/http://vlsicad.cs.ucla.edu/GSRC/
GTXGTXnew models and studies ; usability, use model feedbacknew models and studies ; usability, use model feedback
My contact info: [email protected] contact info: [email protected]
Make Your Contribution !!!Make Your Contribution !!!
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““The Design Productivity Gap”The Design Productivity Gap”
Equivalent Added Complexity
68 %/Yr compoundedComplexity growth rate
21 %/Yr compoundProductivity growth rate
Year Technology Chip Complexity Frequency Staff Staff Cost* 3 Yr. Design
1997 250 nm 13 M Tr. 400 MHz 210 90 M
1998 250 nm 20 M Tr. 500 270 120 M
1999 180 nm 32 M Tr. 600 360 160 M
2002 130 nm 130 M Tr. 800 800 360 M
* @ $ 150 k / Staff Yr. (In 1997 Dollars)
Logic Tr./Chip Tr./S.M.
““How many gates How many gates can I get for $N?”can I get for $N?”
Source: SEMATECHSource: SEMATECH
$1$1$3$3
$10$10
Potential Design Complexity and Designer Productivity
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0%20%40%60%80%
100%
1999
2002
2005
2008
2011
2014
% Area Memory
% Area ReusedLogic
% Area New Logic
Percent of die area that must be occupied by memory to maintain SOC design productivity
Design Productivity Gap Design Productivity Gap Low-Value Designs? Low-Value Designs?
Source = Japanese system-LSI industry
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““Roadmap Process and Its Implications” (Ideally...)Roadmap Process and Its Implications” (Ideally...)
Basic TechnologicalAssumptions
Basic MethodologicalAssumptions
Implications tothe Community
Models andDiscussion
Translation to SpecificResearch Agendas
“Timing closure is a hard problem and will only get harder”
“We will fund research ontiming-aware partitioning”
Research Proposedto Implement Agenda R. Newton, ICCAD99 panel
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““Roadmap Process” (More Practically...)Roadmap Process” (More Practically...)
Basic TechnologicalAssumptions
Basic MethodologicalAssumptions
Implications tothe Community
Models andDiscussion
Couched in Terms ofRoadmap Implications
“Timing closure is a hard problem and will only get harder”
Research Proposed to Solve Hard Problem
“I can make a breakthrough in technology or methodology”
“Here’s how my work is critical for addressing your problem”
Newmodels
R. Newton, ICCAD99 panel
SRC Review 001004 abk 40
Five different interconnect modelsFive different interconnect models Bakoglu’s model (RC)Bakoglu’s model (RC) [Alpert, Devgan and Kashyap, ISPD 2000] (RC)[Alpert, Devgan and Kashyap, ISPD 2000] (RC) [Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC)[Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC) [Kahng and Muddu, TCAD 1997] (RLC)[Kahng and Muddu, TCAD 1997] (RLC) Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC)Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC)
RLC Interconnect Delay ApproximationRLC Interconnect Delay Approximation
25
75
125
175
225
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0Wire Length (mm)
Wire
Del
ay (p
s)
RC_ADK
RC_B
RLC_ADK
RLC_IFN
RLC_KM
HSPICE
25
45
65
85
105
125
145
0.4 0.6 0.8 1.0 1.2 1.4Wire Width (µm)
Wire
Del
ay (p
s)
RC_ADK
RC_B
RLC_ADK
RLC_IFN
RLC_KM
HSPICE
SRC Review 001004 abk 41
Cu Resistivity: Barrier Deposition TechnologyCu Resistivity: Barrier Deposition Technology
Atomic Layer Deposition (ALD)
Ionized PVD
Collimated PVD
• 5 nm barrier assumed at the thinnest spot• No scattering assumed, I.e., bulk resistivity
Interconnect dimensions scaled according to ITRS 1999
source: MARCO IFRC