1
Advanced Digital IC-Design
Technology Scaling
Content
What happens when technology is scaled?0.1 mμ gy
9nm
Gate DrainSourceGate DrainSource
Substrate
Substrate
IC Design Space
Traditionaldesign space
New technologies give a new design
space
Spee
d
Com
plex
ity
design space space
Area Power
Flexib
ility
NewDesignSpace
Progress: Described by Gordon Moore
”The complexity for
Moore’s law, formulated 1965
The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”
” no reason to believe ”… no reason to believe it will not remain nearly constant for at least 10 years”
Source: Electronics, Volume 38, Number 8, 19 April 1965
2
Moore’s Law: Processors
Reformulated by Moore 1975The # of transistors will be doubled every 18th month
Example: 30 nm Transistor
Gate
p-
n+ n+
DrainSource
substratSource: Intel
Intel 20 nm Transistor ITRS
International Technology Roadmap for SemiconductorsSemiconductors
Estimate of future technologies in a 15 year perspective
New estimate every second yearNew estimate every second year
http://public.itrs.net/
3
ITRS System Drivers
MPU (Micro Processor Unit)SoC (System-on-Chip)( y p)- Multi technology (digital, analog, and mixed)- High Performance (high speed)- Low PowerAM/S (Analog & Mixed Signal)DRAM (Dynamic RAM)
Technology predictions from four scenarios
Where are we in about 10 years?
[nm]Vi
Channel length decrease by 7Oxide thickness
Technology100
10
1
9nm
[ ]Virus
ProteinMolecule
DNA
decrease by 5
Thickness of a few atoms
Oxide thickness OxidMetal
Halvledare(semiconductor)
2001 2003 2005 2007 2010 201620130.1
1
Atom
Molecule
0.4nm
Source: ITRS 2002 Update (High performance logic technology)
Gate Oxide in an 150 nm technology
Polysilicon Gate
Gate Oxide
Silicon crystal
About 10 molecular layers of SiO2
Manufacturing: A lithographic process
Photographic glass plate (mask)
Each layer is projected to the silicon die
Dimensions close to light gwavelengths
Out of reach for the Optics!!!
4
Line widths smaller than the wavelength of light
Manufacturing: A lithographic process Optical Proximity Correction (OPC)
Predistortion of the mask layout is needed when scaling down the technology
OPC Corrections With OPCNo OPC OPC Corrections
Original Layout
Needed for 0.1 micron and less
Manufacturing: A lithographic process
Painting a 1 cm line with a 3 cm brush…
Courtesy : IBM
Power Consumption
Two major types
Dynamic power consumption- Two types
Static power consumptionStatic power consumption- Traditionally two major types- Four in submicron technologies
5
What Happens with the Power Consumption?
VDD
Previous focus: Dynamic charging/discharging of the
Chargeg g g g
load
Power consumption:
P = CL VDD2 f
Discharge 80-90% from the load and 10-20% from other sources
Current Spikes (Short Circuit)
Current peak when both N- and PMOS are open
VDD-VT
VT
N openP open
Ipeak
Dynamic Power Consumption
90% capacitive switching and 10% h t i it 5
[V]10% short circuit power
Short circuit power will decrease in submicron technologies when VDD gets closer to VT (Close to Zero when V =2V )
5
VT
VDD
Distancebetween VDDand VT willdecrease
1
2
3
4
when VDD=2VT)
Technology [μm]
1.4 0.350.60.81.0 0.180.25
Lower threshold voltage VT to increase the “gate overdrive”
That is to keep a reasonable propagation delay
Why do the Static Power Increase?
That is, to keep a reasonable propagation delay
VDD
0.93Vage
(V)
0.6
0.8
1
1.2
0.75V
VT
Gate Overdrive (VDD – VT)
0.93VV
olta
0
0.2
0.4
2005 2006 2007 2008 2009 2010 2011
0.75V
2012
Source: ITRS
6
Scaling & Static Power Consumption
VDD-VT trade-off
New Technologies require reduced VDD
V DD V T L I off
[V] [V] [um] [pA]3.3 0.58 0.35 12.5 0.47 0.25 10
Require lower VT
- (or slow devices)
High Leakage
Source: K. Roy
1.8 0.43 0.15 1001.6 0.4 0.10 1000
Dynamic vs. Static Power
Static power is a large contributor to the power todayEstimated to be about equal in today’s technologies
aliz
ed p
ower 1
0.01
100
65 nm
Dynamic power
Mainly subthreshold
Nor
ma
1990 20200.0000001
0.0001
20102000
Static powerYear
Source: ITRS
current in 65 nm
Reverse-biased, drain and source to substrate
junction band-to-band-tunneling (BTBT)
Most Important Leakage Currents
Gate oxide tunneling
Gate oxide tunneling
Subthreshold current
Source K. Roy, IEEE Micro, March – April 2006
Junction BTBTJunction BTBT
Sub Threshold
Static Power in an NMOS Device
Subthreshold dominates the power todayGate leakage will be the major source
1 uA
1 nA
Leakage
Subthreshold
Gate Leakage
6 orders of magnitude!
Source K. Roy, IEEE Micro, March – April 2006
1 pA
Junction BTBT
25 nm90 nm 50 nm
g
7
Static Power in an NMOS Device
Leakage increase with temperatureSubthreshold dominates at high temperatures
Note: Linear scale
15 nALeakage (A/um2)
Subthreshold
5 nA
10 nA
Total
Source K. Roy, IEEE Micro, March – April 2006
Junction BTBT
Gate Leakage
400300 350
5 nA
0
Temperature
Junction BTBTM j i f t t h l i (25 )
Leakage Currents
Junction BTBT
Gate oxide tunneling
Junction BTBT
Sub Threshold
Major source in future technologies (25 nm)
Gate oxide tunnelingMajor source in future technologies (50 nm and
below)
Subthreshold current
Source K. Roy, IEEE Micro, March – April 2006
Major source today (90 and 65 nm)
and below at high operating temperatures
Why do the Static Power Increase?
Shrinking feature sizes,
Shrinking thin oxide
Drain
Gate
Source
Shrinking thin oxide
Lower voltage to avoid break-through
Increased propagation delay tp:
Thin oxide
2( - )L DD
pDD T
C Vtk V V
=
Why do the Static Power Increase?
Exponential increase of the static power!
GS T
T
V Vm v
ffI I e−×= ×
ln(ID)
10n
1u
100u
10mLow VTHigh Ioff
0offI I e= ×
1p
100p
0 1.0 2.0 2.50.5 1.5
VGS (V)
High VTLow Ioff
VT
8
Gate Oxide Tunneling
Gate to bulk current
High electrical field over the thin oxide (t ) will High electrical field over the thin oxide (tox) will cause tunneling through the gate
Will be a major obstacle in submicron technologies
Gate oxide tunneling
Junction BTBT
tunneling
Junction BTBT
Sub Threshold
Normalized Gate Oxide Tunneling
90 nm technology Experimental technology
Cox = 1Igate-leak = 1
Cox = 1.6Igate-leak < 0.01
Other Static Power Consumption
Gate-Induced Drain Leakage (GIDL)
Not very serious for the supply voltages
suggested by ITRSgg y
Drain-Induced Barrier Lowering (DIBL)
Result in an increase of the subthreshold current
Gate
Source DrainDIBL
GIDL
Static Power and Scaling
Junction BTBT will increase
Subthreshold current will increase
Gate oxide tunneling will increase
DIBL and GIBL give minor contributions
Gate oxide tunneling
Junction BTBT
tunneling
Junction BTBT
Sub Threshold
9
Threshold Variations Device Variability – a big Problem
Threshold voltage variations in 90 nm
Leakage change exponentially with the threshold
The problem increases with denser technologies
Hotspots
Advanced tools to reduce the hotspot temperature
Before After
Scaling & Soft Errors Rate (SER)
Cosmic Rays at ground level is about 15 times lower than in outer
Normalized Soft Error Rate
space
Noise margin decreases with lower VDD
Mainly a memory problem (both SRAM and DRAM)
Exponential growth with
decreasing VDD
Cosmic ray = high-energy particle from outer space
10
Some Quotations
Cosmic rays are almost impossible to stop. They'll go through 5 feet of concrete without any trouble … and cause a bit to flip (Lange IBM)
In 0.13-micron technology we're seeing some memory technology with error rates of 10,000 or 100,000 FITs per megabit. This brings the frequency of error in a single device down to weeks or months (Eric-Jones MoSys)
A system with 1 GByte of RAM can expect an error every y y p ytwo weeks; a hypothetical terabyte system would experience a soft error every few minutes (TezzaronSemiconductor)
FIT/Mbit = Failures In Time: Errors per billion hours of use
Full (ideal) Transistor Scaling
Original deviceVDt
Scaled device(New Technology)
VD/St /S
Drain
Gate
Source
tox
L
Channel length (L)Channel width (W)
IDDrain
Gate
Source
tox/S
L/S
Channel length (L/S)Channel width (W/S)
ID/S
Increased acceptor concentration for constant electrical field
Channel width (W)Thin oxide thickness (tox)
Drain current (ID)Voltage (VD, VT, VDD, etc.)
Doping (NA)
Channel width (W/S)Thin oxide thickness (tox/S)
Drain current (ID/S)Voltage (VD/S, VT/S, VDD/S, etc.)
Doping (SNA)
Scaling Factors: Area & Capacitance
oxox
ox
W L W L C W Ltε
∝ × ∝ × × = × ×Area Capacitance
2
2 2
1
/
1oxox
ox
S SW L
WL WL
S
S SC
St Sε
∝ × ⇒ =
∝ × = × ⇒ =
Area Scaling factor
Capacitance Scaling factor
tox
L
W oxε = Material constant
Scaling Factor: Delay
V
2 2
( )
( ) ( )L DDL OH OL
n GS n DD T pHLHT Lp
Q C V C V V
Q I t k V V t
C V
k V V t
= ×Δ = − =
= × = − × = ×−
CL
2( )L
n DpH
DDL
D T
C Vk V
tV−
=
11
Scaling Factor: Delay (tp)
oxWk CL
μ
μ
= =
=
Gain factor
Electron mobility
2
2 22
2
( ) ( )( )
ox DDL DD DDp
DD T DD Tox DD T
DD
C WL VC V L Vt Wk V V V VC V VL
VL
μμ
× ×∝ ∝ ∝
− −−
2
2
2
( )1
DD
pDD T
S SS
S
tV Vμ
∝ ⇒ =−
Scaled delay Scalning factor
Source: J. Rabaey, Digital Integrated Circuits
tox
L
W
22 L DD
L DDp
C VP C V ft
= ∝
Scaling Factor: Power Consumption
ox
tε =
=
Material constant
Delay
oxL ox
ox
C W LC WLtε
ε
= = tox
L
W
pt Delay
2
2
oxDD
oxL DD
p
WL VtP C V ft
ε
= ∝
Source: J. Rabaey, Digital Integrated Circuits
Delay (factor 1/S)
2
2
P
oxDD
oxL DD
p
WL VtC V ft
ε
= ∝
Scaling Factor: Power Consumption
2 2
2
p
ox DD
ox
p
VWLtt
SS S
S
ε
∝ ⇒Scaled power
2 1S
⇒ =Scaling factor
2 1S
⇒ =Power consumption Scaling factor
Scaling Factor: Power Consumption
2 1
S
S⇒ =Area Scaling factor
Power consumption 1 ⇒ =Power consumption
Scaling factorArea unit
12
Ideal Scaling: Limitation
Voltage scale less than other parameters
d h h f ld h h lLeads to higher E-field in the channel
Leads to saturation of the electron velocity
Electron velocity
e- e- e-
e-e-
Electron velocity cannot have an
unlimited increase
High E-field
Velocity Saturation
´ ( )2nk WI V V= N t t d( )2D GS TI V V
L= − Non-saturated
´ ( )2
nD GS T
k WI V VL
α= − Velocity Saturated 2α <
The drain current is reduced due to the velocity saturation
2 L Saturated
Velocity Saturation (0.25um technology)
α2.1Low VDD: Velocity Saturation can be neglected
1.7
1.8
1.9
2.0High VDD: α decreases
Saturation appear earlier in denser technologies
´k W α
2.01.0 3.01.5 2.51.5
1.6
VDS [V]
Source: M. R. Stan, IEEE Trans. on VLSI Systems, Apr 01.
( )2
nD GS T
k WI V VL
α= −
Velocity Saturation
VGS=5VShort Long
VGS=3V
VGS=4V
VGS=2VI D
Line
ar D
epen
denc
e
V
Id
V
Id
ShortDevice
LongDevice
1 2 3 4 5VDS [V]
VGS=1V VGS
(Saturated Region)
VGS
13
Delay
2
2
2
2
( )
1DD
DD T
S SS
VL
V V∝ ⇒ =
−Non-saturated gate delay Scaling factor
2
2
2
2
2
2 ( )
1DD
DD T
S
SS
L V
V V
L
∝ ⇒ =−
Fixed voltage gate delay Scaling factor
2
2 1 (or )(
DD
DD T
SS
L V
V V α∝ ⇒−
<Saturated gate delay Scaling factor1 )S
The current do not increase as ”expected” at high voltages
Power
2 2
2
2
1ox DD
ox
VWLtt
SS S
S
ε
∝ ⇒ =Non-saturated power consumption Scaling factor 2
2
2
22
2
pHL
oxDD
ox
pHL
oxDD
ox
t
WL Vt
t
WL Vt
SS
SS S
SS
S
ε
ε
∝ ⇒ =Fixed-voltage power consumption Scaling factor
Saturated power consumption ( 1)S⇒ <Scaling factor
The current do not increase as ”expected” at high voltages
ox∝Saturated power consumption (or 1)pHL
S
St ⇒ <Scaling factor
Transistor Scaling
Parameter Full Scaling Fixed Voltage
SaturatedScaling
gVoltage Scaling
Dimensions (W, L, and tox) 1/S 1/S 1/S
VDD and VT0 1/S 1 1
Delay 1/S 1/S2 1/S
Capacitance 1/S 1/S 1/S
ID 1/S S 1
Power consumption 1/S2 S 1
Power per area unit 1 S3 S2
We will compare to ITRS later
Voltage do not scale: leads to increased power consumption
Dynamic Power Consumption
Partly limited by velocity saturation
Dependent on technology type
2 L DDP C V f=
Dependent on technology type Technologies for high performance: Increased consumptionTechnologies for low power: Low voltage, less increase in power consumption
14
Power in new technologies?
Dynamic power have been dominating
Static power will increase drasticaly
How about interconnections?How about interconnections?
Metal LayersYear 2001 2003 2005 2007 2010 2016
Techology (nm) 150 107 80 65 45 22Metal Layers 7 8 9 9 10 10
Metal Layers - Not a 2D problem!!!
TransistorsTransistors
Tungsten Contacts
Delay vs Technology
Delay [ps]
30
35
40Interconnect Delay
0
5
10
15
20
25
Gate Delay
Source: SIA Roadmap
Technology [um]1989 1992 1995 1998 2001 2004 2007
00.65 0.5 0.35 0.25 0.18 0.13 0.1
15
Capacitive load will increase
Contacts
Plate Plate capacitors was dominating
Fringing capacitors will
Fringing Capacitors
will dominate in new technologies
Interconnections on a Silicon Die
0.08Connection Probability
Local Wires
Global Wires
0.06
0.04
Global Wires 0.02
1.00.2 0.80.60.4Wire Length/Chip Diagonal Length
do not scale with the technology
Comparison of Network-on-Chip and Busses Copper Wires
40 % reduction in resistance12 % performance improvement in a Power PCp p
Transistor
16
Delay vs. Technology
Interconnect dominates the load- Fringing capacitances added
3 dimensions- 3 dimensions- “Longer” global wires
Solutions?- Copper wires- Materials with low dielectric constantMaterials with low dielectric constant- Interconnect optimization methodology
Physical design must be considered in all design phases
High performance:
Total power per function
Trends for Maximum Power
P [W]300
Low power: Doubling
over 15 years
High performance:
Doubling over 15 years
Idag, 150W
2016,290W
300
100
200
158W
Today,
Source: ITRS 2002 Update
Standby: Constant over
15 years
2001 2003 2005 2007 2010 201620130
100
3W
What about Moore’s Law?
The number of transistors is doubled every 18th month(1965)
Gordon Moore
25
Moore’s lag: Total power?
100 W today
25 kW the year 2020
10
15
20
25
P (k
W)
25 kW per chip!!!
2008 2010 2012 2014 2016 2018 20200
5P
ÅrYear
17
Manufacturing Costs
Initial cost have the largest increaseSmaller sizes leads to an explosion of the
2Mask set cost [M$]
1
costs for a mask-set
2M$
0.80 0.070.100.130.150.180.250.350.60
Feature size
1
Source: eASICSource: eASIC
Manufacturing Costs - Masks
2500Cost ($1000)
1000
2000 45 nm
65 nm
90 nm
More Expensive in the beginning
Exponential cost increase
20081995 20020
Year
130 nm180 nm
250 nm
Source: Jan Rabaey
Manufacturing costs in new Technologies
More Expensive for lower volumes but cheaper when the volumes goes up
130 nm
t /
Die
($)
180 nm
Volume (Dies)
Cost
Cost per Function (CPF)
CPF reduction between 29-35% per year
Technology 1
cost
per
funct
ion
0.1
1
Technology cross over
Technology 1
Technology 2
Technology 3
Source: Rakesh Kumar
Rel
ativ
e
Years0.01
0 2 4 6 8 10 12
Technology cross-over
18
Costs – New Fab
Capital Cost (M$)3000
12"2.5 Billion $
2000
1000
6"
8"
$
Technology
00.82 0.5 0.25 0.15 0.130.8 0.07
5"
6"
What is volume?
Typical "business case" for an ASIC (130 nm):
Price of "off-the-shelf" IC - 50$ per ChipPrice of off the shelf IC 50$ per Chip
Manufacture cost - 10$ per Chip
Development costs - 20M$
50$ 10$Break-even 500000 Chips−=
Source: Peter Olanders, Ericsson
Break even 500000 Chips20M$
Break-even is higher for 90 nm, 65nm …
Increase from 50% to over 90% of the silicon area
Memories on Chip
20%40%60%80%
100%
% Area Memory
% Area ReusedLogic
0%20%
1999
2002
2005
2008
2011
2014
g% Area New Logic
source: Japanese system-LSI industry