65nm CMOS Process TechnologyPaul Kim
Senior Manager, Foundry ServicesFujitsu Microelectronics America, Inc.
2February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm New 300mm Fabs – Mie, Japan300mm Fab No.2
•Process•65nm/90nm CMOS Logic
•Structural Features•Seismic-vibration control construction•Clean room area: 24,000 sq. meters
•Production Capacity•10,000 wafers per month (FY07 projection)•Maximum capacity of 25,000 wafers per month
•Planned Start of Operation•April 2007
300mm Fab No.1
•Process•90nm/65nm CMOS Logic
•Structural Features•Seismic-control construction•Clean room area: 12,000 sq. meters
•Production Capacity•15,000 wafers per month (FY06)
•Start of Operation•April 2005
3February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm
1000
100
10
500
50
20
200
1998 2000 2002 2004 2006 2008 2010Year (Production Start)
Phys
ical
Gat
e Le
ngth
(nm
)
45nm45nm65nm65nm
90nm90nm130nm130nm180nm180nm
CS100A
CS200
CS100HP
CS80 / 80A
CS90A
CS200ACS90
CMOS Technology Roadmap
CS100/CS100A (90nm)L actual=40-80nmSiOC (k:2.9) low-kDual Damascene Cu
CS200/CS200A (65nm)L actual=30-50nmNCS (NanoNano--Clustering Clustering Silica)Silica)
4February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Proven Track Record of 90nmComplex Designs and ProductsProven Track Record of 90nmComplex Designs and Products
5February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm
High-performance Products PC CPU (Transmeta)Large-scale FPGA (Lattice) Others
Low-power ProductsMultimedia processorDigital AV productsOthers
0 5 10Tape Out Number
20-5050-100
100-200
200-250
250-350350-450
Chi
p Si
ze (m
m2)
High EndLow Power
Proven Track Record of 90nmComplex Designs and Products – continuedProven Track Record of 90nmComplex Designs and Products – continued
6February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm 65nm, CS200 / 200A Features65nm, CS200 / 200A Features
FeaturesUltra-high-speed performance (CS200)
LG = 30nm, on-current enhanceCompared to 90nm technology, CS200 offers:
1.3 times faster speed0.6 times lower power2 times higher density
3 variations of Vth on a chip (CS200A)(1.8V & 2.5V) or (1.8V & 3.3V) I/O combination available11-layer copper interconnects with robust, very low K ILD
7February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm CS200 / 200A Transistor Variations
CS200: Ultra High SpeedCS200A: Wide Speed Range + Low Power Consumption
Speed
Leak
age
curr
ent
Fast
Larg
e
High End Server
STD-Tr
LL-Tr
Server/Network
Digital Consumer
Cellular Phone
STD-Tr
HS-Tr
HVt-Tr
Mobile Computing
HS:High speedSTD:Standard LL:Low leakage
HS-Tr
CS200
CS200A
8February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm
PerformanceLa
rge
Sm
all
SlowFast
tpd × P65nmnode
90nmnode
45nmnode
Leading-edge Transistors
Propagation Delay
Leak
age
9February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm
1nm-thick Gate Oxide Surface Cleaning
Ultra-Thin Gate Insulator / Mobility Improvement
Electric Field [MV/cm]
Nor
mal
ized
gm
(∝m
obili
ty)
0.0
5.0E-4
1.0E-3
1.5E-3
2.0E-3
-0.5 1.5 3.5 5.5
After optimize
Before
40% increase
Si substrate
Nitrided-SiO2
Poly-Si
10February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Speed Performance ImprovementsSpeed Performance Improvements
65nm 90nmCS200 CS100 Delay
(ps/gate) (ps/gate) Improvement
Inverter 5.7 7.0 19%
2-input NAND 8.7 11.4 24%
2-input NAND + 200 grid interconnect load 23.1 30.8 25%
11February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm High-Performance Competitive Transistors
Ion vs Ioff Characteristics of nMOSFETs
Company 2)
A
Fujitsu
70nA/μm
10-9
10-8
10-7
10-6
0.7 0.8 0.9 1.0 1.1 1.2 1.3
Ioff
(A/u
m)
Ion (uA/um)
Vd=1.0V
Company 1)
B
Ref. 1, 2) 2004 Symposium
on VLSI Technology
12February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Advanced Cu and Low-k
180nm node 130nm node 90nm node
CS80/80A6-Cu layersILD FSG CS90A
7-Cu layersILD hybrid low-k
CS100/100A/15010-Cu layersILD full low-k
65nm node
Die
lect
ric c
onst
ant
Hig
hLo
w CS200/200A/25011-Cu layersILD hybrid Ultra-low K
ILD: Inter-layer Dielectric
Four Generations of Experience
13February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm FujitsuFujitsu’’s Lows Low--k Leads ITRSk Leads ITRS
CS90SiLKTM/SiO 2
CS100Full- SiOC
CS200NCS/ SiOC
CS300Full - NCS
K=2.7/4.1 K=2.9/2.9 K=2.25/2.9 K=2.25/2.25
kW
idth
[nm
]
0
500
400
300
200
100
2000 2005 2010 2015
3.0
2.5
2.0
1.5
1.0
Products Year
CMOS Technology NodeCMOS Technology Node
IntermediateIntermediateWire PitchWire Pitch
130nm130nm90nm90nm
65nm65nm45nm45nm
32nm32nm
k
<1.9
<2.4
<2.1
<2.7
14February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Low-k Advantages of 65nm
Ultra low-k impacts on speed and power dissipation
CS100A (90nm)with SiOC/SiOCRsh: 90mΩ/sq., C: 56fF/1000 grid
CS200A (65nm)with SiOC/SiOCRsh: 150mΩ/sq., C: 52fF/1000 grid
CS200A (65nm)with NCS/SiOCRsh: 150mΩ/sq., C: 40fF/1000 grid
15February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm 11-Layer Copper Interconnects
Cu 11-layer Stack-via Chain
16February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm The Fujitsu EcosystemThe Fujitsu Ecosystem
Packaging,Assembly
& Test
Packaging,Packaging,Assembly Assembly
& Test& TestProcess
Technology
Process Process TechnologyTechnology
Library Development
Library Library DevelopmentDevelopment
IP Development
& Support
IP IP DevelopmentDevelopment
& Support& Support
Application& Software
Support
ApplicationApplication& Software& Software
SupportSupport
DesignMethodology
DesignDesignMethodologyMethodology
Design Services
Design Design ServicesServices
EDA Vendors
3rd PartyDesign Houses
3rd Party IP Vendors
3rd PartyLibrary Vendors
3rd Party Test
Houses
17February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Fujitsu Technology AccessFujitsu Technology Access
ASIC Flow
Customer Fujitsu
COT Flow
Customer Fujitsu
CustomFlow
Customer Fujitsu
Clock Tree SynthesisClock Tree Synthesis
RTL DesignRTL Design
Physical SynthesisPhysical Synthesis
Logical SynthesisLogical Synthesis
DFT InsertionDFT Insertion
Formal VerificationFormal Verification
FloorplanningFloorplanning
RoutingRouting
Test ValidationTest Validation
Physical VerificationPhysical Verification
STA / ECOSTA / ECO
Timing & SI VerificationTiming & SI Verification
Flexible collaboration models provide easy access to Fujitsu’s leading-edge process for the development of highly complex silicon products
18February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Design Flow & MethodologyDesign Flow & Methodology
Reference design flow - Fujitsu’s leading-edge design methodology focuses on timing, signal and power integrity closure Support for both Cadence SOCEncounterTM and Synopsys GalaxyTM
platforms In-house CAD software development augments leading third-party EDA solutionsEnsures silicon correlation and a fast path to silicon success by combining Fujitsu’s strengths in process, CAD tool and methodology development with design experience and expertiseProduction proven flows used on 100+ multi-million-gate designs at 180, 130 and 90nmConstantly updated and improved to address all issues at each process node
19February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Fujitsu Design ServicesFujitsu Design Services
Library and tool supportMethodology development and supportHigh-speed I/O design and expertiseVertical expertise and IP coresRTL designSynthesis and physical synthesisDesign partitioning and floorplanningStatic timing analysis Test insertion and ATPG generationPlace and routeTiming and SI closureFormal verificationPhysical verificationTest and product engineering
20February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm
Global PresenceLocal design centers around the world provide designservices for all phases of the development process
Skilled engineering teams experienced in development of large complex designs at 130nm and below100+ multi-million gate designs taped out
Fujitsu Worldwide Design CentersFujitsu Worldwide Design Centers
21February 7, 2006 DesignCon 2006
Leading-edge Technology
Fujitsu 65nm Summary Summary Fujitsu Objective
Helping customers accelerate their innovation, differentiate their products and enhance their competitive advantage, therefore helping them succeed
Leading-edge technologiesStrength in process technologies
90nm, 65nm and beyondPartnerships and customer collaborations
Flexible customer engagements and close collaborationsEarly customer engagementsTailored support and services to meet customer needs
System-level LSI solutions ASIC and ASSP/SoC, including10GbE switch chip and WiMAX SoC
Full design and development environments and support