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25Gbps SerDes
IEEE HSSG Meeting, Orlando FL - March 13-15, 2007
Charlie Zhong, Cathy Liu and Freeman ZhongSystem Architecture, LSI Logic
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Outline
• Introduction• 25G SerDes Design Considerations
– Different signaling schemes – Equalization– Crosstalk cancellation – FEC– Analog/digital partition
• Simulation Results• Conclusions
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Introduction
Advantage: Higher density
25Gbps SerDes
4X25Gbps
In 100Gbps Ethernet backplane, replace XFI with:
OIF CEI-25G is work in progress
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Outline
• Introduction• 25G SerDes Design Considerations
– Different signaling schemes – Equalization– Crosstalk cancellation – FEC– Analog/digital partition
• Simulation Results• Conclusions
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Signaling/modulation Choices
• NRZ is the choice of 10G BASE-KR and OIF CEI-11G.– Large installed base– People want to use NRZ in 25G as long as it is
feasible• PAM4• Constant envelope modulations: QPSK,
DQPSK,FSK…• OFDM• Partial-response signals: Duo Binary, PR4
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The Benefit of Higher-order Modulation
Lower insertion loss at reduced symbol rate
155½ symbol rate gain (dB)
2512.5Data rate (Gbps)
The difference is largerat higher data rates.
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Frequency Response: Force10 channel #6
channel
OIF 25G channel model
IEEE802.3ap channel model
3.125G
6.25G
12.5G
NRZ v.s. PAM4/QPSK
Note: the OIF 25G mask is updated based on the Q107 meeting
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The Drawback of Amplitude Modulation
1
-3
3
-1
1
-1/31/3
-1
PAM4
Max voltage swing limit
Reduced signal spacing
The 3x reduction in minimum distance results in9.5 dB SNR loss.
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Comparison between Modulation Schemes
12.5GS/s circuitDifficult to implement in DC
N12.5GQPSK
12.5GS/s ADCY12.5GPAM4
25GS/s ADCN25GNRZ
Implementation9.5dB lossSymbol RateModulation
• Analog implementation of QPSK requires a carrier frequency much higher than the data rate in order to maintain the orthogonality.• OFDM/QPSK implemented in the digital domain can maintain the othogonality without using a carrier frequency.
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Partial-Response Signals
• Ideal NRZ equalization target is flat spectrum.
– Requires a lot of high frequency boost.
• DB’s 1+D equalization target has a null at the Nyquist frequency.
– Better match to the channel at high frequencies and consequently requires less high frequency boost.
• PR4 has nulls at both DC and Nyquist.
– Null at DC may match DC-null in AC coupled systems, but PR-4’s DC null is much deeper.
– Results in throwing away the signal in the low frequency range where the SNR is strongest.
2 4 6 8 10 12
• Change of equalization target byrelaxing the zero-ISI condition• ML sequence detection is needed for optimal detection
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Equalization
• Traditional DFE is not enough.• Super DFE employs both front-end and back-end signal processing
to handle ISI in a more intelligent way.• Super DFE can have performance similar to that of a 40-tap DFE,
but with much fewer taps.
DFEDFE
++FIRFIRChannelChannel
Pre-ProcessingPre-Processing
Timing Recovery
Timing Recovery
Post-Processing
Post-Processing
Transmitter
Receiver
-+
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Crosstalk Cancellation
TX
RX
Delay alignment
Fine xtlkemulator
Coarse xtlkemulator
++-
+++ +
-
NEXTTX
RX
Delay alignment
Fine xtlkemulator
Coarse xtlkemulator
++-
+++ +
-
FEXT
• Emulate NEXT or FEXT at the receiver• Cancel both NEXT and FEXT• Do-able for 4-lane Ethernet SerDes
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Error Control
• Error propagation is more severe at 25G, so burst correcting code is a must.– (2112,2080) shortened code was adopted by IEEE
802.3ap.– (1584,1560) Fire code is used by OIF CEI.
• Implementation considerations– Parallel decoder– Small number of parity bits– (2112,2080) code has only 32 bits OH and requires
circuits running at only 769.2MHz if used in 25G.
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Analog/Digital Partition
• Traditional SerDes is mainly an analog design.• Some building blocks (DFE, CDR) can be moved to the digital
domain for process portability and design scalability.– Digital DFE: 20-tap DFE is do-able
• More digital signal processing can be introduced to handle the challenging 25G channels.
– OFDM/QPSK– Soft decision Viterbi decoder
• Low power GS/s ADC is the key: 4-6 bits ADC with 100mW power consumption is feasible.
ADCAnalog Circuits Digital circuits
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Outline
• Introduction• 25G SerDes Design Considerations• Simulation Results
– Model description– Channel frequency responses– Impact of crosstalk cancellation – Comparison between different signaling schemes – Effect of smarter equalization– Performance with better channel materials– Reduced data rate
• Conclusions
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Simulation - Analytic Model
• Analytic model is used to get slicer SNR at optimal sampling point.– Includes
• Intersymbol Interference (channel and package) • Random Jitter • Electronics (White) Noise• Crosstalk (NEXT and FEXT)• Duty Cycle Distortion
– Does Not Include• Receiver Sensitivity• Other Sources of DJ
Reference: J.Caroselli and C. Liu, “An Analytic System Model for High Speed Interconnects and its Application to the Specification of Signaling and Equalization Architectures for 10Gbps Backplane Communication”, DesignCon 06.
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Required SNR
2
2min
σdSNR =
⎟⎟⎠
⎞⎜⎜⎝
⎛≈
2221Pr SNRerfcerr
Approximately 24dB is required for an error rate of 10-15 and 23 dB for 10-12.
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Simulation Overview
• Different Signaling and Equalization architectures are compared.
• The number of taps in the feed forward and feedback equalizers are varied.
• All tap values are ideal.• The effect of one (worst case)
near-end crosstalk aggressor is considered.
• A simple RC model with pole at 0.75*baud rate is used for the transmitter.
• IEEE802.3ap capacitor-like package model included on both transmitter and receiver.
See notedCross Talk
AddedTX/RX Package
1ps sigmaRandom Jitter
40dBElectronic noise
25 Gb/sData rate
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Force10 Network Channels
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mag
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ch1: 4 3 4
ch2: 7 3 7
ch3: 10 3 10
ch6: 4 10 4
ch7: 7 10 7
OIF 25G channel model
IEEE802.3ap channel model
3.125G
6.25G
12.5G
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Intel Channels
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B1
B3
B8
B12
B20
OIF 25G channel model
IEEE802.3ap channel model
3.125G
6.25G
12.5G
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NEXT
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Xtlk Frequency Response
NEXTOIF 25G channel modelIEEE802.3ap channel model3.125G6.25G12.5G
• Modest crosstalk• Magnitude above
signal mask at 12.5G
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The Impact of Crosstalk Cancellation
>>100>>100>>1007
100>>100>>1003
4260851
PAM4DBNRZForce10 Channels
4772677
2129283
2039371
PAM4DBNRZForce10 Channels
With modest crosstalk
If crosstalk is cancelled
• All with 3-tap TX FIR.• Number of DFE taps required to achieve BER of 10-15
Note: DB is better than NRZ with crosstalk, but when crosstalk is perfectly cancelled, the advantage of DB(easier equalizer target and less boost) is gone
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Comparison between Signaling Formats
• All with 3-tap FIR and cross talk cancellation.• Number of DFE taps required to achieve BER of 10-15 :
47382130201934421917
PAM4
84141Intel B374039Intel B874034Intel B1279080Intel B2053937Force10 154540Force10 242928Force10 344848Force10 657267Force10 7
82829Intel B1QPSKDBNRZChannels
PAM4 has better performance than NRZ.
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Results with Super DFE
23.1821.58Force10 726.4823.69Force10 627.4223.36Force10 324.1922.75Force10 226.3923.41Force10 124.7219.67Intel B2024.6421.45Intel B1224.3621.68 Intel B824.7321.01Intel B324.3422.48 Intel B1
Super DFEDFEChannels
6-tap FIR and 20-tap DFE, NRZ signaling, crosstalk cancellation
Only 20-tap DFE is needed for NRZ.(PAM4 needs slightly fewer taps: 15-tap for B8, 20-tap for ch2 )
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Xilinx Channels
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F20
F40
F
E
ER
D
OIF 25G channel model
IEEE802.3ap channel model
3.125G
6.25G
12.5G
Backplane material: Rogers Hybrid
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F20 NEXT
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Xtlk Frequency Response
channelOIF 25G channel modelIEEE802.3ap channel model3.125G6.25G12.5G
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25.9119.74F (34”)
28.7822.92ER (27”)
29.0129.01F20 (20”)
SNR: super DFE (dB)
SNR: DFE (dB)Xilinx Channels
NRZ signaling, 8-tap DFECrosstalk cancellation
Backplane material: Rogers Hybrid
40%15% higher cost70-80% higher costRogers v.s. FR4
# of LanesOverall systemRaw materialsChannels
Does it make sense to use better materials for 25G?
System Tradeoff
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Reduced Data Rate
At 22Gbps, 6-tap FIR and super DFE, NRZ signaling, crosstalk cancellation
13Intel B2010Intel B812Intel B3
Super DFEChannels
Number of taps needed to have a BER of 10-15:
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Summary of Simulation Results
• Crosstalk cancellation is essential.• Higher order modulation provides better
performance.• Intelligent equalization technique can
support NRZ with a DFE of only 20 taps.• To use a DFE with less than 10 taps
– Better channel materials– QPSK– 22Gbps or BER of 10-12
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Conclusions
• The support of 25G SerDes over backplanes at higher speed demonstrates system feasibility for 100G based systems.
• A combination of signaling formats, equalization scheme, crosstalk cancellation, FEC and analog/digital partition can make 25G SerDes feasible.