Download - 2009-08-25-AVNET Institute SAM3 Session
AT91SAM3 Cortex-M3 MCUs
Atmel's New Cortex-M3 based Product Introduction: the SAM3U
AT91SAM3 Cortex-M3 MCUs
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Outline
1. Cortex M3 introduction and specific SAM3U implementation
2. SAM3U in depth technical overview
AT91SAM3 Cortex-M3 MCUs
1. Cortex-M3 Introduction & Specific SAM3U Implementation
AT91SAM3 Cortex-M3 MCUs
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ARM Cortex Family
Architecture version v7 is divided into three profiles: A profile, designed for high-performance application
platforms R profile, designed for high-end embedded systems in
which real-time performance is needed M profile, designed for deeply embedded microcontroller-
type systems
Cortex-M3 is the first ARM processor based on the ARMv7-M architecture Designed to achieve high system performance in power
and cost-sensitive embedded applications such as microcontrollers
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Cortex-M3 Processor Overview
Hierarchical processor integrating core and advanced system peripherals
Cortex-M3 core Harvard architecture 3-stage pipeline w. branch speculation Thumb & Thumb®-2 decoder ALU (Arithmetic and Logical Unit)
with H/W divide and single cycle multiply
Cortex-M3 processor NVIC: Configurable interrupt controller Bus matrix Advanced debug components Optional MPU & ETM
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Cortex-M3 Benefits (1/2)
Harvard architecture Separate buses for instructions and data speeding application
execution
Thumb-2 Instruction Set Architecture Blend of 16 and 32-bit instructions that delivers significant
benefits in terms of ease of use, code size and performance
3-stage pipeline + branch speculation When a branch instruction is encountered, the decode stage also
includes a speculative instruction fetch
000
00 1111 1
1
01 01
11
11
1
10
0 000
0
0
0 11 1
1
01
1
00 0
00
0
0 00
00 1
0 11
11
1
CORE
FLASHRAM
DMA
PERIPH
PERIPH
I-Code
1
11
0
10 0
0
CM3
FLASHRAM
DMA
PERIPH
PERIPH
10
1
1 0
1
D-C
od
e0
0
00
1
0
110 1
1
0
Syste
m
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Cortex-M3 Benefits (2/2)
Complete hardware support for interrupts for low latency interrupt handling
Interrupt Service Routines (ISRs) are purely written in C
Advanced ALU with support for hardware divide and single cycle multiply
Integrated atomic bit manipulation for improved data storage
Reduced pin debug & Trace interfaces
Embedded sleep control and power-down modes
Optional MPU & ETM
1.25 DMIPS/MHz
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Thumb-2 Instruction Set
Single powerfull instruction set backward compatible with 16-bit Thumb instruction set Not backward compatible with 32-bit ARM instruction set
Automatic optimization for both performance and code density, without the need for complex interworking
New instructions that make it easier to write compact code
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Nested Vectored Interrupt Controller (NVIC)
Cortex-M3 processor integrates an advanced Nested Vectored Interrupt Controller (NVIC) Nested and Vectored interrupt feature
Up to 240 external interrupt sources: 30 interrupts for the SAM3U.
Programmable interrupt priority control: 16 priority levels for the SAM3U.
Reduced interrupt latency thanks to late arrival interrupt acceptance and tail-chain interrupt entry
Non Maskable Interrupt (NMI): not implemented for the SAM3U
System Tick (Sys Tick), which is 24-bit count-down timer suitable to drive a RTOS or other scheduled tasks
SAM3U Specific
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Memory Protection Unit (MPU)
Supports 8 regions (32bytes to all of the 4GB)
Protection rules are based on the type of transaction (read, write or execute) and privilege of code performing the access
MPU violation will cause the Memory Management Fault exception to take place
MPU usage scenarios: MPU can be set up by an operating system, allowing data used
by privileged code (kernel) to be protected from untrusted user programs
To make memory regions read-only, to prevent accidental erasing of data
To isolate memory regions between different tasks in a multitasking system
IMPLEMENTED
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Advanced Debug Features
Cortex-M3 implements debug technology Data Watchpoint and Trace unit for watchpoints, data tracing and system
profiling Flash Patch and Breakpoint (FPB) unit for breakpoints and code patches. Instrumentation Trace Macrocell (ITM) for printf style debugging support. Debug Access Port (DAP) for Serial Wire Debug Port (SW-DP) or Serial
Wire JTAG Debug Port (SWJ-DP) debug access. Optional Embedded Trace Macrocell (ETM) for instruction trace: not
implemented for the SAM3U
SAM3U Specific
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Debug and Trace
6 code breakpoints and 4 general-purpose watchpoints
Serial Wire Debug interface (2 pins) and JTAG Debug interface (5 pins) to access to all memory and registers in the system
Live access to the core allowing to read and write memory and set/clear breakpoints on a running application
SAM3U Specific
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Debug and Trace (cont.)
JTAG by default Dedicated JTAG sequence to switch to Serial Wire Debug
(SWD) Supported by SAM-ICE v6 and higher
Asynchronous Trace (ITM) available when selecting Serial Wire Viewer (SWV) Supported by SAM-ICE v6 (v6 max speed 500 kHz, v7 6 MHz) Enables data trace or profiling
Pins JTAG-DP SW-DP
TDI TDI -
TCK/SWCLK TCK SWCLK
TMS/SWDIO TMS SWDIO
TDO/TRACESWO TDO TRACESWO
SAM3U Specific
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Cortex-M3 r2p0
Improvements into several areas: Low power features
- Sleep extension interface
- and optional new Wake-up Interrupt Controller (not implemented for the SAM3U)
System features- Better flexibility in the implementation to reduce gate count
Debug functionalities- DWT data trace supports « read only » and « write only »
option
Optimizations- Internal data path optimizations to allow Cortex-M3 to be
faster and easier to implement
IMPLEMENTED
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SAM3U Cortex-M3 Implementation
Cortex-M3 r2p0WIC - NoClock Gating - YesMPU - YesNVIC
No NMI, 30 interrupts and 16 priority levels
Debug Level 3 (Full option) Halt, 6 breakpoints, 4 Watchpoints, DWT counters, DAP,
Flash patch and DWT data match
Trace Level 1 (Standard option) DWT watchpoint, DWT metrics, DWT trace and ITM. No
ETM
AT91SAM3 Cortex-M3 MCUs
2. SAM3U Technical Overview
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Backup Unit
User Peripherals
System Peripherals
Cortex-M3
APB
SAM3U4E 144 pins
Peripheral Bridge
5-layer AHB Matrix
PWMx4
TWI16-bitTimer
x3
I/Ox96
RC OSC12/8/4MHz
WDT
UART
PMC
RSTC
12-bitADCx8
Flash128kB
ROM
FFPI
SAM-BA Boot
USART
USART
PDC
PDC
PDC
PDC
PIO A/B/C
SAM3U4E
Microcontrollers
Package
Key Features
QFP 144
BGA144
Peripheral DMAController: 11 channels
PCK-MCK 96MHz
JTAG ICE & SWD
JTAG Boundary Scan
Single Supply1.62 to 3.6V
4-chDMA
BODRTT
PORRC OSC32kHz
XTAL32kHz
PDCSupplyContr
TIC NVIC
ITM
SSCSPI
Peripheral Bridge
RTC
UniqueID
HSMCI
8-bit
Flash128kB
SRAM
16KB
SRAM
32KB
10-bitADCx8
PDC
US
B D
ev
ice
Hig
h S
pe
ed
DMA
UserInt.
FIFO
EBI
SMC(8/16-bit)
NANDNOR
PSRAM
ECC
16-bit
TWI
USART
USART
PDC
PDC
MPU
8 x GPBREG
3-20MHzOSC
PLLUTMI
PLL
PDC
4k SRAM
PDC
IAP
LDO
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Backup Unit
User Peripherals
System Peripherals
Cortex-M3
APB
SAM3U4C 100 pins
Peripheral Bridge
5-layer AHB Matrix
PWMx4
TWI16-bitTimer
x3
I/Ox57
RC OSC12/8/4MHz
WDT
UART
PMC
RSTC
12-bitADCx4
Flash128kB
USART
USART
PDC
PDC
PDC
PDC
PIO A/B/C
SAM3U4C
Microcontrollers
Package
Key Features
QFP 100
BGA100
Peripheral DMAController: 11 channels
PCK-MCK 96MHz
JTAG ICE & SWD
JTAG Boundary Scan
Single Supply1.62 to 3.6V
4-chDMA
BODRTT
PORRC OSC32kHz
XTAL32kHz
PDCSupplyContr
TIC NVIC
ITM
SSCSPI
Peripheral Bridge
RTC
UniqueID
HSMCI
4-bit
Flash128kB
SRAM
16KB
SRAM
32KB
10-bitADCx4
PDC
US
B D
ev
ice
Hig
h S
pe
ed
DMA
UserInt.
FIFO
EBI
SMC(8-bit)
NAND
ECC
8-bit
USARTPDC
MPU
8 x GPBREG
PLLUTMI
PLL
4k SRAM
PDC
3-20MHzOSC
ROM
FFPI
SAM-BA Boot
IAP
LDO
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SAM3U Series FeaturesFeatures SAM3U 144 pins SAM3U 100 pins
Max Frequency 96MHz 96MHzVoltage 1.62-3.6V 1.62-3.6V
Flash (KB) 256 / 128 / 64 256 / 128 / 64RAM (KB) 52 / 36 / 20 52 / 36 / 20
Ext. Bus Interface8 or 16-bit, 24-bit address
4 Chip select
8-bit, 8-bit address
2 Chip selectUSB 2.0 High Speed Device High Speed DeviceTimers 3 3PWM 4 4UART 1 1
USART 4 3SPI 1 1MCI 1 (8 bits) 1 (4 bits)TWI 2 1
FWUP/SHDN pins Yes No
SSC / I2S 1 1
ADC8 Ch. 12-bits
8 Ch. 10-bits
4 Ch. 12-bits
4 Ch. 10-bitsTotal GPIO’s 96 57
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SAM3U Performances
Two bridges but same clock: One bridge for slow speed peripherals with PDC support:
USART, UART, PWM, TWI, 10-bit ADC and 12-bit ADC One bridge for high speed peripherals with DMA support: SSC,
SPI and HSMCI (High Speed MCI)
2 SRAM blocks to get the highest bandwidth (one for DMA, one for Cortex-M3 for example) Seen as contiguous by the core
4-channel DMA + USB High Speed dedicated DMA + PDC
Matrix for parallel access path 5-layer Bus Matrix 10 slaves
AT91SAM3 Cortex-M3 MCUs
Embedded Memories
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Embedded Flash
Flash size: SAM3U4E/SAM3U4C: 256KBytes (dual plane, 2x128KBytes
contiguous) SAM3U2E/SAM3U2C: 128KBytes (single plane) SAM3U1E/SAM3U1C: 64KBytes (single plane)
128-bit or 64-bit Flash Access (programmable) Single cycle random Flash access up to 24MHz Zero wait state Flash for sequential accesses up to 96MHz
Page Programming time 4.6ms max (auto-erase included)
Unique-ID 128-bit factory programmed
Automatic sleep mode when Flash is accessed at low speed
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Dhrystone & Flash Frequency
Drysthone
results
Frequency
1.62V 1.80V
SAM3
(-64 bit access)
SAM3
(-128 bit access)
0 WS 24 MHz 27 MHz 1.227 DMIPS/MHz 1.227 DMIPS/MHz
1 WS 40 MHz 47 MHz 1.068 DMIPS/MHz 1.107 DMIPS/MHz
2 WS 72 MHz 84 MHz 0.915 DMIPS/MHz 0.988 DMIPS/MHz
3 WS 84 MHz 96 MHz 0.774 DMIPS/MHz 0.861 DMIPS/MHz
Trade-off Consumption/Power
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SAM3U4 Dual Bank Flash Boot Selection
Possibility to boot from a bank or another using GPNVM2
GPNVMBit[#] Function
0 Security bit
1 Boot mode Selection
2 Flash selection (Flash 0 or Flash 1) only applicable to 256KBytes Flash version
Application 1
FLASH BANK 00x80000
Application 2
FLASH BANK 10x100000
Application 1
BOOT MEMORY0x00
GPNVM2 cleared
Application 2
BOOT MEMORY0x00
GPNVM2 Set
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Embedded SRAM
SRAM size: SAM3U4E/SAM3U4C: : 32KBytes and 16KBytes
SAM3U2E/SAM3U2C: 16KBytes and 16KBytes
SAM3U1E/SAM3U1C: 8KBytes and 8KBytes
4KBytes embedded in the Nandflash controller can be used as generic SRAM if NandFlash controller not used
32 Bytes Backup registers
AT91SAM3 Cortex-M3 MCUs
Power Management, Reset and Clocks
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Power Management Flexibility
The SAM3U embeds: a Supply Controller (SUPC): controls supply voltages
a Power Management Controller (PMC): controls clocking of the system
Provides a wide range of low power modes allowing to choose the best trade-off between: Power Consumption
Wake-up time
Clock frequency
Wake-up sources
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Backup ModeRTC, RTT, Backup registers
Sleep Mode@500Hz
SAM3U Operating Modes
Active Mode
Wait ModeWake-up< 300µs
Wake-up < 10µs
VDDIO1 Power UpWide Range ofLow Power Modes
2.5µA typ (VDDBU)
8µA typ (VDDCORE)
17µA typ (VDDCORE)
Depends on clock
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Single Power Supply Strategy Example
1.8V to 3.6V
3.0V to 3.6VUTMI
ADC
1.8v
Main Voltage
Regulator
VDDUTMI
VDDANA
VDDI0
VDDIN
VDDOUT
VDDCORE
VDDPLL
I/Os 1.62V to 3.6V
VDDBU 1.62V to 3.6V
2.4V to 3.6V for ADC 12 bits3.0V to 3.6V for ADC 10 bits
1.8V
AT91SAM3 Cortex-M3 MCUs
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Reset pins
NRSTB: asynchronous reset (reacts as the POR) Resets everything (including backup region (RTC, RTT,
Backup registers))
Anti-glitch filter integrated
NRST: output by default Reset the Cortex-M3 and peripherals (Proc_nreset and
periph_nreset) but not the backup region (RTC,RTT, Backup registers)
AT91SAM3 Cortex-M3 MCUs
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Power On Reset
POR on VDDBU Always enabled
Monitoring voltage at start-up and power-down
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Brown Out Detector
Brown-out on VDDCORE Enabled by default
Can be disabled by software
Can generate a reset of the core
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Supply Monitor
Supply Monitor on VDDUTMI Disabled by default
Can be activated by software (sampled mode possible)
16 steps programmable
Can generate an interrupt or reset of the core
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Clock Sources Slow Clock – SLCK
On-chip 32KHz RC oscillator (20KHz-44KHz) Xtal 32KHz oscillator featuring bypass mode Selection is made through XTALSEL bit in SUPC_CR
Main Clock – MAINCK On-chip 4/8/12 MHz RC oscillator
- 8 and 12 MHz calibrated in production- +/- 1% at 25°C- +/-5% all conditions
Xtal 3-20 MHz oscillator featuring bypass mode
PLLA Clock – PLLACK Input frequency: 8-16 MHz Output frequency: 96 to 192 MHz Integrated RC filter PLL with fast startup target frequency in less than 200 µs
UPLL Clock – UPLLCK Input frequency: 12 MHz Output frequency: 480 MHz Integrated RC filter
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Power Management Controller
RC 4MHz
RC 32 kHz
4 MHz
Start-up
NewUseful for debug
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Clock Failure Detection
The clock failure detector allows to detect an eventual defect of the 3-20 MHz oscillator (for example if the crystal is disconnected) Switch automatically to internal 4/8/12 MHz RC oscillator if
the processor runs out of MCK or out one of the PLL using the Main oscillator
Send an interrupt
Can be programmed as Fault input for PWM
AT91SAM3 Cortex-M3 MCUs
Peripherals
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High Speed Multimedia Card Interface (HSMCI)
Compatibility with Multimedia Card Specification 4.3
Compatibility with SD Memory Card Specification 2.0
Compatibility with SDIO Specification 2.0
Can be connected to the 4-channel DMA
Dedicated MCI I/O for clock: 45 MHz @1.8V (65MHz @3.0V) with 30 pF
Master/slave/multi-master Quick SMBus Command PDC
Two Wire Interface (TWI)
AT91SAM3 Cortex-M3 MCUs
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USART New Feature
USART SPI mode Master and Slave mode Maximum frequency:
MCK/4 SPI mode 0,1, 2 and 3
supported
New
USART pinSPI Master
signal
SPI Slave
signalTXD MOSI MISORXD MISO MOSISCK SCK SCKRTS NSS -CTS - NSS
You can have until 5 SPI on the SAM3U(1 SPI and 4 USART) !!!
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UART and System Peripherals
UART + CHIPID = ex-DBGU without Debug (COMRX/TX)
UART needs to be clocked by PMC
UART, RTC, RTT, WDT, RSTC, SUPC, SMC, EEFC0/1
=> All these peripherals have now separated Interrupts (no more « OR » in software to handle)
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Serial Peripheral Interface (SPI)
SPI Speed improved Dedicated SPI I/O for clock: 45 MHz @1.8V (65MHz
@3.0V) with 30 pF
Timings improved…
… e.g. Maximum speed in Master Mode @3.3V with a 7ns slave delay = 1/(SPI0+ slave delay) = 48 MHz
Higher Speed
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USB Device High Speed (UDPHS)
UDPHS embeds its own DMA master controller => Large transfer can be done without CPU overhead
UDPHS embeds a 4KB DPR memory to store full packets payloads (different from a FIFO) Prevents from buffer underflow/overflow Allows to reduce system clock
7 endpoints Endpoint type is configurable (Ctl, ISO, Bulk, Int.) Number and size of banked DPR buffers is configurable Dedicated DMA interface for 6 endpoints
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PWM Controller New Features
PDC Support
Complementary Output (PWMxL, PWMxH)
Fault Inputs Providing an Asynchronous Protection of PWM Outputs
Events Lines Intended to Synchronize ADC Conversions
Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and PDC Transfer Requests
PMC Driven when Crystal Oscillator Clock Fails
Dead-Time generator
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Static Memory Controller (SMC)
Running at Master Clock 8-bit or 16-bit data bus width 4 independent chip select lines (16-Mbyte per Chip Select) 24-bit address lines Ready/Busy pin (Nand Flash Only) Off-Chip Memory Scrambling/Unscrambling
Interfacing Capabilities NOR Flash (AT49BV like) SLC NAND Flash LBA-NANDTM (MLC NAND + ECC + Bad Block Mgt) Static Asynchronous RAM Pseudo-static RAM (PSRAM- Asynchronous mode only – no page mode) External LCD controller External Ethernet Controller Any Memory Mapped Peripherals.
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SMC New Features
Biggest change is the Nand Flash Controller “EFC-Like” Nand Flash command management & automatic mgt.
of the NAND Flash operation with Dedicated 4k bytes SRAM (accessible by the CPU if not used)
Command/Address Register Based for read, write operations
Nand Flash Page Read Command Example
NandFlash
SAM3
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ADC 12-Bit Controller
1Msps Cyclic Pipeline ADC Good Trade-off between SAMPLING RATE and RESOLUTION
12-bit Resolution
1MHz Conversion Rate with 20MHz input clock
2.4V to 3.6V Wide Range Power Supply Operation
Selectable Single Ended or Differential Input Voltage
Programmable Gain x1 / x2 / x4 for Single-Ended or x0.5 / x1 / x2 in differential Mode
Standby Mode for Fast Wakeup Time Response
Power Down Capability
New
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DMA Features
Embeds 4 channels:– 3 channels with 8 bytes/FIFO for Channel Buffering– 1 channel with 32 bytes/FIFO for Channel Buffering
Linked List support with Status Write Back operation at End of Transfer Word, Half Word, Byte transfer support.
Handles high speed transfer of SPI, SSC and HSMCI (peripheral to memory, memory to peripheral)
Memory to memory transfer
Can be trigged by PWM and T/C which enables to generates waveform though the External Bus Interface
New
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I/Os & PIO Controller New Features
Rising / Falling Edge Detection
High or Low Level Detection
Provides PIO Lines Lock Status from other Peripherals (ex. PWM)
I/Os: 35 MHz @1.62V with 25 pF Dedicated SPI and MCI clocks (up to 65MHz @3.0V)
PIO Toggling Benchmark 21MHz with MCK @ 84MHz (MCK / 4) (assembly code)
~8 – 10MHz with MCK @ 84MHz (C code)
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SAM3U ODT
ODT = On-Die-Termination: embedded series resistor on all I/Os for impedance matching between the driver, the PCB trace impedance and the receiver
36 Ω Serial Resistor on all PIOs
Lower the resistive equivalent component is, higher quality factor is, higher over/under shounting effect due to the trace ringing is.
New
AT91SAM3 Cortex-M3 MCUs
SAM3U-EK Tools & Software
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AT91SAM3 Cortex-M3 MCUs
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SAM3U Toolchains
Major Tools supported IAR EWARM
Keil MDK
Code Sourcery GNU Tools supported
Flash Programming while Debugging IAR EWARM through SAM-ICE
Keil MDK through SAM-ICE
In-Situ Flash Programming SAM-BA through USB or Serial
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SAM3U Soft Pack Contents
Getting started Bit Banding Example Power Consumption
Example TWI Example
Interfacing with E², Audio DAC T° sensor
PWM/PDC Example RTC and RTT Examples Dhrystone ADC Audio Out Example Touch screen
Using the NAND Flash with the DMA Controller Example
Flash loader Example
USB HS Mass Storage
Multiple LUN, SDCard, NAND Flash and PSRAM
USB CDC Example
USB HID Example
USB Composite Examples
Using the HSMCI with the DMA Controller Example
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SAM3U-EK On-board Demo
USB Mass Storage Device- Click icon and connect PC via USB
Slide ShowPower ConsumptionAudio Parameters
LCD Backlight Temperature Date and Time
MP3 Player (later)Image Viewer (later)
AT91SAM3 Cortex-M3 MCUs
Thanks!