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Graduate Inst i tute o f Electronics Engineer ing, NTU
Digital IC Design FlowDigital IC Design Flow
Lecturer: Chihhao Chao
Advisor: Prof. An-Yeu Wu
Date: 2006.3.8
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OutlineOutline
vIntroduction
vIC Design Flow
vVerilog History
vHDL concept
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MooreMoores Law: Driving Technology Advancess Law: Driving Technology Advances
v Logic capacity doubles per IC at regular intervals (1965).
v Logic capacity doubles per IC every 18 months (1975).
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Process Technology EvolutionProcess Technology Evolution
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Chips SizesChips Sizes
Source: IBM and Dataquest
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Shrinking Product CyclesShrinking Product Cycles
v Shrinking product cycles
v Shrinking development turnaround times
v Need for productivity increase (remember the design gap!)
PCS: Personal Communication Services
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Design Productivity CrisisDesign Productivity Crisis
v Human factors may limit design more than technology.
v Keys to solve the productivity crisis:
v Design techniques: hierarchical design, SoC design (IP reuse,platform-based design), etc.
v CAD: algorithms & methodology
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Increasing Processing PowerIncreasing Processing Power
v Very high performance circuits in today"stechnologies.vGate delays: ~27ps for a 2-input Nand in 0.13um process
vOperating frequencies: up to 500MHz for SoC/Asic, over1GHz for custom designs
v The increase in speed/performance of circuitsallowed blocks to be reused without having to beredesigned and tuned for each application
v Enhanced Design Tools and TechniquesvAlthough not enough to close the design gap!, tools are
essential for the design of today"s high-performance chips
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IPIP--BasedBased SoCsSoCs
vAn Evolutionary Pathv Early days
IP/Cores not really designed for reuse (no standarddeliverables)
Multiple Interfaces, difficult to integrate
v IPs evolved: parameterization, deliverables, verification,synthesizable
vOn-Chip bus standards began to appear (e.g, IBM, ARM)
v Reusable IP + Common on-chip bus architectures
v 1998: max number of cores > 30 corescore content between 50% and 95%
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IP / CoresIP / Cores
v Soft IP/Corev Delivered as RTL verilog or VHDL source code with
synthesis script (i.e: clock generation logic)
v Customers are responsible for synthesis, timing closure, andall front-end processing
v
Firm IP/Corev Delivered as a netlist to be included in customer"s netlist(with don't touch attribute)
v Possibly with placement information
v Hard IP/Corev Due to their complexity, they are provided as a blackbox
(GL1/GDSII). Ex. Processors, analog cores, PLLsv Usually very tight timing constraints. Internal views not be
alterable or visible to the customer
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Changes in the Nature of IC DesignChanges in the Nature of IC Design
(IEEE Spectrum Nov,1996)
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Chasing the Design GapChasing the Design Gap
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Evolution of Silicon DesignEvolution of Silicon Design
Source: "Surv iving the SoC revolu tion A Guide to Platform-based Design,#
Henry Chang et al, Kluwer Academic Publishers, 1999
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MethodologyMethodology $$ Analysis and VerificationAnalysis and Verification
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IC Design and ImplementationIC Design and Implementation
IdeaDesign
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Design FlowDesign Flow
Design Specification
Design Partition
Design Entry-VerilogBehavioral Modeling
Simulation/FunctionalVerification
Design Integration &
Verification
Pre-SynthesisSign-Off
Synthesize and MapGate-Level Netlist
Post-SynthesisDesign Validation
Post-SynthesisTiming Verification
Test Generation &
Fault Simulation
Cell Placement, ScanChain & Clock Tree
Insertion, Cell Routing
Verify Physical &Electrical Design Rules
Extract Parasitics
Post-LayoutTiming Verification
Production-ReadyMasks
Production-ReadyMasks
Front End
Design Sign-Off
Back End
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System SpecificationSystem Specification
From CIC
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Algorithm MappingAlgorithm Mapping
RTL Level
System Level
From CIC
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Gate and Circuit Level DesignGate and Circuit Level Design
From CIC
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Physical DesignPhysical Design
From CIC
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Behavioral ModelBehavioral Model
Transistor Level
Gate Level
Register Transfer Level
Architecture
Algorithm
Systemconcept
Increasingbehavioralabstraction
Increasing
detailedrealization &complexity
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Design DomainDesign Domain
Behaviorallevel of
abstraction
Design Model Domain
Abstract PhysicalStructural
System
Algorithm
RTL
Gate
Switch
ArchitectureDesign
StructuralDesign
LogicDesign
LayoutDesign
Verification
Verification
Verification
ArchitectureSynthesis
RTL levelSynthesis
Logic levelSynthesis
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Introduction to HDLIntroduction to HDL
vHDL # Hardware Description Language
vWhy use an HDL ?
vHardware is becoming very difficult to designdirectly
vHDL is easier and cheaper to explore differentdesign options
vReduce time and cost
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VerilogVerilog HDLHDL
vBrief history of Verilog HDLv1985: Verilog language and related simulator
Verilog-XL were developed by GatewayAutomation
v
1989: Cadence Design System purchasedGateway Automation
v1990: Cadence released Verilog HDL to publicdomain
v1990: Open Verilog International (OVI) formed
v1995: IEEE standard 1364 adopted
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VerilogVerilog HDLHDL
vFeaturevHDL has high-level programming language
constructs and constructs to describe theconnectivity of your circuit.
v
Ability to mix different levels of abstraction freelyvOne language for all aspects of design, test, and
verification
vFunctionality as well as timing
vConcurrency perform
vSupport timing simulation
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Compared to VHDLCompared to VHDL
v Verilog and VHDL are comparable languagesv VHDL has a slightly wider scope
v System-level modeling
v Exposes even more discrete-event machinery
v VHDL is better-behaved
v Fewer sources of non-determinism(e.g., no shared variables ???)
v VHDL is harder to simulate quickly
v VHDL has fewer built-in facilities for hardwaremodeling
vVHDL is a much more verbose languagevMost examples dont fit on slides
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The Verilog LanguageThe Verilog Language
vOriginally a modeling languagefor a very efficient event-driven digital logic simulator
v Later pushed into use as a specification languagefor logic synthesis
v Now, one of the two most commonly-used languagesin digital hardware design (VHDL is the other)
v Combines structural and behavioral modeling styles
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Different Levels of AbstractionDifferent Levels of Abstraction
vArchitectural / AlgorithmicvA model that implements a design algorithm in high-level
language constructs
v Register Transfer Logic (RTL)vA model that describes the flow of data between registers
and how a design process these data.
vGatevA model that describe the logic gates and the
interconnections between them.
v SwitchvA model that describes the transistors and the
interconnections between them.
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VerilogVerilog HDL Behavior LanguageHDL Behavior Language
v Structural and procedural like the C programminglanguage
v Used to describe algorithm level and RTL levelVerilog models
v Key features
v Procedural constructs for conditional, if-else, case, andlooping operations.
vArithmetic, logical, bit-wise, and reduction operations forexpressions.
v Timing control.
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VerilogVerilog HDL Structural LanguageHDL Structural Language
vUsed to describe gate-level and switch-levelcircuits.
vKey features
vA complete set set of combinational primitives
vSupport primitive gate delay specificationvSupport primitive gate output strength
specification
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Language ConventionsLanguage Conventions
v Case-sensitivityvVerilog is case-sensitive.
vSome simulators are case-insensitive
vAdvice: - Dont use case-sensitive feature!
vKeywords are lower case
v Different names must be used for different itemswithin the same scope
v Identifier alphabet:vUpper and lower case alphabeticals: a~z A~Z
vDecimal digits: 0~9
vUnderscore:_
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Language Conventions (contLanguage Conventions (contd)d)
vMaximum of 1024 characters in identifierv First character not a digit
v Statement terminated by ;
v Free format within statement except for within quotes
v Comments:
vAll characters after // in a line are treated as acomment
vMulti-line comments begin with /* and end with */
v Compiler directives begin with // synopsys XXX
v Built-in system tasks or functions begin with $
v Strings enclosed in double quotes and must be on asingle line !Strings"
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Design EncapsulationDesign Encapsulation
v Encapsulate structural and functional details in a module
v Encapsulation makes the model available for instantiation inother modules
module my_design (ports_list);
... // Declarations of ports go here
... // Structural and functional details go here
endmodule
G d t I t i t t f El t i E i i NTU
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Port DeclarationPort Declaration
vThree port typesvInput port
input a;
vOutput portoutput b;
vBi-direction port
inout c;
net
net
netnet
input output
inout
reg or net reg or net
module
Port list
Port Declaration
module full_add (S, CO, A, B, CI) ;
output S, CO ;input A, B, CI ;
--- function description ---
endmodule
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Two Main Data TypesTwo Main Data Types
v Nets represent connections between thingsv Do not hold their value
v Take their value from a driver such as a gate orother module
v Cannot be assigned in an initialor always block
v Regs represent data storagev Behave exactly like memory in a computer
v Hold their value until explicitly assignedin an initialor always block
v Never connected to something
v Can be used to model latches, flip-flops, etc.,but do not correspond exactly
v Shared variables with all their attendant problems
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Primitive CellsPrimitive Cells
v Primitives are simple modulesv Verilog build-in primitive gate
v not, buf:
Variable outputs, single input (last port)
v and, or, buf, xor, nand, nor, xnor:
Single outputs (first port), variable inputs
module full_add (S, CO, A, B, CI) ;
--- port Declaration ---
wire net1, net2, net3;xor U0(S,A,B,CI);and U1(net1, A, B);
and U2(net2, B, CI);and U3(net3, CI, A);or U4(CO, net1, net2, net3);
endmodule
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How Are Simulators Used?How Are Simulators Used?
v Testbench generates stimulus and checks responsev Coupled to model of the system
v Pair is run simultaneously
Testbench System Model
Stimulus
ResponseResult
checker
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Example:Example: TestbenchTestbenchmodule t_full_add();
wire sum, c_out;reg a, b, cin; // Storage containers for stimulus waveformsfull_add M1 (sum, c_out, a, b, cin); //UUTinitial begin // Time Out#200 $finish; // Stopwatchendinitial begin // Stimulus patterns#10 a = 0; b = 0; cin = 0; // Statements execute in sequence#10 a = 0; b = 1; cin = 0;#10 a = 1; b = 0; cin = 0;#10 a = 1; b = 1; cin = 0;#10 a = 0; b = 0; cin = 1;#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;#10 a = 1; b = 1; cin = 1;endendmodule
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g g,
pp. 39
VerilogVerilog SimulatorSimulator
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EventEvent--Driven SimulationDriven Simulation
v A change in the value of a signal (variable) during simulation isreferred to as an event
v Spice-like analog simulation is impractical for VLSI circuits
v Event-driven simulators update logic values only when signalschange
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StylesStyles
vStructural - instantiation of primitives andmodules
vRTL/Dataflow - continuous assignments
vBehavioral - procedural assignments
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Structural ModelingStructural Modeling
vWhen Verilog was first developed (1984)most logic simulators operated on netlists
vNetlist: list of gates and how theyreconnected
vA natural representation of a digital logiccircuit
vNot the most convenient way to express testbenches
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Behavioral ModelingBehavioral Modeling
vA much easier way to write testbenchesvAlso good for more abstract models of circuits
vEasier to write
vSimulates faster
vMore flexiblevProvides sequencing
vVerilog succeeded in part because it allowed
both the model and the testbench to bedescribed together
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Style ExampleStyle Example -- StructuralStructural
module full_add (S, CO, A, B, CI) ;
output S, CO ;input A, B, CI ;
wire N1, N2, N3;
half_add HA1 (N1, N2, A, B),HA2 (S, N3, N1, CI);
or P1 (CO, N3, N2);
endmodule
module half_add (S, C, X, Y);
output S, C ;input X, Y ;
xor (S, X, Y) ;and (C, X, Y) ;
endmodule
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Style ExampleStyle Example $$ BehavioralBehavioral
module fa_bhv(S, CO, A, B, CI) ;
output S, CO ;input A, B, CI ;
reg S, CO; // required to hold! values between events.
always@(A or B or CI) //;begin
S
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How Verilog Is UsedHow Verilog Is Used
v Virtually every ASIC is designed using either Verilogor VHDL (a similar language)
v Behavioral modeling with some structural elements
v !Synthesis subset"v Can be translated using Synopsys Design Compiler or
others into a netlist
v Design written in Verilog
v Simulated to death to check functionality
v Synthesized (netlist generated)
v
Static timing analysis to check timing