Download - 1.introduction to hd ls
![Page 1: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/1.jpg)
INTRODUCTIINTRODUCTION ON TO TO
VLSI & VLSI & HDLSHDLS
Sreejeesh S.G
![Page 2: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/2.jpg)
Course Contents
![Page 3: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/3.jpg)
Course Contents What are HDLs ? Are they really required ?. VHDL Verilog Advantages/Disadvantages
![Page 4: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/4.jpg)
SSG, VLSI DESIGN GROUP ,NIELIT
4
VLSI Realization Process
Determine requirements
Write specifications
Design synthesis and Verification
FabricationManufacturing test
Chips to customer
Customer’s need
Test development
Design
Manufacture
![Page 5: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/5.jpg)
HHardware DDescription LLanguage
Sreejeesh VLSI DESIGN GROUP. NIELIT
HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.
HDLs are used to write executable specifications of some piece of hardware.
![Page 6: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/6.jpg)
HDLs - Motivation Increased productivity shorter development cycles, more
features, but........still shorter time-to-market, 10-20K gates/day/engineer
Flexible modeling capabilities. can represent designs of gates or
systems description can be very abstract or very structural
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 7: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/7.jpg)
Design reuse is enabled. packages, libraries, support reusable,
portable code Design changes are fast and easily
done convert a 8-bit register to 64-
bits........four key strokes, and its done! exploration of alternative architectures
can be done quicklySreejeesh VLSI DESIGN GROUP. NIELIT
![Page 8: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/8.jpg)
Use of various design methodologies. top-down, bottom-up, complexity hiding
(abstraction) Technology and vendor independence. same code can be targeted to CMOS, ECL,
GaAs same code for: TI, NEC, LSI, TMSC same code for: .5um, .35um, .25um, .18um
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 9: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/9.jpg)
Enables use of logic synthesis which allows a investigation of the area and timing space.
Using a standard language promotes clear communication of ideas and designs.
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 10: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/10.jpg)
DO WE REALLY NEED HDL’S ??
Before Emergence of HDL’s How was Designing Field ??
We where designing systems using Boolean equations…isn't ?
![Page 11: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/11.jpg)
SCHEMATIC REPRESENTATION
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 12: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/12.jpg)
DRAWBACKS OF TRADITIONAL DESIGNING METHODS
System will be specified as interconnected blocks and this is not how specification of system is given to you or created.
System spec is always given as behavior of a system.
Handling of large complex system is not feasible.
Analyzing thousands of Boolean equations is not possible.
We all know that over six thousand gates the schematic become incomprehensible.
We in modern world deal with millions of gates.Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 13: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/13.jpg)
So We go for HDL’s …
Sreejeesh VLSI DESIGN GROUP. NIELIT
What are these HDL’s ?? “Hardware Description Language”. What they do ?? Describe digital circuits.Describe digital circuits. HDLs allowed the designers to model the concurrency
of processes found in hardware elements.
HDLs such as Verilog HDL and VHDL became popular.
![Page 14: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/14.jpg)
COMPARISON B/W TRADITIONAL APPROACH AND HDL APPROACH.
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 15: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/15.jpg)
Design Flow
Modelsim VHDL
Place and Route
FPGAHardware
ModelSim
Design EntrySimulation
Xilinx ISELogic Synthesis
Logic Analyzer
![Page 16: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/16.jpg)
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 17: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/17.jpg)
ORIGIN OF VHDL•Initiated by US Government’s Dept of Defense US Government’s Dept of Defense VHSIC
Program in 1980.
•IBM, TI and Intermetrics started the development of VHDL in
1983
•VHDL Ver. 7.2 released in 1985.
•IEEE standard 1076-1987 in 1987.
•IEEE 1076-1993 - revision in 1993Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 18: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/18.jpg)
VVHDLHDL
VVery High Speed Integrated Circuit HHardware
DDescription LLanguage
VHDL is an industry standard HDL for the Description, Modeling and
Synthesis of digital circuits and systems.
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 19: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/19.jpg)
VVHDLHDL
It is the most popular HDL , worldwide.
System specification can be done structural or/and in behavioral levels.
Good VHDL simulation tools are available in market at reasonable price.
Synthesis with VHDL is available with all most all EDA vendors.
It is a universal modeling language, i.e. it can be used to model electromechanical
systems, hydraulics, chemical and other system. It is not restricted only to
electronics.
![Page 20: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/20.jpg)
BASICFEATURES OF VHDL CONCURRENCY. SUPPORTS SEQUENTIAL STATEMENTS. SUPPORTS FOR TEST & SIMULATION. STRONGLY TYPED LANGUAGE. SUPPORTS HIERARCHIES. SUPPORTS FOR VENDOR DEFINED
LIBRARIES. SUPPORTS MULTIVALUED LOGIC.
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 21: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/21.jpg)
CONCURRENCY
Sreejeesh VLSI DESIGN GROUP. NIELIT
VHDL is a concurrent language. HDL differs with Software languages with respect
to Concurrency only. VHDL executes statements at the same time in
parallel, as in Hardware.
![Page 22: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/22.jpg)
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 23: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/23.jpg)
DESIGN PROCESS OF A DIGITAL SYSTEM
Design process of a digital system has 4 phases - Requirement Analysis & Specification.- Design .- Implementation & Testing.- Manufacturing .
In 1st phase, Function, Performance and interface requirements are determined and specified.
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 24: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/24.jpg)
DESIGN PROCESS OF A DIGITAL SYSTEM..
In 2nd phase , system is partitioned into different levels of
decomposition such as
- System Design : System is decomposed several
subsystems and the communication protocol among them is also
defined.
- Architectural Design : Architectural style and performance of
each subsystem is determined.
![Page 25: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/25.jpg)
DESIGN PROCESS OF A DIGITAL SYSTEM…
RTL Design : Architecture is translated into an interconnection of RTL Modules.
- Logic design: RTL Modules are constructed using logic
gates.
In 3rd phase, subsystems are implemented and tested including partitioning,
placement and routing to produce a layout of circuit.
In final phase , process is to prototype , manufacture the design.
![Page 26: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/26.jpg)
![Page 27: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/27.jpg)
ADVANTAGES OF VHDLCan verify design functionality early in the design process and simulate a design written as a VHDL description.Logic Synthesis and optimization converts a VHDL description to a gate level implementation in a given technology.Reduces circuit design time and errors.VHDL descriptions provide technology independent documentation for a design and its functionality.
![Page 28: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/28.jpg)
ADVANTAGES OF VHDL..
Powerful constructs to write complex logic.It has multiples levels of design descriptions.It supports design libraries and the creation of reusable components.It provides for design hierarchies to create module design.
![Page 29: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/29.jpg)
ADVANTAGES OF VHDL….Device independent design
VHDL permits to create a design without first choosing the device for implementation
PortabilityVHDL is an IEEE standard.Libraries of VHDL models of components can be shared across platforms, tools organization and technical group
ASIC MigrationQuick time to market and low cost
![Page 30: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/30.jpg)
CAPABILITIESCAPABILITIESVHDL supports design hierarchies
A digital system can be modeled as a set of interconnected components
It supports flexible design methodologiesTop-down , Bottom-up or mixed.
VHDL is not technology specific.It can support various hardware technologies
It supports both synchronous and asynchronous timing models
NIELIT
![Page 31: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/31.jpg)
CAPABILITIES…CAPABILITIES…
Various modeling techniques such as FSM, algorithmic and Boolean equations can be modeled using VHDL.
Any large design can be modeled using VHDL
No limitation imposed by the size of a design
Test benches can be written in VHDL to test other models.
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 32: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/32.jpg)
CAPABILITIES…
Propagation delays, set-up and hold time timing constraints can be described in VHDL
Generics and attributes are useful in describing parameterized design
Models written in VHDL can be verified by Simulation
Behavioral models are capable of being synthesized to gate- level description
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 33: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/33.jpg)
Sreejeesh VLSI DESIGN GROUP. NIELIT
![Page 34: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/34.jpg)
DISADVANTAGESLess control of defining gate level implementation.The implementation created by synthesis tool is inefficient.The quality of synthesis varies from tool to tool.
![Page 35: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/35.jpg)
SUMMARYVHDL modeling can be used to model hardware at multiples levels of abstraction.VHDL is independent of technology and design methodologies and promotes portable descriptions, rapid prototyping and free exchange of models among organizations and individuals.
![Page 36: 1.introduction to hd ls](https://reader038.vdocuments.us/reader038/viewer/2022103105/58edb2721a28ab90318b4677/html5/thumbnails/36.jpg)
ANY QUESTIONS ??ANYBODY ??COMMENTS ??
Thanks.
Sreejeesh S.G