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J-K FF, Counters
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Menu
• Clocks and Master-Student Flip-Flops• J-K and other Flip-Flops• Truth table & excitation table• Adders (see [Lam: pg 130])• Counters
Look into my ...
https://youtu.be/Bg21M2zwG9Qhttps://youtu.be/3PycZtfns_U
Master Student
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Master-Student Flip-Flop
Complex Circuit
tc = time when signals changetw = digital systems do their
work here, others finish their work in this phase
Most digital systems expect their inputs to be stable very early in the tc phase of the clock. As drawn, it is possible for S and/or R to “change” while CLK = 1 (during tc).
Master-Student Latch/Flip-Flop
Q (active-high and -low) may change during time tceven though other hardware expect them to be stable!!
CLKtc
tw
SR
Q
Q
ECLK
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Master-Student Flip-Flop• Q: How do we solve this problem?• A: Use 2 latch’s, one master, one student. Signals do not change
during tc. (This is a digital-only solution; the 3rd option discussed earlier.)
• Q: Why?• A: Now {Q(H), Q(L)} will not change until tw. Hence, inputs to
other systems are stable during tc.
Master Student
SR Q
Q
E
S
R Q
Q
ECLKtc
tw
CLKtc
tw
Master-Student S-R Flip-Flop
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Master-Student JK FF
Gated S-R Latch Q(L)
Q(H)
S(H)
E(H)
Pre-Clear
Pre-Set
R(H)SR
Q
Q
E
LogicWorks
> With master-student FFs we have a completely digital solution to the “stable” input problem. No oscillation occurs!!!!
JK_from_M-S_SR*.cct
Master-Student J-K FF(Falling Edge Clock)
R QE
R QE
Master Student
Q QS SK
J
J-K FF withfalling edge-clock
JK
Q
QS
R
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J-K FF, Counters
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Flip-FlopsMaster-Student J-K FF(Rising Edge Clock) J-K FF with
rising edge-clock
JK
Q
QK QE
K QE
Master StudentQ QJ J
T-FF using JK D-FF using JK
TJK
Q
Q D JK
Q
Q
D-FF using SR
D SR
Q
Q
How about constructing a JK with a D?Hint: D = J /Q + /K Q
S
R
S
R
S
R
S
R
J-K FF withfalling edge-clock
JK
Q
QS
R
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D-FF using Two MUXs• Designed by Alex Kagioglu, a UF EEL 4712 student, 2008
10Sel
Y2-input MUX 0
1Sel
Y2-input MUX
Q(H)
D(H)CLK
CLK
d-ff_mux.bdf d-ff_mux.vwf
mux2to1.vwf
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J-K Flip-FlopNext State Truth Table for J-K FF
K-Map gives
Q+ = J /Q + /K Q
(Q+ = S + /R Q)
Abbreviated Next State Truth Table
for J-K FF
Excitation Table for J-K FF
Abbreviated Excitation Table for J-K FFJ\KQ 00 01 11 10
0 0 1 0 01 1 1 0 1
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Rising edge triggered JK-FF Timing Diagram
Lam: Figure 5.2
JK
Q
Q
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Rising edge triggered D-FF Timing Diagram
Lam: Figure 5.2
DQQ
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Two Common FF ICs74’74 Dual D-FFs(rising edge triggered)
74’73 Dual JK-FFs (falling edge triggered)
(in your lab kit)
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• Q1: Is addition sequential?Adder Circuits using Memory
> In this circuit a 1-bit FA with a D-FF can be used to add an arbitrary N-bit number (e.g., a 32 bit number). But a 32 bit adder without memory requires, for example, eight 74’283 4-bit parallel adders.
CLR
QD
SABCi Ci+1
Xi (H)Yi (H)
CLK
SUMi(H)
Ci+1 (H)
FAR
• A1: No. (At least not from what we previously learned.) It can be implemented with a combinational circuit.
• But we CAN make a sequential adder:
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Adder Circuits using Memory
CLR
QD
SABCi Ci+1
Xi (H)Yi (H)
CLK
SUMi(H)
Ci+1 (H)
FAR
Lam: Figure 5.5 (Ex 5.1)
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• Q2: How big can N be? What is the cost?• A2: As big as you want --- same (IC) cost.• Observations:
>We can often realize complex combinational logic with simple sequential logic
>We can realize impossible combinational functions with sequential logic (e.g., counting)
>The trade-off is parallel (combinational) vs. sequential circuits, and time vs. hardware complexity– Parallel circuits obtain a sum in 1 clock tick; serial circuits
require N clock ticks.
N-bit Adder (Using Memory and 1-bit FA)
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• Recall we mentioned in lecture #2 that “counting” requires memory. In the next few page we will design a 3-input (8 state or 23) counter.
• There are several steps in the design of sequential circuits:> Develop a state diagram> Make a next state truth table (NSTT)> If not D-FFs, pick FFs and get excitation info to NSTT> Add outputs to NSTT> Get equations for FFs inputs > Design circuits based on the equations
• A counter turns out to have very simple steps! We will show that some of the steps above are trivial
• Assumption: A clock pulse “P” is used to clock the counter> (example/analogy) A car counter used by the road department
Steps for Counter Design
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Counter Design: State DiagramDesign a counter that counts the following sequence:Q2Q1Q0 = 100, 010, 111, 110, 011, 000, 101, 001,100,...
100
001
101
000 011
010
111
110
PP
P
P
P
P
P
PStartNote the strange counting sequence:
4, 2, 7, 6, 3, 0, 5, 1, 4, 2, 7, …
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Counter Design: Truth Table
• 3-bit counter (with 23=8 states) needs 3 FF’s• From the desired counter sequence, for Q2+
(the next state for Q2) we obtain the sequence, 0 1 1 0 0 1 0 1, i.e., column Q2 of the counter sequence but delayed (starting in row 2) by 1 row> Q1+: 1 1 1 1 0 0 0 0> Q0+: 0 1 0 1 0 1 1 0> Put this in a next state truth table (NSTT)
• For each FF, we develop state equations > For D-FFs Qi+ = Di , i.e., what comes in goes out
immediately after the clock• Notice that the counting order truth table
(shown here) is preferred
P
100
001
101000 011
010111
110
P
P
P
P
P
P
PStart
Q2 Q1 Q0 Q2+ Q1+ Q0+0 0 0 1 0 10 0 1 1 0 00 1 0 1 1 10 1 1 0 0 01 0 0 0 1 01 0 1 0 0 11 1 0 0 1 11 1 1 1 1 0
Current Next
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Counter Design: FF Next State Equations
/Q2/Q0
Q2Q1Q0
Q2+ = /Q2/Q0 + /Q2/Q1 + Q2Q1Q0= D2
QQ2D
Q2+
CLR
/Q2/Q1
Using these sequences, we fill 3 K-maps, one for each of Q2+, Q1+, & Q0+.
Current NextQ2 Q1 Q0 Q2+ Q1+ Q0+0 0 0 1 0 10 0 1 1 0 00 1 0 1 1 10 1 1 0 0 01 0 0 0 1 01 0 1 0 0 11 1 0 0 1 11 1 1 1 1 0
D2 D1 D0
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Counter Design: FF Next State Equations
Q2/Q0
Q1/Q0
Q1+ = Q2/Q0 + Q1/Q0 + Q2Q1= D1
QQ1D
Q1+
CLR
Q2Q1
Using these sequences, we fill 3 K-maps, one for each of Q2+, Q1+, & Q0+.
Q2 Q1 Q0 Q2+ Q1+ Q0+0 0 0 1 0 10 0 1 1 0 00 1 0 1 1 10 1 1 0 0 01 0 0 0 1 01 0 1 0 0 11 1 0 0 1 11 1 1 1 1 0
Current NextD2 D1 D0
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Counter Design: FF Next State Equations
Q1/Q0
Q0+ = /Q2/Q0 + Q1/Q0 + Q2/Q1Q0= D0
QQ0D
Q0+
CLR
Q2/Q1Q0/Q2/Q0
Using these sequences, we fill 3 K-maps, one for each of Q2+, Q1+, & Q0+.
Q2 Q1 Q0 Q2+ Q1+ Q0+0 0 0 1 0 10 0 1 1 0 00 1 0 1 1 10 1 1 0 0 01 0 0 0 1 01 0 1 0 0 11 1 0 0 1 11 1 1 1 1 0
Current NextD2 D1 D0
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Counter Design: Realization (Designing the Circuit)
Q2+ = /Q2/Q0 + Q2Q1Q0 + /Q2/Q1= f2(Q2, Q1, Q0) = D2
Q1+ = Q2/Q0 + Q1/Q0 + Q2Q1= f0(Q2, Q1, Q0) = D1
Q0+ = /Q2/Q0 + Q1/Q0 + Q2/Q1Q0= f0(Q2, Q1, Q0) = D0
Q Q2D
Q Q1D
Q Q0D
Q2+
Q1+
Q0+
CLR
CLR
CLR
Comb2
Comb1
Comb0
Q2, Q1, Q0
Q2, Q1, Q0
Q2, Q1, Q0
CLKDone!
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Activation-Levels for State Bits• What if one (or more) of the state bits (Qi ) is
active-low?>As you may recall, when we first started discussing
circuits we feedback, I stated that with these types of circuits it is often easier to deal with voltages rather than with logic.
• Recommendations:>Design the next state circuits for counters (and other
state machines) with all active-high state-bits>Then design the output circuits using the appropriate
(specified) activation levels
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State Machine Design
Next State
Comb. Logic
Q’sFlip-Flops
Inputs
Clk
Output Comb. Logic
Q’s
Inputs
Outputs
• For Moore machines, there are no dashed line “Inputs”; Mealy machines have these inputs
• For counters, state bits (Q’s) are generally some of the outputs, but might be active-low or active-high
Q’sClk
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Another Counter Design: State Diagram
Design a counter that counts the following sequence:Q2Q1Q0 = 000, 001, 101, 100, 010, 110, 111, 011, 000,...
Observation: Simple! Each bubble (node) is a state.The only input is a pulse, P.
000
011
111
110 010
001
101
100
PP
P
P
P
P
P
PStart
Note the counting sequence:0, 1, 5, 4, 2, 6, 7, 3, 0, 1, 5, …
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Another Counter Design: Truth Table
• 3 bit counter (8 states or 23=8) 3 FF’s• From the desired counter sequence, for
Q2+ (the next state from Q2) we obtain the sequence, 0 1 1 0 1 1 0 0, i.e., column Q2of the counter sequence but delayed (starting in row 2) by 1 row.> Q1+: 0 0 0 1 1 1 1 0> Q0+: 1 1 0 0 0 1 1 0> Put this in a next state truth table (NSTT)
• For each FF, we develop state equations > For D-FFs Qi+ = Di , i.e., what comes in goes
out
Counting:0, 1, 5, 4, 2, 6, 7, 3, 0, 1, …
Q2 Q1 Q0 Q2+ Q1+ Q0+0 0 0 0 0 10 0 1 1 0 10 1 0 1 1 00 1 1 0 0 01 0 0 0 1 01 0 1 1 0 01 1 0 1 1 11 1 1 0 1 1
QQiD
Qi+
CLR
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Q2 Q1\Q0 0 100 0 001 1 011 1 110 1 0
Q2 Q1\Q0 0 100 1 101 0 011 1 110 0 0
Q2 Q1\Q0 0 100 0 101 1 011 1 010 0 1
Q1Q0 Q1Q0
Q2Q1
Q2Q0Q1Q0
Q1+ = Q2Q1+Q2Q0+Q1Q0= D1
Q2+ = Q1Q0+Q1Q0= Q1 Q0= D2
Q2Q1 Q2Q1
Q0+ = Q2Q1+Q2Q1= (Q2 Q1)= Q2 Q1= D0
Another Counter Design: Next State Equations
QQiD
Qi+
CLR
Using these sequences we fill 3 K-maps, one for each of Q2+, Q1+, & Q0+.
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Another Counter Design: Realization (Designing the Circuit)
• Choose FF’s to realize Qi+, i=2,1,0.• Choose D-FF because Qi+ = Di.
Simple!!!D2=Q2+, D1=Q1+, and D0=Q0+.
• What are the output equations? O2=Q2, O1=Q1, and O0=Q0Simple!
• You could get the outputs from Qi+, but the Qi’s are better with regard to a starting count
QQ2D
Q Q1D
Q Q0D
D2 = Q2+
D1 = Q1+
D0 = Q0+
CLR
CLR
CLRCLK
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J-K FF, Counters
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Another Counter Design: Realization (Designing the
Circuit)• Realize using D-FF, T-FF, SR-FF or JK-FFs
CombinationalNetwork
Observation: This circuit contains feedback! Since the flip-flops are edge triggered, after the signal propagates through the combinational network, they do not feedback around to change the states.
CLK
Q1Q2
Q2Q1 Q2/Q1 Q1/Q0
Q1Q0
GND
Reset
Q Q2D
Q Q1D
Q Q0D
Q2+
Q1+
Q0+
CLR
CLR
CLR
Vcc
counter2.cct
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Another Counter Design: Realization (Designing the
Circuit)• Realize using D-FF, T-FF, SR-FF or JK-FFs
CombinationalNetwork
Observation: This circuit contains feedback! Since the flip-flops are edge triggered, after the signal propagates through the combinational network, they do not feedback around to change the states.
CLK
Q1Q2
Q1Q2 Q1/Q3 Q2/Q3
Q2Q3
GND
Reset
Q Q1D
Q Q2D
Q Q3D
Q1+
Q2+
Q3+
CLR
CLR
CLR
Vcc
counter2.cct
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J-K FF, Counters
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Another Counter Design: Simulation
•Check it with LogicWorks>Build it>Simulate it
•BOUNCING!!
Counter2.cct
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Switch Bouncing
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J-K FF, Counters
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Switch Bouncing
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Digital Switch DebounceCircuit (with SPDT)
• The S-R latch should be made with NAND’s or NOR’s> S-R latch below is made with a S-R latch with active high inputs> Be carefully to pick the proper S-R latch design (2 NANDs or 2 NORs)
D
C
S
R
Q
Q
+5VON
OFF
CLN_IN(H)
CLN_IN(L)
VccS
R
Q
Q
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Bouncing with SPST
0ms 1ms 2ms
6V
4V
2V
0V
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Debounce Circuit Response
6V
4V
2V
0V0ms 1ms 2ms
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J-K FF, Counters
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Wrong Time Scale for Bouncing with SPST
0ns 50ns 100ns 150ns 200ns
6V
4V
2V
0V
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Analog Switch DebounceCircuit (with SPST)
• Not a good solution, but one that will probably work for HC chips.
• Should use a Schmitt Trigger (74’14) with below
Debounced Switch.cct
Vcc
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J-K FF, Counters
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Q & AQ: Can we obtain a cheaper solution using other FF’s?A: Possibly. Some like to use JK FFs because you can make any FF
using JK.Q: But shouldn’t you use T or D -vs- JK because they are slightly faster?A: It is true that a master/student JK is slightly slower. Unless you have a
very high frequency, it is still fast enough!Q: You start the counter at 000. Anywhere else?A: Yes. The Qi’s are pre-cleared to start at 000. Any other state is
relatively simple to obtain using pre-clear/pre-set.Q:Who would build such a counter?
(i.e., to go 0 1 5 4 2 6 7 3 0)A: Nobody (probably). I wanted to show you that it can be designed
using any count sequence you wish. this is a pedagogical example!
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Procedure for Sequential State Machine Design
• Develop a state diagram> Use bubbles for states, arrows for transitions
• Create a next state truth table• Pick FF and add to NSTT• Add outputs to NSTT• Use K-maps to find equations to drive the FF inputs to
generate the required outputs• Design the circuit based on the equations
>Use selected FF’s and other logic gates
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J-K FF, Counters
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State Machine Counter Design Steps
s0000
s1001
s2101
s3100
s4010
s5110
s6111
s7011
Q1+ Q2+ Q3+
(ex) When Q1Q2Q3=000, Q1+=0, Q2+=0, and Q3+=1Q1Q2Q3=101, Q1+=1, Q2+=0, and Q3+=0
Fill up K-Maps for Qi+ using the “original” order{0 1 5 4 2 6 7 3 0}
Next state truth table just adds a Di=Qi+
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State Machine Counter Design Steps
Since using D-FF (because Qi+ = Di) thenD1=Q1+, D2=Q2+, and D3=Q3+. D1 = Q2 Q3, D2 = Q1Q2+Q1Q3+Q2/Q3 , and D3= /(Q1 Q2)
Since the outputs are the Q’s, i.e., Oi=Qi (or Oi=Qi+) O1=Q1, O2=Q2, and O3=Q3
Q+ = D
QD
CLR
SET
Q
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J-K FF, Counters
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State Machine Counter Design w/ SR FF’s
Let’s do it with SR FF’s.
Q
QCLK
S
R
Since we only want to count, Oi=Qi O1=Q1, O2=Q2, and O3=Q3.
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State Machine Counter Design w/ SR, JK, & T FFs
S1 R1 J2 K2 T3
Use Excitation Table to
Complete the Design
[Example] Design the counter{0 1 5 4 2 6 7 3 0}From the previous example we have:
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J-K FF, Counters
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State Machine Counter Design w/ SR, JK, & T FFs
[Example] Design the counter{0 1 5 4 2 6 7 3 0}From the previous example we have:
current state Q1 Q2 Q3 next state Q1+ Q2+ Q3+ S1 R1 J2 K2 T3s0 0 0 0 s1 0 0 1 0 X 0 X 1s1 0 0 1 s2 1 0 1 1 0 0 X 0s2 1 0 1 s3 1 0 0 X 0 0 X 1s3 1 0 0 s4 0 1 0 0 1 1 X 0s4 0 1 0 s5 1 1 0 1 0 X 0 0s5 1 1 0 s6 1 1 1 X 0 X 0 1s6 1 1 1 s7 0 1 1 0 1 X 0 0s7 0 1 1 s0 0 0 0 0 X X 1 1s0 0 0 0 s1 0 0 1 0 X 0 X 1
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State Machine Counter Design w/ SR, JK, & T FFs
R1 = /S1= /(Q2 Q3)
For R1 = f(Qi’s)
S1 = Q2 Q3
For S1 = f(Qi’s)
Each arrow is an entry in the K-map
Recall: Q1 goes 001101100Q1+ goes 01101100
next
start
0 1 5 4 2 6 7 3 0
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J-K FF, Counters
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State Machine Counter Design w/ SR, JK, & T FFs
Do NOT just design for a D-FF and then make it into an SR or JK. Not optimal!This is
a D-FF!
Q Q1
CLK
S
R
Q2Q3
Pulse
R1 = /S1= /(Q2 Q3)
For R1
S1 = Q2 Q3
For S1
Now do similar for Q2 and Q3
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Design an Up/Down CounterLet us design a more general Up/Down Counter
00
1011
01U
U
U UDD
DD
This is a 2-input 4-state system.
* Inputs: D, U
* States: Q1,Q0
D = Down PulseU = Up Pulse
DU 1
D U Q1 Q0 Q1+ Q0+0 0 0 0 0 00 0 0 1 0 1… … … … … …
0 1 0 0 0 10 1 0 1 1 0… … … … … …
1 0 0 0 1 11 0 0 1 0 0… … … … … …
1 1 0 0 X X1 1 0 1 X X… … … … … …
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28-May-21—1:22 PM
24University of Florida, EEL 3701 – File 13© Drs. Schwartz & Arroyo
J-K FF, Counters
EEL3701
48University of Florida, EEL 3701 – File 13
© Drs. Schwartz & Arroyo
Design an Up/Down Counter
00
1011
01U
U
U UDD
DD
• Could add an output when the count is at a certain value> Modify NSTT> Get new equation
D = Down PulseU = Up Pulse
DU 1
Q0+
Q1+
EEL3701
49University of Florida, EEL 3701 – File 13
© Drs. Schwartz & Arroyo
Next State Truth Table• You can make a next state truth table
>Inputs: Q1 and Q0 (the state), U, D>Intermediate outputs: Q1+ and Q0+ (the next state)>Outputs depend on type of flip-flop(s) desired and will
require use of excitation tables and use of Qi & Qi+– If using JK-FFs: Outputs: J1, K1 and J0, K0
– If using D-FFs Outputs: D1, D0
– If using one JK-FF for MSB and one D-FF for LSB Outputs: J1, K1 and D0 This option is very common in exams!
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28-May-21—1:22 PM
25University of Florida, EEL 3701 – File 13© Drs. Schwartz & Arroyo
J-K FF, Counters
EEL3701
50University of Florida, EEL 3701 – File 13
© Drs. Schwartz & Arroyo
The End!