11-1
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Latch-up & Power Consumption
Latch-up Problem
Latch-up condition1 2 >1
GND
Vdd
Rsub
Rw
1
2
I1
I2
VW
11-2
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
V V V
V R V
W on
s sub w
~ .0 6
1 1 2
I
VL
Vdd-GND (I/o drive /pads)
11-3
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Latch-up Solutions
1) Reduce RW , Rsub
2) Many contacts to substrate and well3) Guard rings for transistors with W > 100m
GND
Brown Green
Vdd
4) Epi -layer5) SOI
NMOS PMOS
P+ N+
11-4
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
CMOS Latch-up and It’s Preventions
What is CMOS Latch-up?— CMOS latch-up is a parasitic circuit effect in which both npn and pnp transistors are turned on at the same time. The result of this effect is the shortening of the VDD and VSS lines. Current no longer flows thru the surface channel, but thru the bulk and the junctions, the signal outputs will be latched at an unknown state (0.85~1.5V).
— IDD current will increase until they self-limit or until they result in the destruction of the chip or it’s bonding leads.— Once it is being latched, the only way to restore it’s function is to turn off/on the power.
For example: n-well CMOS epi technology
11-5
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
npn=0.5~10 depends on the distance between n+ to n-wellpnp =50~100 depends on the base width (XJN-well—XJP+)RW =1k~20k depends on N-well sheet resistance and distance between n+and P+
RS =10(for p- / p+ epi) 500-700 for bulk substrate
11-6
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
How to prevent latch-up?
— Reduce current gain of parasitic bipolar transistor npn pnp >1 by suitable vertical process design and horizontal spacings. But for high packing density VLSI, this is difficult to achieve.— Reduce Rs and Rw Rw, by putting more n-well plugs (VDD) or sorrunding n-well with n+ guard rings. Rs, by putting more p+ plugs (ground) in substrate, or with p- /p+ epitaxial layer substrate.— Put top side ring as surface ground contact or use backside contact as ground.— Use trench isolation or silicon on Sapphare Sustrate.— If use epi, n+ —p+ spacing should be greater than the epitaxial thickness.— Special attention on the I / O pad, put guard rings around the buffer circuit.
11-7
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
ESD (Electrostatic Discharge)
concerns in Input Protection Circuit
Human body model Typical input protection circuit
1.5k2000V1000pF
Total energy stored1/2CV2=0.210-3 J
Finger tip
pad
1~2kVDDVDD
Two mechanisms in ESD effect.1. Oxide rupture2. Poly Si resistor, or pn junction burned out.
11-8
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
SiSiO2
SiO2 dielectric strength 6106V/cm(thinner oxide, the dielectric strengtheven higher)if 650Å, BV=39Vif 300Å, BV=25V
The voltage that can build up on a gate may be determined from
Vt
Cg
If charging current 10A, charging time 1s, Cg=0.03pF, then V=330V !!! It will definitely rupture gate oxide.
Conventionally, use two clamping diodes plus one resistor (1~2K), thisresistor is for current limiting purpose, preferably using poly siliconline, but the strength of poly is not as good as that of a diffusion resistor.In high speed circuit, one should watch out the extra RC delay dueto current limiting resistor. The area of clamping diodes will determinepower dissipation capability.
11-9
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Some Layout Precautions on latch-up
1. Separate PMOS. NMOS driver transistors2. P+ guard rings around NMOS and connected to VSS
3. N+ guard rings around PMOS and connected to VDD
PMOS
N+ VDD
NMOS
P+ VSS
PAD
4. Employ minimum area P-well, minimize photo current during transistor.5. Source fingers of PMOS / NMOS prefer to be perpendicular to the current flow direction
Current direction
PMOS
NMOS
11-10
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
6. P-well should hard wired to GND, N-sub should hard wired to VDD, VDD, VSS face each other.
n+ n+
n+ n+P+
P+ P+ P+
tied to VDD by metal from VDD
line, not just got VDD from substrate.P-welltied to GND by metal running over
7. Spacing between p+ and n+ (in p-well) should be minimum (“d” can be zero.) Spacing between n-sub n+ and p+ source should be minimum.
p+ p+ p+n+ n+ n+
d d
P-
n-
11-11
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Potential Well/Sub Contact Problem
p+p+ n+n+
SD p-sub
Signal GND
MisplacedSubstrateContact
Signal (Drain)
p+/p-sub
n+(source)
11-12
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
p+ p+
SD
in out
n-well
CLK
Floating Well Pass Transistor (DON’T FORGET WELL TABS!)
Vdd
CLK
outin IN VG Vwell Vout
0 1(off) u 0 1 0(on) VX 1 (VDD - VD,on) 1(off) VX 1 0 0(on) VX 0 0 1(off) VX 0 01 1(off) VX 1
11-13
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Power Consumption For CMOS
(1) Static dissipation If there is no pseudo NMOS pull-rp or other resistive current path, the only static power dissipation is from junction leakage.
A useful estimate is to allow a leakage current of 0.1nA to 0.5nA per gate at room temperature. Junction Leakage <Example> 106 gate circuits Itotal = 0.5nA 106 =0.5mA Power = Itotal 5V=2.5mW Gate Leakage (10pA/m) (10m) 10M ~1mA Power = 1mA 5V= 5mW
Static Power leakage currents SuppleVoltage
neanowatts inverter
n
1 2~ /
11-14
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Power Consumption in CMOS (cont’d)(2) Dynamic Power
switching) offraction is F (where chip entireFor
sec/
2
110
2
exp
exp
2
2
22
0
/22
/
0
2
fCVFP
WattsJoulesfCVPowerAVG
JoulesCVCV
dtR
VEnergy
R
Vti
dtRtidtpower
timePowerEnergy
RCt
RCt
R
R
11-15
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Dynamic dissipation (cont’d)(a) Switching transient current Psw (small)
VDD
VDD - | Vtp | Vtn
t1 t2 t3
T
trVVP
trttr
V
Vt
t
tVtVwhare
dtVtVT
dttT
VP
tDDsw
DD
t
rDDin
tin
t
t
t
t
mean
DDmeansw
3
21
22
1
3
1
212
2,,
2
22
12
Slow rising/falling results in power dissipation of noise susceptibility (Psw as tr )
Isw t
t
11-16
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
W
MMHzfFP
fFMG
fFMG
60
gates 11003.360
240~4
601
2
Dynamic dissipation (cont’d)
(b) Charging and discharging of load capacitance (dominant)
fVCt
VCV
dt
dVCVVP
fpVCP
DDLDD
LDDLDDDD
DDLd
2
2
0
If the chip function consists of several frequencies, then the totalpower consumption will be:
P C f C f C f Vd total L p L p L p DD 1 1 2 2 3 32
Note: the power dissipation is independent of the device parameters
Ex:
11-17
Integrated Microsystems Lab.
EE372 VLSI SYSTEM DESIGN E. Yoon
Power consumption For NMOS
For NMOS inverter, assume 50% duty cycle
P V
V
V V
WL
C V V
d DD V DD V DD
D sat Dd
TD Dd
L
Ln ox TD DD
OL OH
12
0
12 2
14
2
2
,
For minimum power WL=Wmin, LL=kRLmin