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ECE-777 System Level Design and Automation3D integration. Reconfigurability and testing.
Cristinel AbabeiElectrical and Computer Department, North Dakota State University
Spring 2012
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Outline
• 3D integration– Main idea– Pros and cons– Technologies– Example: IMEC– 3D NoCs
• Reconfigurability, FPGAs, and NoCs• Testing of NoCs
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The communication bottleneck
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3D integration: main idea
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3D integration: pros and cons
• Pros– Increased system integration, smaller form-factor– Enhances interconnect resources
• Improved bandwidth and throughput• Reduced wirelength (WL)
• Cons– Risk of losing performance gain if the increased heat
density leads to degraded performance– Depending on the actual 3D technology, the yield may
decrease– Cost
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3D technologies
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3D technologies• Wire bonded
– Limited to the resolution of wire bonders– Difficult as the number of I/Os– Limited to the chip periphery
• Microbump– Use solder/gold bumps on the surface of the die– Signals need to be routed to the periphery– Parasitic capacitances
• Through silicon via (TSV)– Has the potential to offer the highest interconnect density– Alignment is difficult for many tiers– Risk of attaching a good die to a faulty one yield drops– Heat inside the stack is limiting factor
• Contactless– Capacitive coupling
• Requires tiers to be face-to-face and hence is limited to two tiers
– Inductive coupling
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Basic requirements for a 3D Die stacking Technology
• Electrical requirements:– Low inductance: mainly defined by interconnect length, requires
short connections : favors thin die.– Low resistance: favors thin die and larger diameter, but is not
very critical.– Low capacitance:
• Causes RC-delay and increased fCV^2 power consumption!• Favors thin die, small diameters, small connection pads (high alignment
precision) and thick dielectric isolation liner with silicon.• Most demanding and difficult requirement
• Reliability and thermal requirements:– Low thermo-mechanical stress: metal via <-> Si– Low interface thermal resistance: thin gaps
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Basic requirements for a cost-effective 3D Die stacking Technology
• Minimize process complexity:– Minimize process number of steps– Minimize number of additional lithography steps– Single side wafer processing: lithography, etching,
metallization.• High equipment throughput for each process step• Minimize TSV diameter: avoid loss of active Si
area• Maximize a parallel processing
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3D integration technology example: IMEC
• 3D-Wafer Level Packaging (3D-WLP)– WLP Trough-Si via and micro-bumping– Ultra-thin chip stacking and embedding– 3D interconnects realized at wafer level– 3D interconnects processed post IC passivation– 3D interconnects realized at 0-level packaging interconnect
• 3D-Stacked IC (3D-SIC)– 3D interconnects realized at wafer level– 3D interconnects processed post Front End and prior to
Back End local interconnects– 3D interconnects at intermediate and global interconnect
levels (3D-SIC) or local (3D-IC)
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3D-WLP = 3D-Wafer Level Packaging WLP Trough-Si via and micro-bumping: Concept
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Key technologies
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3D-Wafer Level Packaging (3D-WLP)
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3D-WLP Via Technology Roadmap
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Ultra Thin Chip Embedding
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3D-SIC = 3D-Stacked IC: Concept
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Key technologies
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IMEC roadmap
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3D TSV-based Integrated Circuits
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Summing up…
• Good power and speed• Area overhead is significant• Reliability not ideal (fabrication and aging)• Synchronization is hard (skew minimization across
layers)• Therefore:
– Cost and design effort are not trivial– Not just another dimension for wiring (as of today)– Need a sistematic way to deal with non-ideality
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3D NoCs
• Shorter channel length• Reduced average
number of hops
PEPE
PEPE
Planar link
TSV
Router
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Example topology
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Bottom layer layout
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Area overhead of TSV bundle
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3D NoC test chip
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Design challenges
• Mesochronous Synchronization• Performance Analysis• Reliability Enhancement• 3D NoC Topology Synthesis
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Mesochronous Synchronization
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Performance Analysis
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Reliability Enhancement
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Reference NoC design flow
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3D NoC Topology Synthesis
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Topology Synthesis Algorithm
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Effect of TSV Constraint
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Effect of NoC Frequency
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Case study
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Generated 3D topology
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Design Floorplan
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Comparison with 2D NoC
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Wire Length Distribution
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Other ideas/solutions: bus based
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Multi-layer On-Chip InterconnectRouter Architecture (MIRA)
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Summing up…
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Summing up…
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Outline
• 3D integration• Reconfigurability, FPGAs, and NoCs
• FPGAs background• Configurable SoCs• NoCs prototyping• Reconfigurable NoCs
• Testing of NoCs
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Field-Programmable Gate Arrays (FPGAs)
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FPGAs
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LUT
• Program configuration bits for required functionality
• Computes “any” 2-input function
In Out00 001 010 011 1
2-LUTConfiguration Bit 0
Configuration Bit 1
Configuration Bit 2
Configuration Bit 3
A B
C A
BC=AB
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Programmable interconnects• Interconnect architecture
– Fast local interconnect– Horizontal and vertical lines of various lengths
C LB
C LB
C LB
C LB
C LB
C LB
C LB
C LB
C LB
C LB
C LB
C LB
SwitchMatrix
Switch Matrix
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Switchbox operation
• 6 pass transistors per switchbox interconnect point
• Pass transistors act as programmable switches
• Pass transistor gates are driven by configuration memory cells
After ProgrammingBefore Programming
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FPGA-based design flow
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HDL Synthesis
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Technology mapping
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Place and route
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XILINX ISE
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Configurable System on Chip (CSoC)
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Advantages
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NoC prototyping: CMU
MotionEst. 2
FrameBuffer
InputBuffer
DCT &Quant.
VLE &Out. Buffer
MotionComp.
MotionEst.
Inv Quant.& IDCT
Point-to-point Implementation
InputBuffer R1 R2
DCT &Quant.
VLE &Out. Buffer
Inv Quant.& IDCT
MotionEst.
MotionComp.
FrameBuffer
MotionEst. 2
InputBuffer
DCT &Quant.
VLE &Out. Buffer
Inv Quant.& IDCT
MotionEst.
MotionComp.
FrameBuffer
Bus ImplementationBus Cont.
Unit
Synthesis for Xilinx Virtex II FPGA with CIF (352x288) frames
free
MotionEst. 2
in-house
Xilinx core generator
• To build prototypes, we will likely use a mix of free, commercial, and in-house IPs.
[] Umit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson, "Challenges and Promising Results in NoC Prototyping Using FPGAs," IEEE Micro, vol. 27, no. 5, pp. 86-95, 2007.
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Recore’s reconfigurable system
• Recore Systems– http://www.recoresystems.com
• Reconfigurable computing platforms
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Programmable platform chips
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Many-core architecture
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NoC instead of a bus
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Reconfigurable architectures
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Reconfigurable technology
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Reconfiguration enables run-time mapping
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Montium technology: reconfigurable SoC approach
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Dynamic reconfiguration examples
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ReNoC: A Network-on-Chip Architecturewith Reconfigurable Topology
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Physical architecture
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Topology switches
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Implementation
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Logical topology
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Generalization
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Case study
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Architecture
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Implementation
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Results
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Outline
• 3D integration• Reconfigurability, FPGAs, and NoCs• Testing of NoCs
• References• Improving testing via compression schemes• Other testing techniques
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NoC test references• 1. C. Aktouf, "A complete strategy for testing an on-chip multiprocessor architecture," IEEE Design & Test of
Computers, 19(1), pp. 18–28, January/February 2002.• 2. A. M. Amory, E. Briao, E. Cota, M. Lubaszewski, and F. G. Moraes, "A scalable test strategy for network-on-chip
routers," in Proc. Int. Test Conf., Nov., 2005, paper 25.1• 3. A. M. Amory, K. Goossens, E. J. Marinissen, M. Lubaszewski, and F. Moraes, "Wrapper design for the reuse of
networks-on-chip as test access mechanism," in Proc. European Test Symp., pp. 213–218, May 2006• 4. K. Stewart and S. Tragoudas, "Interconnect testing for network on chips," in Proc. IEEE VLSI Test Symp., pp. 100–
105, April 2006.• 5. C. Grecu, P. Pande, A. Ivanov, and R. Saleh, "BIST for network-on-chip interconnect infrastructures," in Proc. IEEE
VLSI Test Symp., pp. 30–35, April 2006.• 6. T. Bengtsson, A. Jutman, S. Kumar, R. Ubar, Z. Peng, "Off-line Testing of Delay Faults in NoC Interconnects," in Proc.
EUROMICRO Conf. on Digital System Design, 2006, pp.677 - 680• 7. P. Bhojwani and R. N. Mahapatra, "An Infrastructure IP for online testing of network-on-chip based SoCs," in Proc.
Int. Sym. on Quality Electronic Design (ISQED), March, 2007, pp.• 8. K. Petersén and J. Öberg, "Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips," in Proc. IEEE/ACM
Design, Automation and Test in Europe (DATE), April, 2007, pp.• 9. P.S. Bhojwani, R.N. Mahapatra, "Robust Concurrent Online Testing of Network-on-Chip-Based SoCs," Very Large
Scale Integration (VLSI) Systems, IEEE Transactions on Volume 16, Issue 9, pp.1199 - 1209, Sep. 2008• 10. Cota, Érika, Kastensmidt, Fernanda Lima, Cassel, Maico, Hervé, Marcos, Almeida, Pedro, Meirelles, Paulo, Amory,
Alexandre, Lubaszewski, Marcelo, "A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip, Computers," IEEE Transactions on Volume 57, Issue 9, pp. 1202 - 1215, Sep. 2008
• 11. O. J. Kuiken, X. Zhang, and H. G. Kerkhoff, "Built-In Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Oct., 2008, pp.45-53
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NoC test references• 12. M. Sedghi, E. Koopahi, A. Alaghi, M. Fathy, and Z. Navabi, "An NoC Test Strategy Based on Flooding with Power,
Test Time and Coverage Considerations," in Proc. Int. Conf. on VLSI Design, 2008, pp.409-414• 13. X.-T. Tran, Y. Thonnart, J. Durupt, V. Beroulle, and C. Robach, "A Design-for-Test Implementation of an
Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application," in Proc. Int. Symp. on Networks-on-Chip, 2008, pp. 149-158
• 14. J. Dalmasso1, É. Cota, M.-L. Flottes, and B. Rouzeyre, "Improving the Test of NoC-based SoCs with Help of Compression Schemes," in Proc. IEEE Computer Society Annual Symp. on VLSI, 2008, pp. 139-144
• 15. B.-G. Ahn, J.-M. Jung, and J.-W. Chong, "Power-Aware Test Framework for Network-on-Chip," in Proc., Int. Conf. on Systems, 2008, pp. 103-107
• 16. M. Hervé, É. Cota, F. L. Kastensmidt, and M. Lubaszewski, "Diagnosis of Interconnect Shorts in Mesh NoCs," in Proc. ACM/IEEE International Symposium on Network-on-Chip (NoCS), May 2009, pp. 256 - 265.
• 17. B. Vermeulen1, K. Goossens, "A Network-on-Chip Monitoring Infrastructure for Communication-centric Debug of Embedded Multi-Processor SoCs, "in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), May 2009, pp. 183-186.
• 18. A. Eghbal, P. M. Yaghini, H. Pedram, and H. R. Zarandi, "Fault Injection-based Evaluation of a Synchronous NoC Router," in IEEE International On-Line Testing Symposium (IOLTS), June 2009, pp. 212-214.
• 19. J. Raik, V. Govind, and R. Ubar, "Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips," in IET Computers & Digital Techniques, vo. 3, no. 5, pp. 476 - 486, Sep. 2009.
• 20. X.-T. Tran, Y. Thonnart, J. Durupt, V. Beroulle and C. Robach, "Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application," in IET Computers & Digital Techniques, vo. 3, no. 5, pp. 487 - 500, Sep. 2009.
• 21. H.-N. Liu, Y.-J. Huang, and J.-F. Li, "A built-in self-repair method for RAMs in mesh-based NoCs," in IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. -, Apr. 2009
• 22. S.-Y. Lin, C.-C. Hsu, and A.-Y. (Andy) Wu, "A Scalable Built-in Self-Test/Self-Diagnosis Architecture for 2D-mesh Based Chip Multiprocessor Systems," in Proc.IEEE International Symp. on Circuits and Systems (ISCAS), May, 2009, pp. 2317-2320 .
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Improving NoC-based Testing Through Compression Schemes
ATE
SoC
core core core
corecorecore
Router
Test wrapper
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NoC-based testing
• Functional inputs and outputs are used during test, similarly standard SoC testing
• The NoC will be used to transmit data from the ATE to the cores and vice-versa
• Wrappers design– NoC protocol – 1500-compliant
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Approaches
• Preemptive testing– One vector per message, non-reserved paths– Schedule next test-vector packet of a core as soon
as a path is available– Length of the paths travelled by different tests to
the same core can be different• Non-preemptive testing
– All test-vectors in one message– Routing is done using dedicated paths, similar to
circuit switching
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Reuse Model: number of Test Ports
SoC
core core core
corecorecore
ATE = 2W channels
w
w ww w
1 core under test
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Observations
• The main limitation for test time reduction is the number of test ports available
• For non-preemptive testing, the problem is even more serious: the number of input and output test ports must be equal (so that a complete access path can be defined per core)
• If extra pins can be added to the system to reduce test time, a more expensive ATE will be required
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Reuse Model: number of Test Ports
SoC
core core core
corecorecore
ATE = 4W channels
w
w
w w
w
w w
w w
2 cores under test
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DFT Costs
Test Time
P93791 - Test time and DfT cost
0
50000
100000
150000
200000
250000
300000
350000
400000
450000
3/3 4/4 5/5 6/6
Test ports configuration: #INPUTS / #OUTPUT PORTS
Test
tim
e
0
20
40
60
80
100
120
140
160
Nu
mb
er
of
extr
a p
ins
Number of Extra Pins
p93791•103 Inputs •79 Outputs•66 Bidirs•32 Cores
Number of extra pins in the system grows much faster than the corresponding decrease in test time
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ATE Costs
P93791 - Test time and ATE cost
0
50000
100000
150000
200000
250000
300000
350000
400000
450000
3/3 4/4 5/5 6/6
Test ports configuration: #INPUTS / #OUTPUT PORTS
Tes
t ti
me
0
50
100
150
200
250
300
350
400
450
Nu
mb
er o
f A
TE
ch
ann
els
Test Time Number of ATE Channels
p93791•103 Inputs •79 Outputs•66 Bidirs•32 Cores
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Challenge
How to increase the number of test portsIncrease test parallelismMaximize NoC channels usageWithout increasing the ATE cost?
Possible solution:Combine a horizontal compression scheme with a non–preemptive test scheduling approach to reduce test time
Each test port needs less than W bitsÞ Less ATE channels per portÞ Increase the number of possible test portsÞ Increase test parallelism
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Compression Applied to NoC-based Test
router
wrapper
N
W
Core
W
router
wrapper
W
Core
router
wrapper
W
Core
router
wrapper
W
Core
input
W
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Compression Applied to NoC-based Test
Core i
router
wrapper
Communication channels
W
WW
decompressor
Fi
W
NoCFunctional input pins
M
M≤ Fi ≤ W
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Compression Applied to NoC-based Test
Core i
router
wrapper
Communication channels
W
WW
compressor
Fi
W
NoCFunctional output pins
M
M≤ Fi ≤ W
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Compression Applied to NoC-based Test
• Horizontal compression– Test width reduction is the primary goal
• Test vectors compression– Implies extra hardware at NoC-level (decompressor sharing)– May increase cores test time
• Test responses compression– Implies extra hardware at NoC-level – Does not affect core test time
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Horizontal compression• Many published methods• Take advantage of Don’t Care bits (X’s) in test sequence• May increase core Test Time
Virtual scan chains (VTS'00)Illinois scan architecture (DATE'02)Ring generator+phase shifter (ITC'02)Circular scan (DATE'04)Test data mutation encoding (DATE'02)Xor network (DAC'01)Reconfigurable Switch (ITC'01)
Dictionnary based methods (TDAES'03 / & ITC'04)
Netlist dependent
Test data dependent
Specific tool dependent
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Decompressor architecture
W
0 0 0 0Add Cells
OutputShift Register
To scan chains
From ATEM
[1] Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains - DELTA 2006: 295-300
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Compression Applied to NoC Data
packet header
test header
01101
tail
01101
01110
Test pattern: 011010110101110
Original test packet (W= 5)
Compressed test packet (M = 2)
packet header
test header
01
tail
101X0001
packet headerpacket header
test headertest header
packet header
test header
01101
tail
01101
01110
Uncompressed test packet (W = 5)
compressor decompressor
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Compression Applied to NoC Data
CoreOriginalPayload(32-bits)
Comp.32 -> 12
Comp.32 -> 10
1 12 22 30
2 511 949 1198
3 2400 2400 2400
4 5670 5670 5670
5 6050 10976 14000
6 9594 11918 12171
7 3230 4069 5054
8 4462 4462 4462
9 768 1426 1791
10 370 6876 8780
Example for d695 ITC’02 benchmark– uncompressed and compressed data (#flits)
Compression may increase test time of individual cores
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Compression Applied to NoC Data• Conclusion:
• Local increase in test time• Increase test parallelism
• Global test time reduction
System Configuration Test time
1 32-bit input port 36588 cycles
3 input ports of 12, 10, and 10 bits 24395 cycles
32 ATEchannels
d695•32 Inputs •32 Outputs•10 Cores
33%
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Test Scheduling with Compression Define test
packets
Define access paths for each core
Select a packet
Find available access path
Schedule packet
If no path is found, try next core
Select I/O pair that leads to minimal total test time
Packets sorted by probable test time
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Test Scheduling Using Dedicated Paths
Out
Out
d695 from ITC02 benchmark
Channel width=32
3 inputs 10, 10, 12 bits
3 outputs I/O pairs
3/9 6/7 8/4
6 5 4 8 10 7 3 9 2 1
2
3
5 10
6 4
1
79 8
In
In
In
Out
10
10
12
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100
Out
2
3
5 10
6 4
1
79 8
In
In
In
OutOut9869
6
6 5 4 8 10 7 3 9 2 1
108566
108566
10
10
12
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101
154595
Out
2
3
5 10
6 4
1
79 8
In
In
In
OutOut9869
6
68265
5 4 8 10 7 3 9 2 1
68505
10
10
12
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126554
2
3
5 10
6
1
9 8
In
In
In
Out
OutOut9869
6
68265
58294
4
7
4 8 10 7 3 9 2 1
151154
10
10
12
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104348
2
3
5 10
6
1
9 8
In
In
In
Out
OutOut9869
6
68265
58294
4
7
8 10 7 3 9 2 1
114318
140138
10
10
12
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2
3
5 10
6
1
9 8
In
In
In
Out
OutOut9869
6
62065
58294
4
7
104348
10 7 3 9 2 1
1006910
10
10
12
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7 3 9 2 1
2
3
5 10
6
1
9 8
In
In
In
Out
OutOut9869
6
62065
58294
4
7
104348
1006910
133287
10
10
12
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Experimental setup
• SOCIN Network– developed at UFRGS– grid topology– 32-bit channels
• ITC’02 SoC Test Benchmarks – Cores’ placement from design– Random test vectors (80% X's)
• Test time versus ATE cost
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System D695: 3 ports example
System Configuration
Test time (cycles)
Number of ATE input channels
1 input port(32-bit) 36588 32
3 input ports(32-bit each)
15293(-58.2%)
96(+200%)
3 input ports (12, 10, and 10
bits)
24395 (-33.3%)
32(+0%)
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Experimental Results – d695Test time and ATE cost with compression
0
5000
10000
15000
20000
25000
30000
35000
40000
1/1 2/2 3/3 4/4 5/5
I/O configurations
Te
st
tim
e
0
20
40
60
80
100
120
140
160
180
# o
f in
pu
t A
TE
c
ha
nn
els
Test Time Number of ATE Channels
d695•32 Inputs •32 Outputs•10 Cores
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Experimental Results – d695
System
Number of Inputs/Outputs
No Compression With Compression
Test time (cycles)
# of input ATE
channels
Test time (cycles)
# of input ATE
channels
d695
1/1 36588 32 n/a n/a
2/2 19788 64 22737 32
3/3 15293 96 20945 32
4/4 9652 128 18067 32
5/5 9652 160 12853 32
- Same ATE cost- 65% test time reduction
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System
Number of Inputs/Outputs
No Compression With Compression
Test time (cycles)
# of input ATE
channels
Test time (cycles)
# of input ATE
channels
d695
1/1 36588 32 n/a n/a
2/2 19788 64 22737 32
3/3 15293 96 20945 32
4/4 9652 128 18067 32
5/5 9652 160 12853 32
- Test time roughly equivalent- 50% ATE cost reduction
![Page 111: 1 ECE-777 System Level Design and Automation 3D integration. Reconfigurability and testing. Cristinel Ababei Electrical and Computer Department, North](https://reader038.vdocuments.us/reader038/viewer/2022110206/56649d0c5503460f949e00b8/html5/thumbnails/111.jpg)
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Summing up…• Combination of NoC-based testing and
horizontal compression – Reduces SoC test time– Reduces ATE costs
• Compression technique– compliant with SoC Testing
• Future works– seek for the best partition of ATE channels into
test interfaces at NoC-level– test time reduction / area overhead trade-off