double fault tolerant full adder design using fault

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ISSN 2348–2370

Vol.11,Issue.05,

May-2019,

Pages:235-240

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Double Fault Tolerant Full Adder Design using Fault Localization M. SRILATHA

1, M. LAVANYA

2

1Assistant Professor, Dept of ECE, AAR Mahaveer Engineering College, JNTUH, India.

2Assistant Professor, Dept of ECE, Geethanjali Engineering College, JNTUH, India.

Abstract: In the era of advanced microelectronics, rate of

chip failure is increased with increased in chip density. A

system must be fault tolerant to decrease the failure rate. The

presence of multiple faults can destroy the functionality of a

full adder and there is a trade-off between number of fault

tolerated and area overhead. This paper presents an area

efficient fault tolerant full adder design that can repair single

and double fault without interrupting the normal operation of

a system. In this approach, self checking full adder is used

detecting the fault based on internal functionality. This

makes the method efficient in term of area and number of

fault tolerated when compared to the existing designs.

.

Keywords:Single Fault, Double Fault, Self Checking Adder,

Self Repairing, Fault Tolerant, Adder.

I. INTRODUCTION

Fault tolerant designs are mainly used for variety of

operations such defense system, satellite and safety measures

e.t.c. An error occurred in a system may cost several damage

or affect human life also. However, some systems are

reconfigurable, which repair itself. These system can’t be

dismantle and repair that error automatically [1]. In the

current scenario, VLSI circuits become more complex as the

CMOS feature size is scaling in nanometer regime. This

downscaling makes the circuit more compact and sensitive

to the transient faults. Transient fault occurred in the

integrated circuit due to electromagnetic noises, cosmic rays,

cross-talk and power supply noise. In addition to this,

technology scaling further increases the chances of the

presence of permanent fault also [2, 3]. The concept of self

checking and fault tolerant is introduced to deal with the

problem of fault. Self checking indicates the detection of

faults and overlooks the overhead associated with fault

recovery. Most of the self checking approaches re-execute

the instruction for the fault recovery. But, this process

decreases the performance of the system because all faulty

nodes are reexecuted. However, this process does not

guarantee the fault recovery if the fault is permanent [4].

Adder performs a variety of applications in digital system

and have a great importance DSP operations [5-8].

There are two types of faults occur in full adder design

i.e. single fault and double fault. Single fault makes only one

output faulty at a time. However, double fault makes both

the outputs faulty at a time. It is very difficult to detect and

repair the double fault. This makes the design more complex

and requires more area overheads. It makes the fault tolerant

full adder design a matter of great importance [9, 10]. In the

past, many approaches are introduced to design the self

checking full adder using hardware redundancy or time

redundancy. These approaches become successful in

detecting the fault but fails in indicating the exact location of

that fault. Hence, it makes the other module faulty due to the

propagation of the carry. In this paper, we propose a new

fault tolerant design which indicates the single and double

fault with its and automatic fault repairing is also possible in

this design.

II. PREVIOUS DESIGN APPROACHES:

A. Time Redundancy

Redundancy is required in self checking system. Time

redundancy is a self checking approach and is used to detect

the transient fault. This approach used the duplicate

hardware in addition to the original hardware to perform the

same operation at different interval of time [11]. The delayed

clock is provided to the duplicate hardware. The fault is

detected by comparing the outputs of both original and

duplicate hardware. If the outputs of both the hardware are

found to be same, it represents fault-free condition.

However, if the outputs of both the hardware are different, it

represents the faulty condition. The main limitation of this

approach is that it does subsequent

computation to reduce the propagation delay before

comparing the outputs. Hence, if the first computation result

is faulty and it is used for other computations, also makes the

subsequent modules faulty [12].

B. Hardware Redundancy:

The commonly used hardware redundancy approaches are

Triple modular redundancy (TMR) and Double modular

redundancy (DMR) [13, 14]. Triple modular redundancy

approach is used to detect the single fault. As indicates by its

name, it requires three identical modules in parallel to detect

the fault. A fault is detected if anyone output of the modules

are different [15]. But this approach is not capable in

indicating the exact location of the fault. Therefore, this

approach provides the faulty outputs if two single full adder

cells become faulty at a time. This problem can be removed

by increasing the hardware but the resulting design requires

more than 500 % hardware. Double modular redundancy

approach is used to detect the single fault at a time by

M. SRILATHA, M. LAVANYA

International Journal of Advanced Technology and Innovative Research

Volume. 11, IssueNo.05, May-2019, Pages: 235-240

comparing the outputs of operation performed by the

original hardware and duplicate hardware in parallel. This

approach requires 200 % hardware cost whereas the

hardware requirement of TMR is 300%. Hence, this

approach becomes successful to increases the reliability of

the design at the minimum cost [16]. But, fault correction is

not possible in this approach because the voting circuit can

not detect the location of the faulty module [15]. The major

drawbacks of the hardware redundancy approach is that it

requires more than 200% area overhead and can-not detect

double fault at a time [12]. The second problem is that fault

recovery is not possible because it is not able to detect the

faulty module. In addition to this, stuck-at faults are not

detectable in this approach and a problem is creates when

both the modules experience the fault.

C. Self -checking CSA

Fig. 1. 2-bit self checking carry select adder.

In self checking CSA, any single fault and single stuck-at

fault can be detected successfully by 2-pair-2-rail checker

during the online testing. Additionally, self-checking

multiplexers and XOR gates are also used to detect these

faults. This self checking adder is proposed by Vasudevan et

al [17] and shown in Fig. 1. The full adder used in Fig.1 is

designed with 28 transistors. Faults are detected at the

primary outputs by the self checking multiplexers. The

checker has two outputs combinations 01 and 10 and

indicated by Z1 and Z2. The combination of the two outputs

indicates the presence of faults. 00 and 11 indicates the fault

in the full adder cells. However, 01 and 10 indicates that the

full adder cells are fault free The limitations of this design

are that it can detect singlenet fault without indicating its

exact location and also the problem of fault propagation

through carry. Therefore, fault recovery is not possible in

this approach.

D. Self repairing adder

Self repairing adder removes the problem of fault

propagation through carry occurred in the previous self

checking design by indicating the exact location of fault.

This adder is proposed by Mohammad ali akbar et at [4] and

the design of self checking full adder is shown in Fig. 2. The

hardware requirements of self checking adder are full adder

cell, equivalent tester and two XOR gates for self testing the

fault.

(1)

(2)

Fig. 2. Self checking full adder.

The XOR gate (X-1) is used for comparing the sum and

carry outputs generated by the full adder cell. It works on the

principle that sum and carry outputs will be equal when all

the input applied are equal and the sum and carry outputs

will be complement to each other when any of the three

inputs applied is different from remaining inputs. The XOR

gate (X-2) is used to compare the outputs of XOR gate (X-1)

and functional unit [(A’B’C’) +(ABC)]’.The fault is

represented in the form of Ef. If Ef is 0, it shows that there is

a fault and if Ef is 1 it shows the fault free condition. The

main problem of this design is that it fails, if double fault

occur in both sum and carry outputs at a time. In this case, Ef

shows the fault free condition and faulty output propagate to

the next unit through carry and make them faulty.

Fig. 3. Self repairing adder.

The faults detected in self checking process are repaired

by replacing the faulty full adder cell with another redundant

full adder as shown in Fig.3. The working behavior is that

one adder is work as a normal adder while the another adder

is work as redundant adder. The hardware requirements of

this design are two self checking full adders and two

multiplexers. The limitation of this design is that it fails

when double faults occur at a time. In this case, the fault

indication output (Ef) of this design shows that there is no

fault and self repairing design will not work in this in

principle. Therefore, fault is not repaired by the self

repairing adder and full adder shows the faulty output.

Double Fault Tolerant Full Adder Design Using Fault Localization



III. PROPOSED SELF CHECKING ADDER

The output expressions for the sum and carry outputs of the

full adder is shown in equations 1 and 2.

(1)

(2)

Table.1. Truth Table of Self checking full adder design

Fig. 4. Proposed self checking full adder design.

The proposed self checking full adder is based on the

principal given below. (1) The sum output is opposite to the

carry output when vectors of inputs A, B and C are not equal

i.e. (010,100). It shows that except (000) and (111) input

combinations of A, B and C sum output is opposite to the

carry outputs as shown in Table 1. (2) The sum output is

equal to the carry output when input vectors A, B and C are

equal i.e. (000, 111). It shows that for first (000) and last

(111) input combinations of A, B and C, sum output is equal

to the carry outputs as shown in Table 1. The complete

design of the self checking full adder is shown in Fig. 4. The

gates G1 and G2 are used to generate the AND and OR

operation of the input bits B and C as given in equations 3

and 4. AND and OR gates are designed using CMOS logic.

Then the outputs gates G1 and G2 are selected by the

multiplexer under the control of input A to generate the

output C1. The output C1 generates the vectors equivalent to

the carry outputs. Then C1 and Carryout are compared using

XNOR gate G4 as given in equation 5. XNOR gate is

designed using DPL logic. If both are same, it shows the

fault free condition and Fc will be 1. If both are different, it

shows that carry output is faulty and Fc will be 0.

Multiplexers are designed through transmission gates.

(3)

(4)

(5)

To detect the fault in the sum output C1 is inverted using

an inverter. This output along with the output (ABC) is fed

to multiplexer under the control of (A’B’C’ +ABC) to

generate the S1. This output S1 generates the vectors

equivalent to the sum outputs. Then S1 and Sum output are

compared using XNOR gate G5 as given in equation 6. If

both are same, it shows the fault free condition and Fs will

be 1. If both are different, it shows that carry output is faulty

and Fs will be 0.

(6)

IV. PROPOSED SELF REPAIRING FULL ADDER

DESIGN

The proposed self repairing full adder requires negligible

area overhead than the existing designs. The operation of the

proposed design is performed using multiplexers under the

control of Fs and Fc. The output Fs and Fc are generated by

the proposed self checking full adder. The proposed self

repairing design does not need any stand by adder cell that

are

used to replace the faulty adder as used in the previous self

repairing full adder [4]. In this approach, faults are repaired

by using inverter in place of the standby full adder cell as

shown in Fig. 5.

Fig. 5. Proposed self repairing full adder design.

The operation of the proposed design is based on the

control signals (Fs and Fc) provided by the self checking full

adder. If the control signal Fs is 0, it shows that there is no

fault in the sum output and the sum output coming from the

full adder cell will be selected by the multiplexer to generate

the final sum. Multiplexers are designed using transmission

gates. On the other hand, If the control signal is Fs 1, it

shows that there is a fault in the sum output. The faulty sum

output coming from the full adder cell is repaired by using

the inverter. The inverted sum output is further selected by

the multiplexer to generate the final sum. Similarly, if the

control signal Fc is 0, it shows that there is no fault in the

carry output, and the carry output coming from the full adder

cell will be selected by the multiplexer to generate the final

carry. On the other hand, If the control signal is Fc 1, it

shows that carry output is faulty. The faulty carry output is

repaired by using the inverter. The inverted carry output is




further selected by the multiplexer to generate the final

carry. In this way, the faulty adder cell is repaired and

converted into the fault free adder. Therefore, this approach

can repair single and double fault occurs at the sum and

carry outputs at the cost of minimum hardware.

V. SIMULATION RESULTS AND COMPARISON

Fig6. Simulation Results1.







Double Fault Tolerant Full Adder Design Using Fault Localization






VI. COMPARISION WITH EXISTING DESIGNS

The proposed fault tolerant full adder can detect single

and double fault at a time. Hence, the proposed design is free

from the problem of fault propagation through carry.

However the TMR, DMR, self checking [17] and self

repairing full adders [4] have the problem of fault

propagation through carry. The proposed design is capable

of detecting and repairing the transient and stuck-at faults

occur in single and multinet. However, design proposed in

[17], TMR and DMR approaches can’t detect the stuck-at

fault. The proposed fault tolerant full adder does not require

redundant full adder for repairing the faults. However, the

self repairing design [4] requires the redundant adder for

repairing the fault. Hence the area acquired by the proposed

design is less. The proposed design requires an inverter to

repair the faults in place of the redundant adder used in the

existing design. Therefore, the proposed design has

minimum chances of common mode failure than the existing

designs.

VII. CONCLUSION

In our design, A Carry select adder architecture is

presented aiming the multiple fault detection and correction

capability. The proposed design consume lesser area because

instead of replacing the faulty adder with redundant adder,

faulty sum and carry output is inverted using an inverter and

multiplexer. Hence, proposed fault tolerant design consumes

19.5 % lesser area than the self repairing full adder. This

design is capable in tolerating the double fault in addition to

the single fault whereas self repairing full adder can’t detect

the double fault. The comparison results of the proposed

technique are found better that ensure their superior

performance capability when compared to the existing

designs.

VIII. REFERENCES

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[17] D.P. Vasudevan, P.K. Lala and J.P. Parkerson, "Self-

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Author's Profile:

Mrs. M.Srilatha, received the Master of

Technology degree in VLSI Systems Design

from the TKR College of Engineering And

Technology-JNTUH, she received the

Bachelor Of Engineering degree from Bhoj

Reddy Engineering College For Women -JNTUH. She is

currently working as Assistant Professor in Department of

ECE with AAR Mahaveer Engineering College. Her interest

subjects are VLSI Design, Microprocessors and Interfacing,

Microcontrollers, Anolog Electronics, Digital Electronics

and etc, Email: [email protected].

Mrs.M.Lavanya, received the Master of

Technology degree in Embedded Systems

from the Geethanjali Engineering College-

JNTUH, She received the Bachelor Of

Engineering degree from Sphoorthy

Engineering College-JNTUH. Currently

working as Assistant Professor in the Department of ECE

with AAR Mahaveer Engineering College. Her interest

subjects are Embedded Systems, Microprocessors and

Interfacing, Microcontrollers, Analog Electronics, Digital

Electronics and etc, Email: [email protected].

mailto:[email protected]

mailto:[email protected]

double fault tolerant full adder design using fault

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