Solid-State Electronics Vol. 32, No. I I, pp. 965-969, 1989 0038-1101/89 $3.00 + 0.00 Printed in Great Britain. All rights reserved Copyright © 1989 Pergamon Press plc

DOPANT DIFFUSION IN n + /p + POLY GATE CMOS PROCESS

WEN LIN, M. L. CHEN, R. H. DOKLAN and C. Y. Lu AT&T Bell Laboratories, 555 Union Blvd, Allentown, FA 18103, U.S.A.

(Received 13 January 1989; in revised form 6 May 1989)

Abstraet--n +/p + Poly gate CMOS devices were fabricated by a process modified from the "Twin-Tub V" CMOS (n + poly gate) processing technology, using source-drain implants for polysilicon doping. CMOS devices so fabricated show comparable characteristics to devices fabricated by the Twin-Tub V process. The effect of dopant diffusion, both vertical and lateral, was studied in terms of several S/D implant anneal temperatures, 850-950°C. After high-temperature anneal, boron penetration from gate to the silicon resulted in depletion-mode characteristics in the p channel device. Lateral diffusion was observed for all processing conditions used. However, it was shown that when p + and n + poly gates are doped homogeneously above the degenerate level, the compensation effect from the counter doping by the diffused-in dopant does not cause measurable variations in the threshold voltage.

INTRODUCTION

In the scaling of VLSI CMOS circuits into the submicron range, a major issue is the scaling of PMOS transistors. With traditional n + polysilicon gates, the p-channel transistor's threshold voltage is adjusted to an appropriate magnitude with a boron compensation implant. The implant is sufficiently large to counter-dope the surface region of the N-tub, creating the so-called "hurried channel" structure. Such a structure can lead to drain-to-source punchthrough current at short channel lengths[l]. Although the punchthrough resistance can be im- proved by creating a shallow counter-doping layer at the channel region and shallow source/drain junc- tions, another approach to further improve the punchthrough is to use an n ÷ poly gate on the n-channel and a p + poly gate over the p-channel without a threshold adjust implant. Thus both the PMOS and NMOS devices are of surface-channel structure.

In using n-type and p-type polysilicon for the gates of NMOS and PMOS devices, respectively, there is a concern about interdiffusion of the dopants between the two regions through the neighboring junction. The diffusion is especially significant through the shorting overlayer of metal silicide normally used. It is well known that for certain dopants the impurity diffusion rates in metal silicides are enormous[2]. Such lateral diffusion of the dopant can compensate the nominal dopant concentration or even convert the dopant type of the underlying polysilicon of the neighboring gate that shares the common silicide runner, resulting in large variations in threshold voltages of n and p transistors. Furthermore, with boron as p + poly dopant, boron penetration into gate oxide/silicon is also of concern.

Dopant lateral diffusion in n +/p + polygate CMOS was studied previously in CoSi213] and TaSi2[4, 5] cases, but not for TiSi2. These studies for cobalt and

tantalum silicide concluded that lateral dopant diffu- sion occurs after high-temperature post-silicidation anneal (950°C) but that Vt shifts were not observed after low-temperature (800°C) anneal. Electrically and analytically, we have shown in our study using TiSi2, that significant lateral diffusion also occurs after low temperature (800°C) post silicidation anneal, via conditions of gate-electrode work-function varia- tion (incomplete dopant activation/homogenization). The conditions were provided by a range of selected annealing temperatures following source/drain/poly- silicon implant, prior to silicide formation.

The main objectives of this work were: (1) to fabricate PMOS and NMOS transistors with p + and n + poly gates, respectively, by implant doping and (2) to study transistor characteristics and the effect of processing temperature on vertical and lateral dopant diffusion in a TiSi2/poly structure.

EXPERIMENTAL

Seven-micron-thick epitaxial P / p + wafers doped to 1.0-3.0 x 1015 cm -3 were used for processing. 4200 undoped polysilicon was deposited on 150 A gate oxide. A process modified from the Twin-Tub V technology[6] was used for tester fabrication. Figure 1 shows a comparison of the modified process with the Twin-Tub V process. The distinct features of the current process include the following:

(1) In the current work, both n and p channels are surface channel devices. The threshold voltage of both devices were adjusted independently through tub implants. No threshold voltage adjustment im- plants were necessary.

(2) Doping of both n + and p + poly gates were made by implants during source/drain implants, with arsenic and BF 2 respectively.

(3) Following S/D implants, three annealing con- ditions, 850°C, 900°C and 950°C for 30rain in

965

966 WEN LIN et al.

TWIN.TUB V CMOS PROCESS (N + POLY GATE)

BF2 TUB FORMATION

~p ~ ~ + ~ + THIN-OXPATTERNING ~ " - ~ HIPOX FIELO OXIDATION

N-TUB BLANKET VT ADJ. IMPL.

N+ IP + POLY CMOS PROCESS USING SID IMPLANT

FOR POLY GATE DOPING

TUB FORMATION

THIN-OX PATTERNING

HIPOX FIELD OXIDATION p . T 2 L _ _ _ _ _ ~ N-TUB

GATE OXIDATION

, - N + POLY - ~ UNDOPED ~LY DEP.

N + POLY DIFFUSION ~ . . ~ "

DEFINE GATE

BLANKET N-LDD IMPL.

SELECTIVE P-LDO IMPL.

FORMING SIDE-WALL

SPACER

SELECTIVE N + IMPL.

SELECTIVE P+ IMPL.

S-D DOPANT ACTIVATION

SELF-ALIGN SILIClDATION

Fig.

SATE OXIDATION

UNDOPED POLY DEP.

OEFINE DATE

BLANKET N-LDD IMPL.

SELECTIVE P-LDD iMPL.

FORMING SIDE-WALL

SPACER SELECTIVE N + IMPL. (S/O AND POLY SATE)

SELECTIVE P+ IMPL.

(S/D AND POLY GATE)

IMPL. DOPANT ACTIVATION

SELF-ALIGN $1LICIDATION

UNDOPEO / +-,,, r--I _ . r" l

"-i

FTI$ i~ ._ N + POLY

1. Schematic process flow of the current process as compared to the Twin-Tub V processing technology.

N 2 + 2% 02 ambient were used for dopant activation and homogenization. Since S/D anneal is the major high temperature cycle that the wafer receives after the gate is doped, potential exists for vertical and lateral dopant diffusion.

(4) After Titanium deposition, a split was made to skip the salicide formation in order to sort out the contribution by impurity lateral diffusion through salicide during the subsequent thermal processes.

D E V I C E C H A R A C T E R I S T I C S

Figure 2 shows the threshold voltage of n and p channel devices with L / W = 20/20 as a function of the second tub implant dose, for three S/D annealing temperatures. This data shows that for n channel, 950

"

1:1 .11"

1.0 O/' /~ I''S"

O.l / / ,"~

0.+ P.TUII ( ~ + / . .A+ "~ +

0.61 N ' ~ E ( ~ A ~ I ~ P-CH N-CH 0.4 + 960°C

• 0 $O&C 8/D ANNEAL 0.3 • • 860°C 0.2 I I l I l l

2 $ 4 $ 8 7 2 r4 TUB IMPLANT DOSE ( E12 era-s)

Fig. 2. Threshold voltage as a function of second tub implant dose for n and p channel devices.

and 900°C anneals yield the same results while the 850°C anneal gives higher Ft's at all three implant doses. The higher Ft's are speculated to be due to incomplete activation of the implanted arsenic in n + poly at 850°C anneal, as may be evidenced by the diffusion study discussed below. The Vt's for p chan- nel devices annealed at 850°C also show higher values than that of 900°C due to incomplete boron drive-in/activation. At a higher temperature, 950°C, measurements show that all p-transistors have deple- tion-mode characteristics. This behavior indicates that at 950°C, vertical diffusion of boron from the p + polygate causes counter doping of the n-tub surface, resulting in depletion-mode p channel characteristics. Since the second tub-implant doses of 3 x 1012 and 4.5 x 10 t2 cm -2 yield threshold voltages closest to the desired value of 0.5 V for n and p channels, respec- tively, only transistor characteristics pertaining to these implant conditions will be discussed below. The threshold voltages do not display evidence of voltage fall off for both n and p channels with 0.6/am of effective channel length.

The drive capability (Io, at Vds = VGs = 5 V) of n channel and p channel devices are shown in Fig. 3. At 0.6/am of effective channel length, the results show a driving current of 450/aA//am for n channel device and 250/aA//am for the p channel device. The corre- sponding behavior of the devices fabricated by Twin- Tub V CMOS tecnology (n + poly gates) are also shown in the plots for comparison. It is seen that the driving capability of current devices are comparable to that fabricated by Twin-Tub V CMOS process.

Dopant diffusion in n +/p ÷ poly gate CMOS process 967

P-TUO :tEl2 o 900°C $lO ANNEAL • as0oc

------ TWIN-TUB Y " "

.

e e

P-CHANNEL A tt00°C 81D ANNEAL N-TUB 4.5E12 A0$0°C 81D ANNEAL

TWIN-TUB V

~ 0 ' ' ' . . . . . . h ' 0. 0. 0 0.a0 1.00 1.20 1. t,.,m (~m)

1.~0

Fig. 3. Driving current of the present n and p channel devices as compared to that due to Twin-Tub V process.

mFFUmON I u+ N+ I

'°°-I i,°J , I

POLY$1LICON ~ ~

(a)

l I I

TISI2 ---~ • " - ~ ' ~ P+ |

(b) Fox

Fig. 5. Schematic of the transistor-poly connector-diffusion source arrangement, and cross-sections (a and b) showing

possible diffusion paths.

EFFECTS OF DOPANT DIFFUSION

The vertical and lateral dopant diffusion during the proc, ss thermal cycles and its effects on the character- istics of current PMOS and NMOS devices with p + and n + gates, respectively, were evaluated.

A. Vertical dopant diffusion

As was pointed out previously, the 950°C S/D anneal caused the p-channel devices to exhibit deple- tion-mode characteristics, which may be attributed to boron penetration by vertical diffusion from p + poly to the n-tub. Figure 4(a) shows vertical SIMS profiles of B n, and O on a cross-section of a P+ poly/gate oxide/n-tub test structure. It shows a distinct high B u concentration (circled region).beneath the oxide layer (may be identified by oxygen peak). This high concen- tration region is not observed for the structures that received 900°C or 850°C S/D anneal, Fig. 4(h). Note that boron tends to segregate at the poly/oxide/silicon interface, as is evidenced by the B '~ peak. Such segregation behavior would facilitate the penetration into silicon.

B. Lateral dopant diffusion

Figure 5 shows the layout of the tester designed for the lateral diffusion study. There are 13 PMOS transistors and an equal number of NMOS transis- tors with 3 x 20/~m gates. Except for a reference

(a) Cb) 060o0 ANNEAL 10:1~ 880°C ANNEAL

lOU

10 I!

I 10".1

10 II

10 II

10' 0

) ( ARB/I1uLqY )

n B

I ! i ~ 0,4 0.0

DEPTH (MlClqONS)

1o 18 110

10 II

10~1 0 0& 0.4 0.1 DEPTH (MICRONS)

Fig. 4. SIMS profiles of boron and oxygen across p+ poly/gate oxide/silicon structure. (a) 950°C S/D anneal (b)

850°C S/D anneal.

transistor, all other transistor gates are extended and connected (with a variable distance L) to diffusion sources doped with dopants of opposite conductivity. The diffusion sources are polysilicon areas implanted with B or As during S/D implants. Different sizes of implanted sources, ranging from 10000 to 10 gm 2 are provided for different diffusion potential. The two probable diffusion paths in the present process are shown in Figs 5(a) and (b); the diffusion via the first path occurs during the anneal following S/D im- plants, and the second path would be the dominant diffusion path during the thermal processes after TiSi 2 is formed. The lateral diffusion resulting from either path can cause compensation of the gate doping concentration, and possible threshold voltage shift.

Diffusion from large-area diffusion sources. Figures 6-8 show threshold voltage shifts from that of the reference V t (the transistor whose gate is not connected to a diffusion source) as a function of poly connector length, for S/D annealing temperatures of 950, 900 and 850°C, respectively. The data plotted are due to diffusion sources with 10000 #m 2 areas. Com- pared to the area of the gate used, 60gm 2, the diffusion source used here may be considered "infi- nite". Figure 6 shows n channel Vt shifts for 950°C S/D anneal (with TiSi2), and devices that received 950°C and double 950°C anneals but without subse- quent titanium deposition (no TiSi2 on top of polysil- icon). No significant differences can be dicerned among these three conditions. The V t shifts for the 900°C anneal (Fig. 7) are slightly greater than that of 950°C. It is rather surprising, however, to note that V t shifts are significantly greater for the case of 850°C S/D anneal, Fig. 8. The shifts in Fig. 8 are definitely a function of connector length. Logically, these data cannot suggest that dopant lateral diffusion is more significant at a lower temperature. We speculate that the 850°C result is due to incomplete drive- in/activation of the implanted dopants in the adjacent gate. SIMS analysis of B profiles supports this view. The boron profile in Fig. 4(b) shows that a 850°C anneal results in lower boron concentrations (mar- ginal for degenerate) in the poly layer and boron

968 WEN LIN et al.

950°C Slid ANNEAL--WITH TISia LATER

" i 'T [ r .L

- -10 i i i i I i I I i I J I

950 ° SID A N N E A L m N O Ti !'c - s I I I I I I I I I I I I .a

DOUBLE 950 ° ANNEAL ~ NO Ti

- - I I I I I I I I I I I I 0 2 4 Q II 10 20

N-CH TRANSISTOR-TO-OIFFUSION SOURCE DISTANCE (#m)

Fig. 6. Threshold voltage shift for devices (top) received 950°C S/D anneal and subsequent TiSi2 formation, (middle and bottom) received 950 and double 950°C S/D anneal,

respectively, and no subsequent TiSi 2 formation.

pile-up near the polysilicon surface due to incomplete drive-in. A similar situation is expected in n + poly for arsenic. The effect of the incomplete drive-in/ activation is discussed in the following.

The gate dopant concentrations in the current process are at degenerate doping levels, -,, 102° cm -3, when implanted B and As (5 × 1015 and 3 x 1015cm -2, respectively) are uniformly driven-in throughout the 4000 J~-thick poly gates. At these doping levels, compensation by the diffuse-in dopant is unlikely to reduce the gate doping concentration to a non-degenerate level and to cause a shift in threshold voltage. Data from the 950 and 900°C anneals seem to correspond to this condition. How- ever, if a portion of gate doping is lower than the degenerate level, either by incomplete drive-in or only partial activation of the implanted dopant, the dopant compensation by diffuse-in counter doping can change the work function of the polygate/silicon and therefore, a variation in Vt. The 850°C data fit this model. It may be estimated from the available data[7] that when gate doping is at or below the degenerate doping level, for example, 10~Scm -3, a factor of 10 change in doping concentration will

900°C SID ANNEAL

2O

10

0

- -10

- - 20

0 N-CHANNEL

x P -CHANNEL

4

I i I I I I I l I I i I 0 ~' 4 e 8 10 ;J0

TRANSI IFrOR-TO-DIFFUSION 8OURCE D t l r rANCE ( # m )

Fig. 7. Threshold voltage shift as function of connector length for devices received 900°C anneal

850°C SID ANNEAL

10

o

--10

--20

~ A N m ~

V V~(~Am~EL / l oo ~rtl t tource A P.,CHANNEL /

o N.~tANNEL ~ x ~ , . .R } 10000 ,m ' . ou~

I

I I I I I t t I I I I 0 2 4 8 8 10 20

TRANSISTOR-TO-DIFFUSION SOURCE DISTANCE (Fro)

Fig. 8. Threshold voltage shift as function of connector length for devices received 850°C anneal.

cause about 70mV shift in work function. The observed Vt shifts, 7-12mV, would correspond to 10o15% dopant compensation by diffusion.

The current data implies that lateral dopant diffu- sions of B and As from degenerately doped "infinite sources" do occur in the present tester arrangement at all three S/D processing temperatures. In the devices heat treated at 850°C S/D anneal, and subse- quent thermal processes (equivalent to 800°C for 2 h), the "diffusion length" is 7-10 #m. In this case, arsenic diffusion into p channel devices causes slightly greater V t shifts than B diffusion on the n channels, if B diffuses at all. It has been found[2] that, at 500-900°C, the mobility of B in TiSi2 is greatly retarded (essentially immobile) by the formation of highly stable TiB2 in the diffusion process, while As displays a diffusivity in TiSi 2 several orders of magni- tude higher than the corresponding value in the silicon lattice. In terms of these findings, the lower Vt shifts observed in Fig. 8 due to B diffusion may be attributed to the low-mobility nature of B in TiSi2, that the V t shifts are mostly due to B diffusion through polysilicon (i.e. path a of Fig. 4 dominates). In the As case, diffusion via both paths a and b contributes' to the observed V t shifts. However, present data do not indicate overwhelming lateral diffusion via silicide under the post-silicide thermal conditions used. The diffusion length of B and As for the processes with 900 and 950°C S/D anneals are likely to be longer than 7-10 #m. Since it causes no significant dopant compensation and shifts in Vt's, no quantitative estimates can be made.

Lateral diffusion from small-area diffusion source. It is noteworthy that the dopant lateral diffusion from "small area" diffusion sources (100100 #m 2) are in- significant as compared to that due to an "infinite source" (10000 ]~m2). The V t shifts due to a small-area diffusion source for 850°C S/D anneal for a 5 gm connector length are also plotted in Fig. 8 for com- parison. This result implies that inter-diffusion is slight between the neighboring n + and p + gates sharing the common salicide runner. The impact of such inter-diffusion may not be important, especially when the gates are degenerately doped.

Dopant diffusion in n +/p + poly gate CMOS process 969

CONCLUSION

n +/p + Poly gate CMOS devices were fabricated by a process modified from the Twin-Tub V CMOS processing technology, using source-drain implants for polysilicon doping. CMOS devices so fabricated show comparable characteristics to devices fabricated by the Twin-Tub V process. No short channel effects were observed at Le~ of 0.6 and 0.5/zm for p and n channels, respectively. The effect of dopant diffusion, both vertical and lateral, was studied in terms of several S/D implant anneal temperatures. A S/D anneal at 900°C was found to be optimum for the present process. It is shown that an anneal at 950°C causes boron penetration from the gate to the silicon through 150A gate oxide, resulting in depletion- mode characteristics in p channels. Whereas an an- neal at 850°C results in incomplete dopant drive-in or only partial activition of the implanted dopants. Lateral diffusion was observed for all processing conditions used. However, it is shown that when p + and n + poly gates are doped homogeneously above the degenerate level, the compensation effect from the

counter doping by the diffuse-in dopant does not cause measurable variations in the threshold voltage.

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