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Panasonic Semiconductor Singapore A Division of Panasonic Semiconductor Asia Pte Ltd Company Registration No. 197803125E 22, Ang Mo Kio Industrial Park 2, Singapore 569506. Tel: (65)64818811 Fax: (65)64816486 Note: This cover page establishes the Doc No., Title and current status of the attached document. Revision History FMSC-GEN-M1-01 DOCUMENT COVER PAGE Removed physical product marking indications. 4 Remarks Change Details Page S/N Eff Date Rev Issue Eff Date Rev Issue Level SDSC-PSE-AN17808B Doc No. Doc Title Product Specifications for AN17808B Total no. of pages (excluding this page) 1 14 28-MAR-05 4 4-NOV-04 2 1 Added this cover page. - 1 Added this page for leadfree specification. 7A 2 Amended Outer Lead Surface Process & 7A 2 Chip Mounting Method. 28-MAR-05 6 1 Removed this page. 3 15-DEC-04 7 1

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Page 1: DOCUMENT COVER PAGE - Digi-Key Sheets/Panasonic Semiconductors... · DOCUMENT COVER PAGE ... Wire bonding method Wire material Mold material Molding method Fin material SiN, Fe group,

����������Panasonic Semiconductor Singapore A Division of Panasonic Semiconductor Asia Pte Ltd Company Registration No. 197803125E 22, Ang Mo Kio Industrial Park 2, Singapore 569506. Tel: (65)64818811 Fax: (65)64816486

Note: This cover page establishes the Doc No., Title and current status of the attached document.

Revision History

FMSC-GEN-M1-01

DOCUMENT COVER PAGE

Removed physical product marking indications.4

RemarksChange DetailsPageS/NEff DateRevIssue

Eff DateRevIssue LevelSDSC-PSE-AN17808BDoc No.

Doc Title Product Specifications for AN17808BTotal no. of pages(excluding this page)

1

14

28-MAR-054

4-NOV-0421 Added this cover page.-1Added this page for leadfree specification.7A2

Amended Outer Lead Surface Process &7A2Chip Mounting Method.

28-MAR-05 61

Removed this page.3 15-DEC-04 71

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28-MAR-05

Product Specifications

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.FMSC-PSDA-002-01 REV 1

Prepared

Checked

Approved

Eff. Date Eff. Date Eff. Date Eff. Date

AN17808BRef No.

Total Page

Page No.

E

14

6

Package Name

Unit : mm

FP-12S29

.96

± 0.

3

28.0

± 0

.3

20.0

±0.1

0.6

6.4 ± 0.3∅ 3.6 7.7 ± 0.3 7.8 ± 0.3

0.6

± 0.

12.

54

3.5

± 0.

30.25

+0.1

-0.0

5

1.2

± 0.

1

R1.

8

112

29.6

± 0

.3

Lim Fuey Sheen

Kenneth Law

Yasuo Higuchi

12-SIL(FP)

*4

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Chip surface passivation

Lead frame material

Inner lead surface process

Outer lead surface process

Chip mounting method

Wire bonding method

Wire material

Mold material

Molding method

Fin material

SiN,

Fe group,

Ag plating,

Solder plating (98Sn-2Bi),

Ag paste,

Thermalsonic bonding,

Au,

Epoxy,

Transfer mold,

Cu group,

Others ( )

Others ( )

Others ( )

Others ( )

Others ( )

Others ( )

Others ( )

Others ( )

Others ( )

1

2 , 6

PSG,

Cu group,

Au plating,

Solder dip,

Multiplunger mold,

2

6

3

4

4

5

5

Product Specifications

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.FMSC-PSDA-002-01 REV 1

Prepared

Checked

Approved

Eff. Date Eff. Date Eff. Date Eff. Date

Ref No.

Total Page

Page No.

F

14

7A

(Structure Description)

Package FP-12S

AN17808B

-

65

7

7

1

4

2

3

Lim Fuey Sheen

Kenneth Law

Yasuo Higuchi

4-NOV-04

*3

(Leadfree)

Solder (95.5Pb-2.5Ag-2Sn)**Au-Si alloy,

15-DEC-04

*3

**Under RoHS exemption clause, Lead (Pb) in high meltingtemperature type solder (i.e. tin-lead solder alloys containing morethan 85% of lead), is exempted until 2010.

-

*3

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